JPS6443891A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6443891A
JPS6443891A JP62199721A JP19972187A JPS6443891A JP S6443891 A JPS6443891 A JP S6443891A JP 62199721 A JP62199721 A JP 62199721A JP 19972187 A JP19972187 A JP 19972187A JP S6443891 A JPS6443891 A JP S6443891A
Authority
JP
Japan
Prior art keywords
read out
data
bits
memory cell
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62199721A
Other languages
Japanese (ja)
Inventor
Jun Miyake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62199721A priority Critical patent/JPS6443891A/en
Publication of JPS6443891A publication Critical patent/JPS6443891A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To easily output data, read out from a memory cell, to an external part, after processing it at high speed and within an internal part. CONSTITUTION:Four bits, corresponding to an address signal Ay, of the read out data from the memory cell, corresponding to a general purpose data storage area E2, are transmitted to complementary common data lines CD1-CD4. On the other hand, the attribute data of four bits, read out from the memory cell, corresponding to an attribute data storage area E1, is given to an attribute data control circuit 7 through an input output switching circuit 5. Then, when the attribute data, given to the control circuit 7, is a level '1', the general purpose read out data of four bits to be supplied to an output selection circuit 8 is forced to be '0' independently of its read out level, and is given to a main amplifier 9. Thus, a purpose can be attained.
JP62199721A 1987-08-12 1987-08-12 Semiconductor memory device Pending JPS6443891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62199721A JPS6443891A (en) 1987-08-12 1987-08-12 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62199721A JPS6443891A (en) 1987-08-12 1987-08-12 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6443891A true JPS6443891A (en) 1989-02-16

Family

ID=16412507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62199721A Pending JPS6443891A (en) 1987-08-12 1987-08-12 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6443891A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221976A (en) * 1995-02-17 1996-08-30 Nec Corp Semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221976A (en) * 1995-02-17 1996-08-30 Nec Corp Semiconductor memory

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