JPS6470993A - Dual port ram - Google Patents

Abstract

PURPOSE:To eliminate the need of external circuit by providing the first and the second ports in which an address bus, a data bus, a read/write signal input terminal, a chip select signal input terminal and an output enable signal input terminal are respectively independent and passing data and an address from one to the other. CONSTITUTION:At the time of executing a memory read operation from a host processor side, the read/write signal 202 is set to a high level to make a chip select signal 203 and an output enable signal 204 active and control a data select circuit 102 and make access to a memory 101 by an address inputted through the address bus 115 and an internal address bus 109. At the time of executing a memory writing operation, the read/write signal 202 is set to a low level, to make the signal 203 active and the signal 204 inactive, similarly, control the select circuit 102 and make access to the memory 101. At the time of operating from a peripheral side, a similar operation is executed by the use of a read/write signal 302 or the like.