JPS6439692A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS6439692A
JPS6439692A JP62194490A JP19449087A JPS6439692A JP S6439692 A JPS6439692 A JP S6439692A JP 62194490 A JP62194490 A JP 62194490A JP 19449087 A JP19449087 A JP 19449087A JP S6439692 A JPS6439692 A JP S6439692A
Authority
JP
Japan
Prior art keywords
plane
planes
address
ram
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62194490A
Other languages
Japanese (ja)
Inventor
Norio Tanaka
Yasuo Hocchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Micro Software Systems Inc
Original Assignee
Hitachi Ltd
Hitachi Micro Software Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Micro Software Systems Inc filed Critical Hitachi Ltd
Priority to JP62194490A priority Critical patent/JPS6439692A/en
Publication of JPS6439692A publication Critical patent/JPS6439692A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To use a RAM large in capacity as the one easy to use and with a size like the RAM small or medium in capacity, by mapping memory cells in which an internal RAM is divided on the same address, and making its constitution into a plane. CONSTITUTION:The planes 2 are formed by dividing the memory cell 1 into N parts. An address buffer 3 which outputs an equivalent address Ab from an external address bus Ai to each plane is provided, and furthermore, a data buffer which performs the input and output of data (d1...dm) from a common data bus Db to N planes 2 is provided. In each of N planes 2, a memory cell control register 5 which controls read/write in a plane unit by the data bus Db is provided. In such a way, it is possible to perform the simultaneous read/ write of the plane.
JP62194490A 1987-08-05 1987-08-05 Semiconductor memory device Pending JPS6439692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194490A JPS6439692A (en) 1987-08-05 1987-08-05 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194490A JPS6439692A (en) 1987-08-05 1987-08-05 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6439692A true JPS6439692A (en) 1989-02-09

Family

ID=16325390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194490A Pending JPS6439692A (en) 1987-08-05 1987-08-05 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6439692A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328374B1 (en) * 1997-09-30 2002-09-04 닛본 덴기 가부시끼가이샤 Semiconductor memory and its driving method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328374B1 (en) * 1997-09-30 2002-09-04 닛본 덴기 가부시끼가이샤 Semiconductor memory and its driving method

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