JPS5798028A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS5798028A
JPS5798028A JP55175151A JP17515180A JPS5798028A JP S5798028 A JPS5798028 A JP S5798028A JP 55175151 A JP55175151 A JP 55175151A JP 17515180 A JP17515180 A JP 17515180A JP S5798028 A JPS5798028 A JP S5798028A
Authority
JP
Japan
Prior art keywords
bit
data
register
bus line
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55175151A
Other languages
Japanese (ja)
Other versions
JPH02725B2 (en
Inventor
Osamu Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP55175151A priority Critical patent/JPS5798028A/en
Publication of JPS5798028A publication Critical patent/JPS5798028A/en
Publication of JPH02725B2 publication Critical patent/JPH02725B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Abstract

PURPOSE:To remarkably reduce the number of elements and occupied area by them by organizing a register with 1-latch circuit which is connected to a bus line provided with the function of holding data, for every one bit. CONSTITUTION:Each bus line 31, 32, 33 consists of 4 bits, lines 31, 32 and input to an operation device 34 and the line 33 is outputted from the device 34. And 4- bit register 35 oranizing an accumulator consists of registers L0-L3 and the line 33 is connected to its input side and a driver circuit 36 to the output side, respectively. Also, a register 37 consists of 4 bits that assign the address of memory for data, and its input side is connected to the lines 32, 33. On the other hand, its output side is connected to a driver circuit 38. Then, the registers 35, 37 to be connected to the bus line are organized by respective 1-latch circuits 41, 42 and 45, 45 for every one bit and data holding functions 54, 55 are provided for every bit and the data stored in the regiters 35, 37 are stored in the holding functions 54, 55.
JP55175151A 1980-12-10 1980-12-10 Logical circuit Granted JPS5798028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175151A JPS5798028A (en) 1980-12-10 1980-12-10 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175151A JPS5798028A (en) 1980-12-10 1980-12-10 Logical circuit

Publications (2)

Publication Number Publication Date
JPS5798028A true JPS5798028A (en) 1982-06-18
JPH02725B2 JPH02725B2 (en) 1990-01-09

Family

ID=15991157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175151A Granted JPS5798028A (en) 1980-12-10 1980-12-10 Logical circuit

Country Status (1)

Country Link
JP (1) JPS5798028A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237131A (en) * 1985-04-12 1986-10-22 Oki Electric Ind Co Ltd Data bus pre-charging circuit
JPS63314640A (en) * 1987-06-17 1988-12-22 Fujitsu Ltd Barrel shifter circuit
JPH01502624A (en) * 1987-05-01 1989-09-07 ディジタル　イクイプメント　コーポレーション High speed low pin count bus interface
JPH01228019A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Data processor
JPH0239232A (en) * 1988-07-28 1990-02-08 Hitachi Ltd Data processor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237131A (en) * 1985-04-12 1986-10-22 Oki Electric Ind Co Ltd Data bus pre-charging circuit
JPH01502624A (en) * 1987-05-01 1989-09-07 ディジタル　イクイプメント　コーポレーション High speed low pin count bus interface
JPS63314640A (en) * 1987-06-17 1988-12-22 Fujitsu Ltd Barrel shifter circuit
JPH01228019A (en) * 1988-03-08 1989-09-12 Fujitsu Ltd Data processor
JPH0239232A (en) * 1988-07-28 1990-02-08 Hitachi Ltd Data processor

Also Published As

Publication number Publication date
JPH02725B2 (en) 1990-01-09

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