JPS5585951A - Matrix operation circuit - Google Patents

Matrix operation circuit

Info

Publication number
JPS5585951A
JPS5585951A JP15758178A JP15758178A JPS5585951A JP S5585951 A JPS5585951 A JP S5585951A JP 15758178 A JP15758178 A JP 15758178A JP 15758178 A JP15758178 A JP 15758178A JP S5585951 A JPS5585951 A JP S5585951A
Authority
JP
Japan
Prior art keywords
circuit
memory
output
size
graph
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15758178A
Other languages
Japanese (ja)
Other versions
JPS6041789B2 (en
Inventor
Takeshi Masui
Kiyoshi Iwata
Shinichi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53157581A priority Critical patent/JPS6041789B2/en
Publication of JPS5585951A publication Critical patent/JPS5585951A/en
Publication of JPS6041789B2 publication Critical patent/JPS6041789B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)

Abstract

PURPOSE:To enable to process the input graph of arbitrary size, by providing the buffer circuit transfering the video signal in bit serial, register storing the output tentatively, and memory storing the mask of graph processing. CONSTITUTION:The matrix operation circuit consists of the buffer circuits 71-1- 71-M having the shift register function of variable shift amount, and the video signal V inputted to the circuit 71-1 is transferred until the circuit 71-M in bit serial. The output of the buffer circuits are tentatively stored in the registers 73-1- 73-M and the output is connected to the memory 77 via the address selector 76. The memory 77 stores the mask content in response to the desired graph processing predetermined. The initial setting of the data corresponding to each address of the memory 77 is made with the initial set address input line 78 and the initial set data input line 79. The variable shift amount of the buffer circuit is set NXN-bit, size of input graph and the number of circuits is with the size M of the mask used for local operation, allowing to use an arbitrary size.
JP53157581A 1978-12-22 1978-12-22 Matrix calculation circuit Expired JPS6041789B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53157581A JPS6041789B2 (en) 1978-12-22 1978-12-22 Matrix calculation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53157581A JPS6041789B2 (en) 1978-12-22 1978-12-22 Matrix calculation circuit

Publications (2)

Publication Number Publication Date
JPS5585951A true JPS5585951A (en) 1980-06-28
JPS6041789B2 JPS6041789B2 (en) 1985-09-18

Family

ID=15652816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53157581A Expired JPS6041789B2 (en) 1978-12-22 1978-12-22 Matrix calculation circuit

Country Status (1)

Country Link
JP (1) JPS6041789B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6162187A (en) * 1984-09-03 1986-03-31 Fuji Xerox Co Ltd Image processor
JPS61288282A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd Picture filtering device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02130374A (en) * 1988-11-08 1990-05-18 Osaka Shosen Mitsui Senpaku Kk Gas conduction mechanism for box body for refrigerating transportation and box body utilizing the same mechanism

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6162187A (en) * 1984-09-03 1986-03-31 Fuji Xerox Co Ltd Image processor
JPS61288282A (en) * 1985-06-17 1986-12-18 Fujitsu Ltd Picture filtering device

Also Published As

Publication number Publication date
JPS6041789B2 (en) 1985-09-18

Similar Documents

Publication Publication Date Title
CH585436A5 (en)
JPS5585951A (en) Matrix operation circuit
JPS55134442A (en) Data transfer unit
JPS5447438A (en) Control system for scratch memory
JPS55105760A (en) Memory control unit
JPS56156978A (en) Memory control system
JPS55108057A (en) Duplex control unit
JPS5748141A (en) Address conversion system
JPS5542308A (en) Semiconductor memory unit
JPS5650423A (en) Initial value set system in information processor
JPS5556220A (en) Data input system
JPS57169866A (en) Picture magnification varying device
JPS54159135A (en) Sequence control circuit
JPS5533282A (en) Buffer control system
JPS55159226A (en) Data input and output unit
JPS55102046A (en) Logic circuit
JPS5629892A (en) Clear control circuit
JPS57203336A (en) Logical circuit element
JPS5710576A (en) Address selection circuit
JPS55122285A (en) Substitute control system in buffer memory
JPS56168269A (en) Logical device
JPS5384437A (en) Control system for test pattern generation
JPS5538683A (en) Mass-storage static shift register
JPS54108545A (en) Semiconductor device of bit slice type
JPS57132269A (en) Vector arithmetic processor