JPS648591A - Memory ic - Google Patents

Memory ic

Info

Publication number
JPS648591A
JPS648591A JP62164228A JP16422887A JPS648591A JP S648591 A JPS648591 A JP S648591A JP 62164228 A JP62164228 A JP 62164228A JP 16422887 A JP16422887 A JP 16422887A JP S648591 A JPS648591 A JP S648591A
Authority
JP
Japan
Prior art keywords
memory
rom
ram
read
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164228A
Other languages
Japanese (ja)
Inventor
Akira Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62164228A priority Critical patent/JPS648591A/en
Publication of JPS648591A publication Critical patent/JPS648591A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To compactly mount the titled IC by combining a ROM and a RAM on the same chip and integrating the circuits. CONSTITUTION:An address line data line and control line are used in common by combining and integrating the read only memory (ROM) 5, a read/write memory (RAM) 4 and two circuits (memory) on the chip. An address enters as address input buffer 1, and an X decoder 2 and a Y decoder 3 access the RAM memory cell 4 and the ROM memory cell 5 and accessed data is outputted or inputted to and from a data input/output terminal through the input/output buffer 6. Moreover, a control signal for memory read or write from a host is controlled by a control circuit 7. Thus, compact mounting is attained.
JP62164228A 1987-06-30 1987-06-30 Memory ic Pending JPS648591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164228A JPS648591A (en) 1987-06-30 1987-06-30 Memory ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164228A JPS648591A (en) 1987-06-30 1987-06-30 Memory ic

Publications (1)

Publication Number Publication Date
JPS648591A true JPS648591A (en) 1989-01-12

Family

ID=15789105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164228A Pending JPS648591A (en) 1987-06-30 1987-06-30 Memory ic

Country Status (1)

Country Link
JP (1) JPS648591A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526302A (en) * 1993-05-31 1996-06-11 Oki Electric Industry Co., Ltd. Semiconductor memory device having volatile storage unit and non-volatile storage unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663906A (en) * 1993-05-13 1997-09-02 Oki Electric Industry Co., Ltd. Semiconductor memory device having volatile storage unit and non-volatile storage unit
US5526302A (en) * 1993-05-31 1996-06-11 Oki Electric Industry Co., Ltd. Semiconductor memory device having volatile storage unit and non-volatile storage unit
US5544096A (en) * 1993-05-31 1996-08-06 Oki Electric Industry Co., Ltd. Semiconductor memory device having volatile storage unit and non-volatile storage unit

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