JPS5798196A - Memory test system - Google Patents

Memory test system

Info

Publication number
JPS5798196A
JPS5798196A JP55173464A JP17346480A JPS5798196A JP S5798196 A JPS5798196 A JP S5798196A JP 55173464 A JP55173464 A JP 55173464A JP 17346480 A JP17346480 A JP 17346480A JP S5798196 A JPS5798196 A JP S5798196A
Authority
JP
Japan
Prior art keywords
pin
circuit board
printed circuit
gate
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173464A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kawanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55173464A priority Critical patent/JPS5798196A/en
Publication of JPS5798196A publication Critical patent/JPS5798196A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To raise the diagnostic efficiency of a printed circuit board, by connecting one of an outputting circuit or a control circuit, of a controllable gate part provided on one of input/output signal circuits of a control memory, to a terminal part of the printed circuit board. CONSTITUTION:A control terminal 11-1 of a tri-state element 11 to which an output of a control memory 5 to be mounted onto a printed circuit board 1 is connected to a card pin 4-5, and also an OR gate 12 is coupled with an output signal circuit of the element 11, and a read data circuit. In this way, a read-out data of the memory 5 corresponding to an address signal from a pin 401 is outputted from the element 11 as shown by a dotted line, and is fetched from a pin 4-4 through the gate 12.
JP55173464A 1980-12-09 1980-12-09 Memory test system Pending JPS5798196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173464A JPS5798196A (en) 1980-12-09 1980-12-09 Memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173464A JPS5798196A (en) 1980-12-09 1980-12-09 Memory test system

Publications (1)

Publication Number Publication Date
JPS5798196A true JPS5798196A (en) 1982-06-18

Family

ID=15960953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173464A Pending JPS5798196A (en) 1980-12-09 1980-12-09 Memory test system

Country Status (1)

Country Link
JP (1) JPS5798196A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198590A (en) * 1983-04-22 1984-11-10 Hitachi Ltd Magnetic bubble memory device controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198590A (en) * 1983-04-22 1984-11-10 Hitachi Ltd Magnetic bubble memory device controller
JPH0646505B2 (en) * 1983-04-22 1994-06-15 株式会社日立製作所 Magnetic bubble memory system

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