JPS5611697A - Logic circuit device mounting memory - Google Patents

Logic circuit device mounting memory

Info

Publication number
JPS5611697A
JPS5611697A JP8570979A JP8570979A JPS5611697A JP S5611697 A JPS5611697 A JP S5611697A JP 8570979 A JP8570979 A JP 8570979A JP 8570979 A JP8570979 A JP 8570979A JP S5611697 A JPS5611697 A JP S5611697A
Authority
JP
Japan
Prior art keywords
logic
memory section
logic circuit
terminal
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8570979A
Other languages
Japanese (ja)
Inventor
Takashi Ihi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8570979A priority Critical patent/JPS5611697A/en
Publication of JPS5611697A publication Critical patent/JPS5611697A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable single test for a plurality of memories mounted on the logic circuit on the same substrate, by fixing the operating mode of input logic and output logic unit to one memory section with the test signal.
CONSTITUTION: The test signal from the test terminal 8 fixes the logic input unit group 5, logic output unit groups 6, 7 corresponding to the memory section 2-1 connected to the terminal pin 9. Accordingly, the signal is written in the memory section 2-1 from the terminal 9 and the signal read out from the memory section 2-1 is picked up from the terminal 10 connected to the unit goup 6 enable single test for memory section 2-1, even if a number of memory sections 2-1, 2-2... and logic circuit group are mounted on the substrate 1.
COPYRIGHT: (C)1981,JPO&Japio
JP8570979A 1979-07-06 1979-07-06 Logic circuit device mounting memory Pending JPS5611697A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8570979A JPS5611697A (en) 1979-07-06 1979-07-06 Logic circuit device mounting memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8570979A JPS5611697A (en) 1979-07-06 1979-07-06 Logic circuit device mounting memory

Publications (1)

Publication Number Publication Date
JPS5611697A true JPS5611697A (en) 1981-02-05

Family

ID=13866348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8570979A Pending JPS5611697A (en) 1979-07-06 1979-07-06 Logic circuit device mounting memory

Country Status (1)

Country Link
JP (1) JPS5611697A (en)

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