JPS55157039A - Test system for logic unit - Google Patents
Test system for logic unitInfo
- Publication number
- JPS55157039A JPS55157039A JP6464279A JP6464279A JPS55157039A JP S55157039 A JPS55157039 A JP S55157039A JP 6464279 A JP6464279 A JP 6464279A JP 6464279 A JP6464279 A JP 6464279A JP S55157039 A JPS55157039 A JP S55157039A
- Authority
- JP
- Japan
- Prior art keywords
- test
- circuit
- lsi4
- unit
- adequacy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To make easy the test of print board unit mounting complicated LSIs and to reduce the cost and time, by mounting a dummy logic circuit unit and performing a simulation test from the input and output terminal of logic unit.
CONSTITUTION: Considering that the adequacy of the entire print board unit 1 can practically and sufficiently be guaranteed (except the adequacy of LSI4 already proved) when only the adequacy of the peripheral circuits except LSI4 can be tested, the dummy circuit 4' having required and sufficient function only in testing the peripheral circuit is formed, it is mounted in place of the LSI4 for the test of the unit 1. The test data for the peripheral circuit assembling the circuit 4' can considerably be simplified in comparison with the test data for the circuit including LSI4 and sufficient test rate can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54064642A JPS6014377B2 (en) | 1979-05-25 | 1979-05-25 | Logical device test method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54064642A JPS6014377B2 (en) | 1979-05-25 | 1979-05-25 | Logical device test method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55157039A true JPS55157039A (en) | 1980-12-06 |
JPS6014377B2 JPS6014377B2 (en) | 1985-04-12 |
Family
ID=13264116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54064642A Expired JPS6014377B2 (en) | 1979-05-25 | 1979-05-25 | Logical device test method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014377B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4744084A (en) * | 1986-02-27 | 1988-05-10 | Mentor Graphics Corporation | Hardware modeling system and method for simulating portions of electrical circuits |
-
1979
- 1979-05-25 JP JP54064642A patent/JPS6014377B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4744084A (en) * | 1986-02-27 | 1988-05-10 | Mentor Graphics Corporation | Hardware modeling system and method for simulating portions of electrical circuits |
Also Published As
Publication number | Publication date |
---|---|
JPS6014377B2 (en) | 1985-04-12 |
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