JPS5582972A - Testing system of highly integrated circuit - Google Patents

Testing system of highly integrated circuit

Info

Publication number
JPS5582972A
JPS5582972A JP15725178A JP15725178A JPS5582972A JP S5582972 A JPS5582972 A JP S5582972A JP 15725178 A JP15725178 A JP 15725178A JP 15725178 A JP15725178 A JP 15725178A JP S5582972 A JPS5582972 A JP S5582972A
Authority
JP
Japan
Prior art keywords
simulation
simulator
output list
integrated circuit
testing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15725178A
Other languages
Japanese (ja)
Inventor
Midori Nakamae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15725178A priority Critical patent/JPS5582972A/en
Publication of JPS5582972A publication Critical patent/JPS5582972A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an output list compact and readily visible by means of a simulation gate model provided on a simulator for reconnection of the input signal and the output signal of the bidirectional pin.
CONSTITUTION: When a simulation is made to verify the logic design of LSIs, with the switch signal SW turned to 0, to input signals IN and IPIN are given to simulate a model 1b. In this case, a simulator 9b outputs an output list to the line printer. The output list corresponds to the signals of the actual bidirectional pin one to one, hence compact and readily visible. When a simulation model is produced upon the end of the simulation for verifying the logic design, the switch signal SW is turned to 1 to actuate the simulator 9b for testing the LSI.
COPYRIGHT: (C)1980,JPO&Japio
JP15725178A 1978-12-19 1978-12-19 Testing system of highly integrated circuit Pending JPS5582972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15725178A JPS5582972A (en) 1978-12-19 1978-12-19 Testing system of highly integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15725178A JPS5582972A (en) 1978-12-19 1978-12-19 Testing system of highly integrated circuit

Publications (1)

Publication Number Publication Date
JPS5582972A true JPS5582972A (en) 1980-06-23

Family

ID=15645547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15725178A Pending JPS5582972A (en) 1978-12-19 1978-12-19 Testing system of highly integrated circuit

Country Status (1)

Country Link
JP (1) JPS5582972A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847926B1 (en) * 1999-10-29 2005-01-25 Stmicroelectronics Limited Method of distinguishing bidirectional pins

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847926B1 (en) * 1999-10-29 2005-01-25 Stmicroelectronics Limited Method of distinguishing bidirectional pins

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