JPS647636A - Semiconductor integrated circuit device with gate array and memory - Google Patents
Semiconductor integrated circuit device with gate array and memoryInfo
- Publication number
- JPS647636A JPS647636A JP62163543A JP16354387A JPS647636A JP S647636 A JPS647636 A JP S647636A JP 62163543 A JP62163543 A JP 62163543A JP 16354387 A JP16354387 A JP 16354387A JP S647636 A JPS647636 A JP S647636A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- mode
- gate array
- input terminal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To utilize a gate array and a signal pin thereof respectively and effectively, and to test a memory accurately by mounting a changeover means changing over a normal mode and a test mode on the memory side, not the gate array side. CONSTITUTION:A mode-changeover signal input terminal 27 supplied with a mode changeover signal TM, a both-mode combining input terminal 25 supplied with a control signal and an input data at each mode of a normal mode and a test mode, changeover means 21-24, which are set up on the memory 17' side and change over so as to transmit a control signal and an input data acquired through a gate array 15 from the input terminal 25 over the memory 17' and write them to the memory 17' and read them from the memory 17' at the normal mode and directly transmit the control signal and the input data over the memory 17' without through the gate array 15 from the input terminal 25 and write them to the memory 17' and read them from the memory 17' at the test mode by a mode changeover signal, and output terminals 40, 29 respectively extracting output data corresponding to each mode from the memory 17' on the normal mode and the test mode are mounted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62163543A JPS647636A (en) | 1987-06-30 | 1987-06-30 | Semiconductor integrated circuit device with gate array and memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62163543A JPS647636A (en) | 1987-06-30 | 1987-06-30 | Semiconductor integrated circuit device with gate array and memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS647636A true JPS647636A (en) | 1989-01-11 |
Family
ID=15775885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62163543A Pending JPS647636A (en) | 1987-06-30 | 1987-06-30 | Semiconductor integrated circuit device with gate array and memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS647636A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0755889A (en) * | 1993-08-11 | 1995-03-03 | Nec Corp | Logic circuit |
US7846282B2 (en) | 2006-02-02 | 2010-12-07 | Suminoe Textile Co., Ltd. | Automobile floor carpet and method for manufacturing the same |
-
1987
- 1987-06-30 JP JP62163543A patent/JPS647636A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0755889A (en) * | 1993-08-11 | 1995-03-03 | Nec Corp | Logic circuit |
US7846282B2 (en) | 2006-02-02 | 2010-12-07 | Suminoe Textile Co., Ltd. | Automobile floor carpet and method for manufacturing the same |
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