JPS6242359B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention shares data input/output with other address input/output, etc. to reduce the number of pins required for memory and also to reduce the time required for memory testing. belongs to.

[Background of the invention]

Conventionally, as shown in FIG. 1, address pins A ₀ to A ₇ and data input/output D _i and D ₀ pins were separated. However, as memory capacity increases, the chip is divided into multiple subchips, and each of these subchips is provided with _{D 0 and D i} pins.
It is necessary to process these in parallel to shorten the test time when viewed as a single LSI. However, if things continue as they are, the number of D ₀ and D _i pins will increase, and the number of pins required for the package that accommodates the LSI will also increase, resulting in an increase in package dimensions and a drawback in that the packaging density for the user will sharply decrease. .

Although it is completely different from the present invention, there is Japanese Patent Application Laid-open No. 48-35736 as an example using the concept of a kind of common use. Claim 13 on page 354 of the publication and FIG. 32a disclose a technique for sequentially transmitting data such as low-order addresses and WRIT data to a common bus. However, this technology is a common wiring between each chip, and it is natural that they be shared, and unlike the present invention, this technology is completely unrelated in terms of sharing the terminals inside the chips. Furthermore, as a matter of course, there is no concept of a time of testing and a time of actual use. ” [Object of the invention] The present invention aims to eliminate the above-mentioned drawbacks.

The present invention aims to reduce the number of pins of an element and improve packaging density.

The present invention aims to reduce memory testing time.

[Summary of the invention]

In order to achieve the above object, the present invention provides a common address input pin and an information input or output pin, which are used at different times.

[Embodiments of the invention]

Example 1 The present invention will be described below with reference to Examples.

In a normal memory, an address signal is required only for a certain period of time (so-called address hold time T _AH ) after the LSI is selected by inputting an external clock signal to the LSI. Also usually D
The period during which the signals _i and D ₀ are valid is after T _AH . Therefore, the address pin, D ₀ , and D _i pins may be used in common, and the roles of the pins may be changed over time. Figure 2 shows an example for that purpose, where D ₀ and D _i are respectively
Commonly used by A ₀ and A ₁ , a kind of clock signal φ ₀ , φ
This is an example in which gates Q ₀ , ₀ , Q _{1 , 1} are controlled by φ 1 and φ ₂ . During the period when the address signal is valid, φ
It is sufficient to turn on only ₀ , turn on only _φ1 during the period when D ₀ is valid, and turn on only _φ2 during the period when D _i is valid. This means that D _i and D ₀ are also provided with only the number of pins A ₀ to A ₇ .

Embodiment 2 Normally, D _i and D ₀ do not need to be valid at the same time, so as shown in FIG. 3, the clock signals φ ₀ , φ ₁ ,
By controlling gates Q ₂ , Q ₃ , Q ₄ with φ ₂
One pin can also be shared by A ₀ , D ₀ , and D _i . Note that φ ₀ to _{φ 2} do not have to be applied externally, but may be signals generated inside the chip CHIP. With this configuration, the same number of D ₀ as the number of address input terminals can be provided, which is particularly effective.

Embodiment 3 This embodiment is a case in which a differential output used in a general dynamic random access memory is provided.

Figure 4 shows the differential signal output D ₀ from one LSI,
This is an example in which ₀ is output. 1 pin
It can be shared between D ₀ and A ₁ , and between ₀ and A ₀ .

Embodiment 4 This embodiment aims to increase the number of outputs when testing a memory and shorten the test time.

Figure 5 shows that only when testing memory LSI,
This is an example in which the external power supply voltage Vcc (5V during normal use) is set to 0V so that the address _A0 and the data output _D0 ', which is valid only during testing, are output in common.

Here, DB is a well-known push-pull type TTL level D ₀ buffer circuit, and in actual use, Q ₉ and Q ₁₀ are always
One of them will turn on. As explained above, the ADS is a circuit that switches between the data output D ₀ ' from the MA and the address signal.
Since Vcc=5V during normal actual use, _φ1
Even when Q11 is turned on, the gate of _Q11 is at a low voltage (N-
MOS example), so Q ₁₁ is turned off. (Here, negative logic is used, and the output is "0" only when the input to the NAND is logic "1", "1". Therefore, the potential is "L", "L" input It becomes “H” only when , and the gate of Q ₁₁ is φ ₁ ,
Turns on when the potential of Vcc is low. ) Therefore ADS always acts as just a logic gate for A ₀ . On the other hand, D ₀ ′ from MA is output to the outside as D ₀ at a normal TTL level by DB. Also, when testing whether the memory (CHIP) is a good product, set Vcc to 0, set D ₀ as an invalid terminal, and instead set Q ₁₁ in ADS to φ ₁ of negative logic “1”. Since conduction occurs, ADS
Output D ₀ ′ from MA and address A ₀ input to MA
It functions to switch between.

The idea of this embodiment is that, as shown in FIG _.
This is effective when dividing into MA ₃ and processing outputs D ₀₀ ′ to _{D 03} ′ from each memory array MA ₀ to _{MA 3} in parallel to shorten test time. In other words, in normal use, among the four outputs D ₀ ′ to D ₃ ′, the DS has a decoding function using two address signals.
One data output D ₀ selected in is used.
On the other hand, when testing LSI, set Vcc to 0V,
4 data outputs D ₀ ′ shared with address pins
Use D ₃ ′.

〔Effect of the invention〕

From the above, by sharing data input/output signals and address pins, the number of required pins can be reduced.
It is obvious that the number of pins required for the LSI package is reduced, and as a result, the packaging density for the user is improved. Note that it is also obvious that the data signal can be shared with other signals other than the address signal. Also, the fourth
In FIGS. 5 and 6, only the address signal and D ₀ are shared, but as is clear from FIG. 3, the address signal and D _i or the address signal, D _i and D ₀ can be shared.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example, and FIGS. 2 to 6 show an embodiment of the present invention in which data input/output is shared with pins for other functions. Explanation of symbols, CHIP: Chip, SA: Sense amplifier, MA, MA ₀ ~ _{MA 3} : Memory array, V: Power supply voltage, DS: Data output from subarray D ₀₀ ~
A circuit that selectively outputs only one piece of data in D ₀₃ using an address signal.

Claims (1)

[Claims] 1 A memory array having a plurality of memory cells on a single chip, a plurality of address terminals and a plurality of information input or output terminals, and at least two of the plurality of address terminals are connected to the input or output terminals. In a memory which is commonly used as a terminal, and whose control is a signal generated inside the chip, and has means for switching the address terminal and the input or output terminal based on the signal, the input or output terminal, the A memory characterized in that an address terminal and a terminal that shares both are provided on the single chip.