JPS6439699A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To offer a fault tolerant memory device and to realize high reliability, miniaturization, and low cost, by arranging plural memory matrices on a semiconductor chip, and outputting is output via a logic circuit such as a majority circuit, etc. CONSTITUTION:In the memory matrices 1, 2, and 3, a large number of memory cells are arranged regularly, and an address signal An is connected to respective memory matrices. A chip select signal, the inverse of CS with selects the memory device and a write signal, the inverse of WR which controls write are prepared, and write control via a logic gate 4 and readout control via a logic gate 5 are performed. The write of the data on the matrices 1, 2, and 3 are performed commonly by a data entry Din, and read out results are inputted to a logic circuit 6, respectively, and after arithmetic operations are applied on them, they are outputted via a buffer 7. The arithmetic operation is performed by a method of majority of the one where an error signal is outputted even when one error is generated. Thus, the miniaturization and the reliability of the device can be obtained.