JP2008186515A - Semiconductor memory and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a defect ratio of memory parts can be suppressed low even if the defect ratio of individual memory cells are high and properties of individual memory cells are changed after shipping of products, and electronic equipment using the same. <P>SOLUTION: The semiconductor memory has memory cell groups 101 to 10m of (m) sets (m>n) consisting of two memory cells 200, 201 to store (n) bits. One kind of state out of three kinds of states indicating that they are data "0", data "1", and a replacement memory cell group is stored in each of the memory cell groups 101 to 10m, is stored. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and an electronic device, and more particularly, to a semiconductor memory device including a nonvolatile memory cell such as a flash memory cell having a function of storing information by utilizing a change in cell current, and the same It relates to the electronic equipment used.

  In recent years, non-volatile semiconductor memory devices such as flash memories and ferroelectric memories have been widely used as semiconductor memory elements for data storage or code (program) storage such as mobile phones and digital cameras. ing. Furthermore, it is considered to mount a nonvolatile memory on a glass substrate such as a liquid crystal panel.

  Such a non-volatile memory cell stores information by utilizing the difference in cell current according to the storage state. However, due to the structure, there is a difference in writing time between individual memory cells, or erasing. There are large variations in cell characteristics, such as cell current variation. In particular, since memory cells formed on a glass substrate have a large variation in characteristics, it is necessary to select memory cells having extremely poor characteristics as defective products. However, it is very inefficient to make an integrated liquid crystal panel part defective due to a defect occurring only in the memory part.

  In addition, individual memory cells are subject to disturbance (disturbance due to access to other memory cells), endurance (degradation of the memory cell's rewrite characteristics due to an increase in the number of rewrites), retention (changes in stored information due to changes in temperature, changes over time, etc.). Since the influences such as the holding characteristics) are different from each other, there arises a problem that the product causes a defect after it enters the market.

  As a typical solution to a conventional memory cell failure, a semiconductor memory device (see, for example, JP-A-2002-74979 (Patent Document 1)) that replaces a redundant memory cell using a fuse, or a nonvolatile memory is used. There is a semiconductor memory device (see, for example, Japanese Patent Laid-Open No. 2002-358794 (Patent Document 2)) that is used and replaced with a redundant memory cell.

  However, since the semiconductor memory device using the conventional fuse needs to cut the fuse with a laser after the wafer test, the throughput is poor, and the area of the fuse portion increases the chip area.

In addition, the semiconductor memory device using the conventional nonvolatile memory has poor repair efficiency if the yield of the nonvolatile memory itself storing the redundant replacement address is poor. Further, since the characteristics of the nonvolatile memory fluctuate after shipment, aftercare such as rewriting is necessary.
Japanese Patent Laid-Open No. 2002-74979 JP 2002-358794 A

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory that can keep the memory unit defective rate low even if the defective rate of individual memory cells is high or the characteristics of the individual memory cells change after product shipment. An object is to provide an apparatus and an electronic apparatus using the same.

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
In order to store n bits, the memory cell group includes m sets (m> n) of k memory cells (n, k, m are natural numbers),
One of at least three states is stored in each of the memory cell groups.

  According to the semiconductor memory device having the above-described configuration, one of the at least three states is stored in each of the memory cell groups, so that 1-bit data “1” stored in one memory cell group “ In addition to the two types of states “0” and “1”, one type of state indicating that the memory cell group is defective can be stored in the memory cell group. Therefore, when normal, n bits of information are stored in n memory cell groups. For example, if one of the n memory cell groups is defective, the defective memory cell group It is possible to store n bits by replacing with one of the (mn) memory cell groups. As a result, even a failure of (mn) memory cell groups can be tolerated. Therefore, even if the failure rate of each memory cell is high or the characteristics of each memory cell fluctuate after product shipment, the memory The defect rate of the entire cell group can be kept low, the yield at the time of shipment can be improved, and the information of the memory cell can be read accurately for a long period after the product is shipped. Further, since it is not necessary to store the address of the defective memory cell group in the replacement address memory cell as in the prior art, the defective rate of the replacement address memory cell itself does not affect the defective rate of the product.

  In one embodiment of the semiconductor memory device, the memory cell group includes data “0”, data “1”, and one of three states indicating a replacement memory cell group. Remember.

  Here, the replacement memory cell group is one that has been replaced with another memory cell group due to a defect.

  In one embodiment, each of the memory cell groups includes two memory cells.

  According to the above-described embodiment, the memory cell group that needs to store at least three types of states is configured by only two memory cells that are at least necessary, so that the circuit scale can be reduced.

In the semiconductor memory device of one embodiment,
The memory cell group is
A first memory cell and a second memory cell;
As a state of the data “0”, “0” is stored in the first memory cell and “1” is stored in the second memory cell,
As the state of the data “1”, “1” is stored in the first memory cell and “0” is stored in the second memory cell.
As a state indicating the replacement memory cell group, “0” or “1” is stored in both the first memory cell and the second memory cell.

  According to the above-described embodiment, even if there are both “erase failure” and “write failure” in the memory cell failure, the failure rate can be reduced to a very low level.

  In one embodiment of the semiconductor memory device, each of the memory cell groups includes six memory cells.

  According to the above embodiment, each of the six memory cells of the memory cell group is divided into three, and at least three memory cells necessary for suppressing defects after shipment by a majority circuit or the like are the same as “000”. By using it for storing “or“ 111 ”, it is possible to increase redundancy and improve reliability.

In the semiconductor memory device of one embodiment,
The memory cell group is
It is composed of first to sixth memory cells,
As the state of the data “0”, “0” is stored in all of the first to third memory cells and “1” is stored in all of the fourth to sixth memory cells,
As the state of the data “1”, “1” is stored in all of the first to third memory cells and “0” is stored in all of the fourth to sixth memory cells,
As a state indicating the replacement memory cell group, “0” or “1” is stored in all of the first to sixth memory cells.

  According to the above-described embodiment, even if there are both “erase failure” and “write failure” in the memory cell failure, the failure rate can be reduced to a very low level.

In the semiconductor memory device of one embodiment,
A first majority circuit to which outputs of the first to third memory cells are connected;
And a second majority circuit to which the outputs of the fourth to sixth memory cells are connected.

  According to the embodiment, the first majority circuit to which the outputs of the first to third memory cells are connected, and the second majority circuit to which the outputs of the fourth to sixth memory cells are connected; As a result, the redundancy can be improved and the reliability can be improved, and the minimum three memory cells necessary for the majority circuit for suppressing defects after shipment are used for storing the same “000” or “111”. The circuit scale can be reduced.

  An electronic apparatus according to the present invention includes any one of the above semiconductor memory devices.

  According to the above configuration, the defect rate of the memory portion can be kept low with a relatively simple configuration, the yield at the time of shipment can be improved, and the information of the memory cell can be accurately read out for a long period after the product is shipped. Since the above-described semiconductor memory device is provided, a highly reliable electronic device can be obtained.

  As is apparent from the above, according to the semiconductor memory device of the present invention, even if the defect rate of each memory cell is high or the characteristics of each memory cell fluctuate after product shipment, a plurality of memory cells 1 bit data is stored in the memory cell group constituted by the above, and when there is a defect, a method of replacing with a spare memory cell group is used, so that the defect rate of the memory portion can be kept low, The yield of the memory cell can be improved, and the information of the memory cell can be accurately read out for a long period after the product is shipped.

  Further, according to the electronic device of the present invention, a highly reliable electronic device can be realized by using the semiconductor memory device.

  Hereinafter, a semiconductor memory device and an electronic apparatus according to the present invention will be described in detail with reference to embodiments shown in the drawings.

(First embodiment)
FIG. 1 shows a semiconductor memory device according to the first embodiment of the present invention. This semiconductor memory device includes m sets of memory cell groups 101 to 10 m each including two memory cells 200 and 201. The information to be stored is n bits and is configured such that m> n (n, k, m are natural numbers). Therefore, normally, if n bits of information are to be stored, it is sufficient to have n memory cell groups 101 to 10n. It has spare memory cell groups 10n + 1 to 10m.

  However, if there is a defective memory cell group, the method of inactivating it with a fuse or the like requires that the fuse be cut with a laser or the like after the wafer test, resulting in poor throughput and the area of the fuse portion. Increases the chip area. Alternatively, there is a method of replacing with a good memory cell group and storing the address of the replaced defective memory cell group. However, if the yield of the memory cell itself storing the replacement address is poor, the repair efficiency is poor.

  Therefore, according to the present invention, spare memory cell groups 10n + 1 to 10m are provided, and a state indicating a defective memory cell group is written to the memory cell group in addition to the data “0” and data “1” states. . Each memory cell group is configured as shown in FIG. Here, as the simplest example, two memory cells 200 and 201 are used.

  A series of flow of the write operation is as shown in the flowcharts of FIGS. 2A and 2B, for example. Here, it is assumed that the memory cells of all the memory cell groups are erased to “0” (normally, the nonvolatile memory is shipped in an erased state). In addition, i = 1 and j = 1 are set as initial settings.

  First, when the writing process is started, the i-th (= 1 to n) data is written in step S1 shown in FIG. 2A, and the process proceeds to step S2 to write to the j-th (= 1 to m) memory cell group. . Here, in the first time of steps S 1 and S 2, the first data is written into the first memory cell group 101.

  Next, the process proceeds to step S3. If it is determined that the data “0” is written, the process proceeds to step S4. On the other hand, if it is determined that the data “0” is not written, the process proceeds to step S21 in FIG.

  In step S4, it is determined whether or not the first memory cell 200 is “0”. If it is determined that the first memory cell 200 is “0”, the process proceeds to step S5.

  Next, “1” is written to the second memory cell 201 in step S5, and the process proceeds to step S6 to determine whether or not the second memory cell 201 is “1”. If it is determined that the data has been successfully written, the process proceeds to step S7 assuming that the data has been normally written.

  Then, i is incremented and j is incremented in step S7, and the process proceeds to step S8. If it is determined that i> n, this processing is terminated as the writing of the first data to the n-th data is successful.

  On the other hand, if it is determined in step S8 that i> n is not satisfied, the process proceeds to step S9 to determine whether j> m is satisfied. If it is determined in step S9 that j> m, the process is terminated as a writing failure, whereas if it is determined that j> m is not satisfied, the process returns to step S1.

  If it is determined in step S4 that the first memory cell 200 is not “0”, the process proceeds to step S11 and “1” is written in the second memory cell 201.

  Next, the process proceeds to step S12. If it is determined that the second memory cell 201 is “1”, the process proceeds to step S13. On the other hand, if it is determined that the second memory cell 201 is not “1”, the write has failed. This process is terminated.

  Then, j is incremented in step S13, and the process proceeds to step S14. If it is determined that j> m, the process is terminated as the writing has failed, whereas if it is determined that j> m is not satisfied, the process returns to step S2.

  2B, when it is determined that the second memory cell 201 is “0”, the process proceeds to step S22, “1” is written to the first memory cell 200, and the process proceeds to step S23.

  Next, if it is determined in step S23 that the first memory cell 200 is “1”, the process proceeds to step S7 in FIG. 2A. On the other hand, if it is determined that the first memory cell 200 is not “1”, the step in FIG. Proceed to S13.

  On the other hand, if it is determined in step S21 that the second memory cell 201 is not “0”, the process proceeds to step S24, “1” is written to the first memory cell 200, and the process proceeds to step S25.

  Next, if it is determined in step S25 that the first memory cell 200 is “1”, the process proceeds to step S13 in FIG. 2A. On the other hand, if it is determined that the first memory cell 200 is not “1”, the writing has failed. As a result, the process is terminated.

  Thus, in the case of data “0”, “0” is stored in the first memory cell 200 and “1” is stored in the second memory cell 201, and in the case of data “1”, the first “1” is stored in the memory cell 200 and “0” is stored in the second memory cell 201.

  If the first memory cell 200 or the second memory cell 201 is defective and a desired state cannot be stored, both the first memory cell 200 and the second memory cell 201 are set to “0” or As “1”, it is distinguished from the state of the data “0” and the data “1”.

  Then, desired data is written into the next memory cell group. Here, the memory cell failure is defined as “write failure” in which “1” cannot be written and “0” is fixed, and “erase failure” in which “1” is fixed without being erased to “0”.

と表される。 Now, assuming that the erase failure rate (including the probability that the memory cell is not in the erased state) is e and the write failure rate is p, the complete failure rate ε0 (FIG. 2A, FIG. 2B “probability of“ write failure ”)
ε0 = p · e
It is represented by Further, the defect rate ε1 (probability of passing through “j = j + 1” in step S13 in FIG. 2A and becoming a defective memory cell group) that the memory cell group can be redundantly replaced is:
ε1 = p + e−2p · e
It is. Further, when there are m sets (m> n) of memory cell groups for n-bit storage, the failure rate ε2 of the entire m sets after redundant replacement is expressed as ε3. When

It is expressed.

Here, if e = p = 1%,
Complete defect rate ε0 = 0.01%
Defect rate ε1 = 1.98%
It becomes. Since ε0 << ε1, the above equation can be set to ε3≈ε1. For example, when the number of bits to be stored is 8 bits (n = 8), two (3) memory cell groups are provided, and m = If it is 10, the overall defect rate ε2≈0.084%, which can be suppressed to a very low defect rate.

  If m = 8 without redundant replacement, the overall failure rate is 14.78%, so the failure rate can be reduced to approximately 1/170.

  Alternatively, if three sets of memory cells are provided and m = 11, the overall defect rate ε2≈0.000045% can be suppressed to a lower defect rate, which is approximately 3250 compared to the case where no redundant replacement is performed. The defect rate can be reduced by a factor.

  According to the semiconductor memory device having the above-described configuration, even (m−n) memory cell groups out of the m sets of memory cell groups 101 to 10m can be tolerated. Therefore, even if the defect rate of each memory cell is high. In addition, even if the characteristics of individual memory cells fluctuate after product shipment, the failure rate of the entire memory cell group can be kept low, and the yield at shipment can be improved. The information in the memory cell can be read out. Further, since it is not necessary to store the address of the defective memory cell group in the replacement address memory cell as in the prior art, the defective rate of the replacement address memory cell itself does not affect the defective rate of the product.

  In addition, since each of the memory cell groups 101 to 10m that need to store three types of states is composed of only the two minimum required memory cells 200 and 201, the circuit scale can be reduced.

  Further, as the state of data “0”, “0” is stored in the first memory cell 200 and “1” is stored in the second memory cell 201, and the state of data “1” is “1” is stored in the memory cell 200 and “0” is stored in the second memory cell 201, and the first memory cell 200, the second memory cell 200, By storing both “0” or “1” in the memory cell 201, even if the memory cell has both “erase failure” and “write failure”, the failure rate can be reduced to a very low rate. .

(Second embodiment)
FIG. 3 shows a semiconductor memory device according to the second embodiment of the present invention. The semiconductor memory device includes m sets of memory cell groups 301 to 30m each including six memory cells 400 to 405, and stores n bits as information to be stored, where m> n. In addition to the states of data “0” and data “1”, a state indicating a defective memory cell group is written to the memory cell group in the same manner as in the first embodiment.

  The second embodiment differs from the first embodiment in that each memory cell group includes six memory cells 400 to 405 as shown in FIG.

  A series of flow of the write operation is as shown in the flowcharts of FIGS. 4A and 4B, for example. Here, it is assumed that the memory cells of all the memory cell groups are erased to “0” (normally, the nonvolatile memory is shipped in an erased state). In addition, i = 1 and j = 1 are set as initial settings.

  First, when the writing process is started, the i-th (= 1 to n) data is written in step S31 shown in FIG. 4A, and the process proceeds to step S32 to write to the j-th (= 1 to m) memory cell group. . Here, in the first step of steps S31 and S32, the first data is written into the first memory cell group 101.

  Next, the process proceeds to step S33. If it is determined that the data “0” is written, the process proceeds to step S34. If it is determined that the data “0” is not written, the process proceeds to step S51 in FIG. 4B.

  In step S34, it is determined whether or not the first to third memory cells 400 to 402 are “0”. If it is determined that the first to third memory cells 400 to 402 are “0”, the process proceeds to step S35. move on.

  Next, “1” is written in the fourth to sixth memory cells 403 to 405 in step S35, and the process proceeds to step S36 to determine whether or not the fourth to sixth memory cells 403 to 405 are “1”. If it is determined that the fourth to sixth memory cells 403 to 405 are “1”, it is assumed that data has been normally written, and the process proceeds to step S37.

  Then, i is incremented and j is incremented in step S37, and the process proceeds to step S38. If it is determined that i> n, this processing is terminated as the writing of the first data to the n-th data is successful.

  On the other hand, if it is determined in step S38 that i> n is not satisfied, the process proceeds to step S39 to determine whether j> m is satisfied. If it is determined in step S39 that j> m, the process is terminated as a writing failure, whereas if it is determined that j> m is not satisfied, the process returns to step S31.

  If it is determined in step S34 that the first to third memory cells 400 to 402 are not “0”, the process proceeds to step S41, and “1” is written to the fourth to sixth memory cells 403 to 405.

  Next, the process proceeds to step S42, and if it is determined that the fourth to sixth memory cells 403 to 405 are “1”, the process proceeds to step S43, while the fourth to sixth memory cells 403 to 405 are “1”. If it is determined that this is not the case, it is determined that the writing has failed, and the process is terminated.

  Then, j is incremented in step S43, and the process proceeds to step S44. If it is determined that j> m, the process is terminated as a writing failure, whereas if it is determined that j> m is not satisfied, the process returns to step S32.

  4B, if the fourth to sixth memory cells 403 to 405 are determined to be “0”, the process proceeds to step S52, and “1” is set to the first to third memory cells 400 to 402. And proceeds to step S53.

  Next, if it is determined in step S53 that the first to third memory cells 400 to 402 are “1”, the process proceeds to step S37 in FIG. 4A, while the first to third memory cells 400 to 402 are “1”. If it is not, the process proceeds to step S43 in FIG. 4A.

  On the other hand, if it is determined in step S51 that the fourth to sixth memory cells 403 to 405 are not “0”, the process proceeds to step S54, where “1” is written to the first to third memory cells 400 to 402, and step S55. Proceed to

  Next, if it is determined in step S55 that the first to third memory cells 400 to 402 are “1”, the process proceeds to step S43 in FIG. 4A, while the first to third memory cells 400 to 402 are “1”. If it is determined that it is not "," this processing is terminated because the writing has failed.

  Thus, in the case of data “0”, “000” is stored in the first to third memory cells 400 to 402 and “111” is stored in the fourth to sixth memory cells 403 to 405. In the case of data “1”, “111” is stored in the first to third memory cells 400 to 402 and “000” is stored in the fourth to sixth memory cells 403 to 405.

  If the first to third memory cells 400 to 402 or the fourth to sixth memory cells 403 to 405 are defective and a desired state cannot be stored, the first to sixth memory cells 400 to 400 are used. All of 405 are set to “0” or “1” to distinguish from the above-described data “0” and data “1” states.

  Then, desired data is written into the next memory cell group. Here, the memory cell failure is defined as “write failure” in which “1” cannot be written and “0” is fixed, and “erase failure” in which “1” is fixed without being erased to “0”.

Assuming that the erase failure rate of individual memory cells (including the probability of not being in the erased state at first) is e and the write failure rate is p, the complete failure rate ε4 (FIG. 4A, FIG. The probability of 4B “write failure”) is
ε4 = 1−γ1, γ2-γ1, γ3-γ2, γ4
It is represented by Further, the defect rate ε5 (probability of passing through “j = j + 1” in step S43 in FIG. 4A and becoming a defective memory cell group) in which the memory cell group can be redundantly replaced is:
ε5 = γ1 ・ γ3 + γ2 ・ γ4
It is.

において、ｄ＝３としたものを用いる。さらに、ｎビットの記憶に対して、ｍ組(ｍ＞ｎ)のメモリセル群を持っている場合の冗長置換後のｍ組全体の不良率ε６は、個々のメモリセル群の不良率をε７としたとき、

で表される。 Where

In this case, d = 3 is used. Further, when there are m sets (m> n) of memory cell groups for n-bit storage, the failure rate ε6 of the entire m sets after redundant replacement is expressed as ε7. When

It is represented by

Here, if e = p = 1%,
Complete defect rate ε4 ≒ 0.2035%
Defect rate ε5 ≒ 5.6485%
It becomes. Since ε0 << ε1, the above equation can be set to ε7≈ε5. For example, when the number of bits to be stored is 8 bits (n = 8), if three memory cell groups are provided and m = 11 The overall defect rate ε6≈0.2435%, which can be suppressed to a very low defect rate.

  If m = 8 without redundant replacement, the overall failure rate is 37.20%, so the failure rate can be reduced to about 1/150. Alternatively, if four sets of memory cell groups are provided and m = 12, the overall defect rate ε6≈0.0325% can be suppressed to a lower defect rate, which is approximately 1140 compared with the case where no redundant replacement is performed. The defect rate can be reduced by a factor.

  According to the semiconductor memory device having the above configuration, since it is possible to tolerate a failure of (mn) memory cell groups among the m sets of memory cell groups 301 to 30m, even if the failure rate of individual memory cells is high. In addition, even if the characteristics of individual memory cells fluctuate after product shipment, the failure rate of the entire memory cell group can be kept low, and the yield at shipment can be improved. The information in the memory cell can be read out. Further, since it is not necessary to store the address of the defective memory cell group in the replacement address memory cell as in the prior art, the defective rate of the replacement address memory cell itself does not affect the defective rate of the product.

  Further, the three first to third memory cells 400 to 402 or the fourth to sixth memory cells 403 to 405 necessary for suppressing defects after shipment by a majority circuit or the like are set to the same “000” or “111”. Since it is used for storing "", reliability can be improved by increasing redundancy.

  Further, as a state of data “0”, “0” is stored in all of the first to third memory cells 400 to 402 and “1” is stored in all of the fourth to sixth memory cells 403 to 405. As a state of data “1”, “1” is stored in all of the first to third memory cells 400 to 402 and “0” is stored in all of the fourth to sixth memory cells 403 to 405. In addition, as a state for indicating the replacement memory cell group, “0” or “1” is stored in all of the first to sixth memory cells 400 to 405, so that the memory cell is defective. Even if there are both “erase failure” and “write failure”, it is possible to suppress the failure rate to a very low level.

  Further, in the second embodiment, the same “0” or “1” is stored in the first to third memory cells 400 to 402 or the fourth to sixth memory cells 403 to 405, so that the product is Even if a data retention failure (retention failure) occurs after entering the market, if there is only one failure among the three memory cells, correct information can be read from the memory cell with a majority circuit such as that shown in FIG. .

である。ここで、ｅ＝ｐ＝ｒ＝ｓ＝１％とすると、リテンション不良率ε８≒０.０５５％となる。 As shown in FIG. 5, the outputs of the first to third memory cells 400 to 402 are connected to a first majority circuit 410, and the outputs of the fourth to sixth memory cells 403 to 405 are connected to a second majority. The circuit 420 is connected. In the semiconductor memory device using the first and second majority circuits 410 and 420, the retention failure rate of the erase memory cell (the probability of “1” change of “0”) is r, and the retention failure rate of the write memory cell ( Assuming that s is the probability of “1” being “0”, the defect rate ε8 after passing through the majority circuit is approximately expressed by the following equation.
ε8 ≒ (1-ep) ⁶ (1-δ1 ・ δ2)
+ 3p (1-ep) ⁵ (1-δ1 · δ3)
+ 3e (1-ep) ⁵ (1-δ2 · δ4)
However,

It is. Here, if e = p = r = s = 1%, the retention defect rate ε8≈0.055%.

  By connecting the outputs of the first to third memory cells 400 to 402 to the first majority circuit 410 and connecting the outputs of the fourth to sixth memory cells 403 to 405 to the second majority circuit 420. In addition to improving reliability and using a majority circuit, the minimum three memory cells necessary to suppress defects after shipment are used for storing the same “000” or “111”, so the circuit scale can be reduced. can do.

  In the second embodiment, the number of memory cells in the memory cell group is six. However, as shown in FIG. 6, the number of memory cells may be generally arbitrary k. When writing "0 ... 0" or "1 ... 1" to half of the memory cells (k / 2) and writing "0 ... 0" or "1 ... 1" to the other half (k / 2) If d = k / 2 is input to the expressions γ1 to γ4, the expressions ε4 to ε6 hold as they are. Of course, the number k of memory cells may be an odd number, or the number of “0... 0” or “1.

(Third embodiment)
7 and 8 are block diagrams showing a liquid crystal panel as an example of an electronic apparatus according to the third embodiment of the present invention. This liquid crystal panel includes any one of the semiconductor memory devices of the first and second embodiments as a nonvolatile memory, and stores digital data for adjusting the common potential Vcom in the nonvolatile memory.

  As shown in FIG. 7, the liquid crystal panel includes a liquid crystal pixel 700, a TFT (Thin Film Transistor) 701, and an additional capacitor 702 arranged in an array, a gate driver 703 that drives the gate of the TFT 701, and a TFT 701. The source driver 704 is connected to the source.

  The TFT 701 selected by the gate driver 703 is turned on, and data is temporarily stored in the additional capacitor 702 from the source driver 704 via the TFT 701. In order to prevent deterioration of the pixel 700 of the liquid crystal panel, high voltage VH data is given in the first half (positive field) in one frame, and low voltage VL data is given in the second half (negative field) in one frame. A voltage of (VH + VL) / 2 is applied as the reference voltage to the common potential Vcom as a reference voltage in order to prevent screen flickering. However, since there is a manufacturing variation in the parasitic capacitance between the gate and the source of the TFT, it is necessary to set the common potential Vcom for each liquid crystal panel.

  Therefore, as shown in FIG. 8, the Vcom voltage generator stores the adjustment value in the memory unit 800 and outputs it as a common potential Vcom via a D / A converter (digital / analog converter) 801 and a Vcom driver 802. Just do it. Since the memory unit 800 needs to store the Vcom adjustment value for a long period of time, a high degree of reliability is required.

  Here, the non-volatile memory of the third embodiment is composed of a plurality of memory cells even if the defect rate of each memory cell is high or the characteristics of each memory cell fluctuate after product shipment. A method of storing 1-bit data in a memory cell group and replacing it with a spare memory cell group when there is a defect is used. As a result, the defect rate of the memory portion can be kept low, the yield at the time of shipment can be increased, and the information of the memory cells can be read accurately for a long time after the product is shipped.

  Therefore, an electronic device including the semiconductor memory device of the present invention can achieve high reliability. Note that the electronic device is not limited to a liquid crystal panel, and can be used in any electronic device such as a digital camera, a mobile phone, a digital audio recorder, and a music recording / playback device.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the first to third embodiments, and various modifications can be made within the scope of the present invention.

FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. FIG. 2A is a flowchart for explaining the operation of the semiconductor memory device. FIG. 2B is a flowchart following FIG. 2A. FIG. 3 shows a semiconductor memory device according to the second embodiment of the present invention. FIG. 4A is a flowchart for explaining the operation of the semiconductor memory device. FIG. 4B is a flowchart following FIG. 4A. FIG. 5 is a diagram showing an example of first and second majority circuits used in the semiconductor memory device. FIG. 6 is a diagram showing a semiconductor memory device according to another embodiment of the present invention. FIG. 7 is a block diagram showing a liquid crystal panel as an example of an electronic apparatus according to the third embodiment of the present invention. FIG. 8 is a block diagram of a Vcom voltage generator used in a liquid crystal panel as the electronic apparatus.

Explanation of symbols

101 to 10 m, 301 to 30 m, 501 to 50 m ... memory cell group 200, 201, 400 to 405, 601 to 60 k ... memory cell 410 ... first majority circuit 420 ... second majority circuit 700 ... liquid crystal pixel 701 ... TFT
702 ... Additional capacity 703 ... Gate driver 704 ... Source driver 800 ... Memory unit 801 ... D / A converter 802 ... Vcom driver

Claims (8)

In order to store n bits, the memory cell group includes m sets (m> n) of k memory cells (n, k, m are natural numbers),
Any one of at least three states is stored in each of the memory cell groups. The semiconductor memory device according to claim 1,
The memory cell group stores data “0”, data “1”, and any one of three states indicating a replacement memory cell group. . The semiconductor memory device according to claim 2,
Each of the memory cell groups is composed of two memory cells. The semiconductor memory device according to claim 3.
The memory cell group is
A first memory cell and a second memory cell;
As a state of the data “0”, “0” is stored in the first memory cell and “1” is stored in the second memory cell,
As the state of the data “1”, “1” is stored in the first memory cell and “0” is stored in the second memory cell.
A semiconductor memory device, wherein “0” or “1” is stored in both the first memory cell and the second memory cell as a state indicating the replacement memory cell group. The semiconductor memory device according to claim 2,
Each of the memory cell groups is composed of six memory cells. The semiconductor memory device according to claim 5.
The memory cell group is
It is composed of first to sixth memory cells,
As the state of the data “0”, “0” is stored in all of the first to third memory cells and “1” is stored in all of the fourth to sixth memory cells,
As the state of the data “1”, “1” is stored in all of the first to third memory cells and “0” is stored in all of the fourth to sixth memory cells,
A semiconductor memory device, wherein “0” or “1” is stored in all of the first to sixth memory cells as a state indicating the replacement memory cell group. The semiconductor memory device according to claim 6.
A first majority circuit to which outputs of the first to third memory cells are connected;
A semiconductor memory device comprising: a second majority circuit to which outputs of the fourth to sixth memory cells are connected.   An electronic apparatus comprising the semiconductor memory device according to claim 1.

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