JPS636648A - Bipolar storage circuit with error detecting function - Google Patents

Abstract

PURPOSE:To detect the inversion of a memory cell done by an alpha line, etc., by using a gate circuit for control of word address decoder which contains a pair of memory cells and can read and write the same contents at a time. CONSTITUTION:When a writing action is carried out with a high potential applied to a control terminal T, two of word selection lines WT1, WT2... set in pairs have high potentials by the combinations of high and low levels of the signals applied to terminals A1-Ai excluding a terminal A0. Thus the writing actions are possible simultaneously to two memory cells M1 and M2 connected to said two word selection lines. In a read mode of contents a read signal is outputted to an output terminal S as long as a high potential is applied to the terminal T. If the coincidence is secured between the states of both cells M1 and M2 which are read out then, the error signal output E keeps a high potential to show the absence of errors. While the potential of a terminal E is lowered to show a soft error of the alpha line, etc.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention can be used as a normal memory circuit, and if necessary, the memory cell can be inverted due to α rays or the like in its memory contents. This invention relates to a bipolar memory circuit with an error detection function that can also be used as a memory circuit with a function of detecting errors.

(Prior art) In recent years, bipolar memory circuits consisting of one cell of one flip-flop circuit have been becoming more highly integrated and faster. A soft error may occur in which the memory cell is inverted due to the influence of the temperature. Conventionally, detection of this soft error is not included in the memory circuit itself, but is performed by an external logic circuit.

(Problems to be Solved by the Invention) The above-mentioned conventional bipolar memory circuit requires a large number of logic circuits because other logic circuits are configured separately to detect inversion of memory cells due to soft errors. However, there are problems in that error detection is slow, and the reliability is low because it is difficult to determine whether the detection result is due to a soft error or an error in another logic circuit itself.

An object of the present invention is to solve all of these problems and to provide a bipolar memory circuit with an error detection function that can detect soft errors in the memory circuit itself, if necessary. .

(Means for Solving the Problems) In order to achieve the above object, the bipolar memory circuit with an error detection function of the present invention has a plurality of memory cells (Ml, M2
~Mn) and means (1a Ilb IQWI) for convolving the contents to be stored in the storage cells (Ml1M2~Mn)
, 9w2) and reading means (2, QRl, QR
2, Ql-G4) and word address decoders (A O to A 6 , Gwt, GW2~Gwn)
In a bipolar memory circuit having a plurality of memory cells (Ml, M2 to Mn), each two memory cells are set as one set, and the same content is simultaneously written to the two memory cells forming the set, or the set is A word address decoder (Ao to A
i.

Gwl, GW2 to Gwn) output control gate circuit (G
l, G2, Gs), and an error detection circuit (Q
5 to Qa) are added.

(Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment according to the present invention.

First, the configuration and operation of the storage section, writing, and reading sections of this embodiment will be explained.

As shown in FIG. 1, the memory cell Ml has resistances Rct and RC2.
and a cross-coupled double emitter transistor QCI
It is composed of IQC2 and forms the entire flip-flop circuit. Similarly, the memory cell M2 has resistors RC3 and RC4, and a cross-coupled double emitter transistor QC3@
Storage cells M3 to M (not shown) configured by QC4
Each of n is also composed of two resistors and two double emitter transistors. One ends of resistors RC1 and RC2 are connected to word selection line WTI, and transistor Q
The emitters e12 and e22 of CLIQC2 are constant 1 to maintain the bistable state of the flip-flop circuit! It is connected to the flow supply line WB1.

Also, the other emitter elL of the transistor QCI eQ"
Ie21 is the respective put selection fgDl.

Connected to D2. And bit selection lines D1, D2
is connected to a negative power supply -V via a current source to supply a read current ID.

The memory cells M2 to Mn also have the same configuration as the memory cell M1 and are connected in the same way.

Further, the bit selection line Dl is connected to a transistor Qwr whose pace is supplied with the output WC of the write signal generation circuit 1a.
The output R of the read signal generation circuit 2 is connected to the emitter of
The emitter of the transistor QRl to which the output signal C is applied is connected, and the emitter of the transistor QW2 to which the output WC of the write signal generation circuit 1b is applied to the pace, and the emitter of the transistor QRl to which the output WC of the write signal generation circuit 1b is applied to the pace, The emitter of a transistor Q2 to which the output RC of the signal generation circuit 2 is applied is connected. Collector loads R1 and R2 are connected to the collectors of the transistors Q p, > and Q R2, respectively, and are connected to the paces of the emitter follower transistors Q s and Q z, respectively. Signals SR and SR are outputted from the emitters of emitter-follower transistors Ql and Q2, respectively, and are connected to the base of transistor Q3IQ4 constituting a difference amplifier. The collector of the transistor Q3 is connected to the read signal output terminal S.

In the above circuit, memory cells Ml, Mz...
- When writing to Mn, write signal generation circuit 1a
The outputs WC and WC of and lb are respectively written in data, so that when the output WC is at a high potential, the output WC becomes a low/high potential, and when the output WC is a low potential, the output WC becomes a high potential.

When writing data at a certain time into a certain memory cell, only the word selection line to which the memory cell is connected is at a high potential, and all other word selection lines are at a low potential.

Indeed, when writing to memory cell M1, word selection line W
Only TI is at high potential, and the other word selection lines W are 2~W T
All n are at low potential. Therefore, if the output WC of the write signal generation circuit 1a is at a high potential and the output W of 1b is at a low potential, the transistor Qw1 is on and the bit selection line Dl is at a high potential, and the transistor QW2
is in the off state and the bit selection line D2 is at a low potential.

Therefore, from the high potential word selection line WT1 to the resistor Rcl
A current flows through the emitter e21 of the transistor QC2,
The transistor QC2 is turned on, but the emitter ell of the transistor QCI is connected to the high potential bit selection line Dl, so the transistor QCI is turned off. At this time, current also flows through the emitter e22 of the transistor QC2 which is in the on state, and the base current of the transistor QC1 which is in the off state is cut off. Therefore, even when the word selection line WTI changes from high potential to low potential and any of the other word selection lines becomes high potential, the base current of the °C transistor QC2 continues to flow through the emitter ezzk to the constant current/common supply line WBl, so the flip-flop The transistor QC2 constituting the programming circuit maintains and stores the on state and the off state of QCl.

Similarly, when writing to memory cell M2, word selection line W
If Tz becomes a high potential and the output WC of the containment signal generation circuit is a low potential and W is a high potential, the transistor QC3 is on and Qc4 is off, and in that state, the word selection line WT2 is at a low potential. It is retained and memorized even after eating. Note that during such a write operation, the output RO of the read signal generation circuit 2 is at a low potential and cuts off the base currents of the transistors QRI and QR2, and both QRI and QR2 are in the off state. It has nothing to do with achievements.

Next, when reading the contents (on and off states) stored in this circuit, write signal generation circuits 1a and lb
The outputs wC and we of are both set to a low potential, the output RC of the extraction signal generation circuit 2 is set to a medium potential between the high potential and the low potential, and the word connection line connected to the memory cell to be read is set to a high potential. do.

For example, when reading the memory contents from the memory cell M1, the word connection line WTI is at a high potential, but the transistors QC1, ! :The ON/OFF state of QC2 changes, so if QCl is in the OFF state, Q
If cz is in the on state, the negative power supply -■ is connected to the bit selection lines D1 and D2 via the constant current circuit ID, so the bit selection line Dlf is connected to the emitter ell of the transistor QC1 in the off state Current flows through the collector of the transistor QRt whose emitter is connected to
The emitter output SR becomes a low potential. On the other hand, the emitter of the transistor Q (connected to the emitter e21 of the on-state transistor Q2) is connected to the bit selection line D2 through which current flows from the emitter e21 to the negative power supply -■ through the constant current circuit ID. Since no current flows through the transistor QR2, and there is no voltage drop across the resistor R2, the base potential of the emitter follower transistor Q2 is high, and therefore the output SR of the transistor Q2 is also high potential.

The outputs SR and SR of the transistors Q1 and Q2 are the two inputs of a differential amplifier formed by the transistors Q3 and Q4 and the constant current circuit Is, so the read signal output connected to the collector of the transistor Q. A high potential voltage tlthl is applied to the terminal S. If the memory state of the memory cell is reversed, the transistor Q connected to the bit selection line Dl
If C1 is in the on state and the transistor QC2 connected to the bit selection line D2 is in the off state, the output of the successive signal output terminal S will be at a low potential.

Next, the configuration and operation of an error detection circuit for detecting soft errors, which is one feature of the present invention, will be explained.

The error detection circuit consists of a transistor Q as shown in Figure 1.
s, Qs, Q? , Q8. The emitters of transistors Q5 and Q6 are both connected to the collector of transistor Q7, and the emitters of transistors Q7 and QB are both connected to the negative power supply -VK through a constant current circuit via Ig. Transistors Qs and Q7
At the pace of, the output SR of the emitter-follower transistor Q1 and the transistor Q
;2 output SR, is given. transistor Q6
and QB's pace have different constant voltages VR1 and VB, respectively.
2 are given and the collectors are both grounded. The output is sent from the error signal output terminal E connected to the connection point between the collector of the transistor Q5 and the collector resistor R4.

With such a circuit configuration, when the potential of the output SR of the transistor Q2 is higher than the constant voltage VR2, the transistor Q7 is turned on and QB is turned off. If the potential of SR is lower than the constant voltage VR2, transistor Q7 is off and QB is on. Similarly, when the potential of the output SR of the transistor Ql is higher than the constant voltage VR1, the transistor Q5 is turned on and the transistor Q6 is turned off. If the potential of SR is lower than the constant voltage V1, transistor Q5 is turned off and transistor Q6 is turned on. Therefore, only when both transistors Q5 and Q7 are turned on, a t+ current flows through the resistor R4, and the output of the error signal output terminal E becomes a low potential.

Therefore, a low-potential error signal appears at the output terminal E because current simultaneously flows into each of the bit selection lines Dl and D2 from the transistors constituting the memory cell, and when both the transistors Qa and QR2 are off, the transistors Ql and This is only when the pace and emitter of Q2 become high potential at the same time.

Next, the output control gate circuit added to the word address decoder, which is another feature of the present invention, will be explained.

Conventionally, it is known that inversion of memory cells by the α gland does not occur for two bits at the same time.

Therefore, if a large number of memory cells are assigned to two memory cells at a time, and one bit is assigned to each pair of C2, and the memory contents are output separately and at the same time, the memory contents of the two memory cells forming the pair will be the same. It is possible to detect whether or not a mechanical error has occurred. In view of this, the output control gate circuit of this word address decoder controls the decoder output so as to simultaneously select two memory cells during writing and reading to obtain an error signal output.

FIG. 2 is a circuit diagram showing an example of a word address decoder used in the embodiment of FIG. 1, and is also used in conventional circuits.

The decoder in Figure 2 has address buffer gates 0 to 0.
Consists of GA3 and word line driver gates GW1 to Gwlo, and address buffers GA3 and word line driver gates GW1 to Gwlo.
If a pure binary code signal (high potential or low level signal) is input to each of the input terminals AO to A3 of the word line driver gates GWIA to A3, the outputs of the word line driver gates GWIA to GW10 will be
A high potential is output to one of A-WT LO.

Here, each of the address buffer gates GAO to Gλ3 has an output having the same potential as the input, and a negative output having the opposite level to the input, and each address buffer gate GAO to Gλ3 has an output having the same potential as the input, and a negative output having the opposite level to the input. is connected to the input of 几 to form a decoding circuit.

However, assuming that one of the address buffer gates, for example, the two output wirings GO1 and GO2 of GAO, can be fixed at a high voltage, the wiring shown by the dotted line in Fig. 2 is all at a high potential. and word line driver gate) Gwt to Gwto all connect high potential to logic “
Since it is an AND gate that takes the low potential as logic "0", its operation is based on the inputs rlJ, rO input through the wires shown in solid lines, regardless of the existence of the wires shown in dotted lines.
The output is determined by the combination of J. Moreover, the shape of the input wiring of each word line driver gate indicated by the solid line is G.
WI and GW2. GW3 and GW4. ...・@Contest G w s and G w s o are the same for the two gates from the top in the diagram. Therefore, if inputs of the combination of r IJ and roJ are given to the address buffer gates A1 to A3, a high' peak will be output to one of the two word line driver gate combinations as described above, and the other combination will be A low potential is output from all gates. Therefore, a decoder output control gate is inserted between one of the address back gates, for example, the output of GAO, and each word line driver gate, and the dotted lines GO1 and GOzi in FIG. When using address buffer gates A1 to ksf, the storage capacity is 1/2
However, a high potential is output from the two word line driver gates, all word selection lines are opened, and writing or reading can be performed in two memory cells at the same time.

For this purpose, the circuit shown in FIG. 3 connects the output of the address back gate GAO of the circuit shown in FIG.
G2. A control gate circuit composed of G3 is added.

In Fig. 3, when a high potential is applied to the control terminal TK, the output of the Nands gate G1 is at a low potential, and the Nands gate G s i
Since the force is applied to one of the nine inputs of the Nant gates G2 and G3, the Nant gate G2. C) 3, the output is at a high potential regardless of the level of the potential of other inputs input from the output of the address buffer gate GAO.

Incidentally, if it is desired to rotate the crops in the decoder circuit in the conventional manner, it is sufficient to apply a low potential to the control terminal T.

By doing this, Nante Gate G2. For both G3, one of the two inputs is at a high potential, so its output is determined by the level of the output of the address buffer gate 0 and 0, and the output of G2 is the same as the negative output of the address back gate GAo. The output of Nant gate G3 is the same as the time-dependent output of address buffer gate GAo.

The word address decoder circuit of the embodiment shown in FIG.
The circuit of Fig. 3 is converted into the address buffer gate GAo of Fig. 2.
It is the same as replacing O. However, in the circuit of FIG. 1, the number of inputs and outputs of the word address recorder is not limited to that shown in FIG. It is.

In FIG. 1, when writing is performed with a high potential applied to the control terminal T, the word selection line is connected to the word address terminal AO.
Word selection is performed by the combination of high and low levels of the word address signals given to the other A1 to No. 8 except for @WT 1 ,
The two lines in the set of WT2... become high potential, and the write signal is simultaneously transmitted to the two memory cells connected to this high potential word address selection line. Writing is performed depending on the level of the output WC9WC of the generation circuits 1a and lb. When reading out the contents stored in the memory cell as the on/off states of the two transistors by this write, is there any control? When a high potential is applied to the a terminal, any two word selection lines connected to one of the two memory cells forming the set become high potential, and the word selection at the high potential @ The on or off state of the two memory cells connected to the emitter-follower transistors Q1 and G2 outputs SR.

The level of the potential of SR is completely determined, and the read signal is output from the collector of the transistor Q4 of the differential amplifier to the read signal output terminal S.
is output to.

If the tt states of the two memory cells read at this time match, if one of the transistors QR11QR2 connected to the bit selection lines DI and D2 is on, the other is always off, and the emitter follower If one of the outputs 8J8R of the transistor Q1゜G2 is at a high potential, the other will always be at a low potential, so one of the transistors Q5 and G7 of the error detection circuit is in the off state, and the collector resistor 4 is Since no current flows and there is no voltage drop, the error signal output E remains at a high potential, indicating that there was no error.

If there is an inversion caused by an alpha ray or other power error in the two memory cells to be read, the on-state, wide transistors of the two memory cells that form the pair will always be connected to the bit selection lines Dl and Dl. Since one is connected to each bit selection line Dl and D
The emitter ufR is transmitted through two memory cells from word line selection to afl-1. Therefore, the transistor QFLI,
QFLZ is also in the off state, and the outputs 5JSR of the emitter follower transistors Q t and Q 2 are both at a high potential. Therefore, transistors Q5 and G of the error detection circuit
7 are both turned on, current flows through the collector resistor R4, and the resulting voltage drop causes the potential of the error signal output terminal E to be low, indicating that a soft error has occurred.

The above explanation is for the case where a high voltage is applied to the control terminal T, but if a low voltage is applied to the control terminal T, the circuit can be used in exactly the same way as a normal memory circuit.

(Effects of the Invention) As explained above, by providing a control gate circuit that controls the output of a word address decoder having a control terminal T, two words are always selected and two words on the same pit selection line are selected. It is now possible to write the same content into memory cells, and when reading out data, if there is a difference in the content read from two memory cells, by providing a circuit that detects this, alpha radiation, etc. This has the effect that it is possible to detect the reversal of the memory cell due to Therefore, there is no need to prepare a separate complicated logic circuit to detect errors as in the past, and the detection results are also easily distinguishable from errors in the logic circuit itself used to detect errors as in the past. It also has the advantage of being highly reliable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment according to the present invention. FIG. 2 is a circuit diagram showing an example of a word address decoder used in the embodiment of FIG. 1. FIG. 3 is a circuit diagram showing an example in which a decoder output control gate circuit is added to the address buffer gate. la, lb...Write signal generation circuit 2...Display signal generation circuit M1. M2...Storage cell Gl, G2, G3...Nant gate GλQ, GA
t, 0 people 2. GA3. OA number 1 address buffer gate Gw l, Gwz, Gw 3 ~ Gw lo ・-')
-)' line driver gates Ql, G2, Qa, G4, G5, Qa, Q
y, Qs...transistor Qc 1. QC2, QCs jQC4...Double emitter transistor Rt, Rz, Rx, R4, Rat, Rc2. Rc3゜R
C4...Resistors WT1, WT2, WT3 to WTIG...Word selection lines Wal, WBz...Constant current supply line 1)1. Dl... Bit selection line In, In, Is... Constant current circuit E... Error signal output terminal S... Read signal output terminal T... Control terminal

Claims (1)

[Claims] A plurality of memory cells, a write means for writing contents to be stored in the memory cells, a read means for reading contents stored in the memory cells, and a memory cell to be written when writing is performed. In a bipolar memory circuit having a word address decoder that outputs a signal for selecting a memory cell to be read out when reading is performed, one set includes two memory cells each of the plurality of memory cells; a gate circuit for controlling the output of the word address decoder so that the same content can be simultaneously written into two memory cells forming the group, or read simultaneously from the two memory cells forming the group; 1. A bipolar memory circuit with an error detection function, characterized in that an error detection circuit is added that simultaneously reads data from memory cells and detects it as an error if the two read contents are different.