JPS54162945A - Programable delay circuit - Google Patents

Programable delay circuit

Info

Publication number
JPS54162945A
JPS54162945A JP7253378A JP7253378A JPS54162945A JP S54162945 A JPS54162945 A JP S54162945A JP 7253378 A JP7253378 A JP 7253378A JP 7253378 A JP7253378 A JP 7253378A JP S54162945 A JPS54162945 A JP S54162945A
Authority
JP
Japan
Prior art keywords
delay time
output
line
tap
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7253378A
Other languages
Japanese (ja)
Inventor
Masahiko Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7253378A priority Critical patent/JPS54162945A/en
Publication of JPS54162945A publication Critical patent/JPS54162945A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks
    • H03H7/32—Time-delay networks with lumped inductance and capacitance
    • H03H7/325—Adjustable networks

Abstract

PURPOSE:To secure the accurate the linear characteristics for the relation between the delay time control signal and the delay time by providing the multiplication gate to select the delay time and the delay line with the tap containing several units of output taps. CONSTITUTION:The impedance matching is given to the terminal of delay line 12, and clock input 1 advances line 12 with no reflection to be supplied to multiplication gate 14 from each tap 16. Then the gate input selected by the output of register 10 is delivered in the form of delayed clock output 2. For example, if the output of register 10 is 000, the pulse of delay time 0 is selected from the extreme left tap of line 12. And in the case of register output of 111, the pulse of the maximum delay time is selected from the extreme right tap. When the delay time between taps of line 12 is made identical to each other, an optional integer-fold delay time can be selected freely by delay time control signal 11. Thus, the accurate linear characteristics can be obtained for the relation between signal 11 and the delay time.
JP7253378A 1978-06-14 1978-06-14 Programable delay circuit Pending JPS54162945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7253378A JPS54162945A (en) 1978-06-14 1978-06-14 Programable delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7253378A JPS54162945A (en) 1978-06-14 1978-06-14 Programable delay circuit

Publications (1)

Publication Number Publication Date
JPS54162945A true JPS54162945A (en) 1979-12-25

Family

ID=13492071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7253378A Pending JPS54162945A (en) 1978-06-14 1978-06-14 Programable delay circuit

Country Status (1)

Country Link
JP (1) JPS54162945A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168505U (en) * 1984-10-09 1986-05-10
US4675562A (en) * 1983-08-01 1987-06-23 Fairchild Semiconductor Corporation Method and apparatus for dynamically controlling the timing of signals in automatic test systems
JPS63211809A (en) * 1988-02-10 1988-09-02 Elmec Corp Electromagnetic variable delay line
JPS648833U (en) * 1987-02-20 1989-01-18
US4820944A (en) * 1983-08-01 1989-04-11 Schlumberger Systems & Services, Inc. Method and apparatus for dynamically controlling the timing of signals in automatic test systems
JPH01194602A (en) * 1988-01-29 1989-08-04 Yokogawa Medical Syst Ltd Variable delay line circuit
US5389843A (en) * 1992-08-28 1995-02-14 Tektronix, Inc. Simplified structure for programmable delays

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4675562A (en) * 1983-08-01 1987-06-23 Fairchild Semiconductor Corporation Method and apparatus for dynamically controlling the timing of signals in automatic test systems
US4820944A (en) * 1983-08-01 1989-04-11 Schlumberger Systems & Services, Inc. Method and apparatus for dynamically controlling the timing of signals in automatic test systems
JPS6168505U (en) * 1984-10-09 1986-05-10
JPS648833U (en) * 1987-02-20 1989-01-18
JPH01194602A (en) * 1988-01-29 1989-08-04 Yokogawa Medical Syst Ltd Variable delay line circuit
JPS63211809A (en) * 1988-02-10 1988-09-02 Elmec Corp Electromagnetic variable delay line
US5389843A (en) * 1992-08-28 1995-02-14 Tektronix, Inc. Simplified structure for programmable delays

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