JPH01194602A - Variable delay line circuit - Google Patents

Abstract

PURPOSE:To decrease waveform distortion caused by the fluctuation of the capacity of a variable capacity diode by connecting one half of plural variable capacity diodes in a complementary direction, and controlling them with voltages having the same absolute value and reverse polarities in a variable delay line circuit having a voltage control means. CONSTITUTION:Since the reverse voltage impressed at the cathode edge of a variable capacity diode 4a is positive, the voltage impressed between the both edges of the variable capacity diode 4a is reduced at a part where at input signal is at a high level, and a delay quantity is increased because of the increase of the capacity. However, in a second stage, since the reverse voltage impressed at the anode edge of a variable capacity diode 4b is negative, it is reverse to that in a first stage. Consequently, in a second stage, the waveform is distorted in the reverse direction to the first stage. For this, the distortion of the signal waveform generated by the variable capacity diode 4a in the first stage is offset by the variable capacity diode 4b in the second stage. Since this is successively repeated, the waveform distortion due to the fluctuation of the reverse voltage can be decreased from the final output signal waveform.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention comprises a plurality of inductances connected in series and a plurality of variable capacitance diodes to which a reverse voltage is applied, and the reverse voltage value is controlled. The present invention relates to a variable delay line circuit that provides a desired delay time to an input signal, and more particularly relates to a variable delay line circuit that reduces waveform distortion of an output signal waveform with respect to an input signal waveform.

(Prior Art) Conventionally, variable delay line circuits including a plurality of inductances and variable capacitance diodes have been used in various devices. FIG. 4 is a diagram showing a variable delay circuit section in a transmitting/receiving circuit in a conventional ultrasonic diagnostic apparatus. In FIG. 4, 1 is an input terminal into which a received signal obtained by converting a reflected ultrasound signal from a reflective substance in the living body into an electrical signal by a probe (not shown) is input, and 2 is a series connection of a plurality of inductances 3. and a plurality of variable capacitance diodes 4 whose anode ends are connected between inductances 3, 5 applies a predetermined positive voltage (reverse voltage) in parallel to each of the cathode ends of the variable capacitance diodes 4, A voltage control circuit that controls the capacitance of the variable capacitance diode 4 by changing this voltage value; 6 is a leakage current prevention capacitor having one end connected to the cathode side terminal of the variable capacitance diode 4 and the other end grounded; 7a; , 7b are respectively connected to the input and output sides of the delay line 2, and are matching resistors for matching the delay circuit section so that the input signal is not reflected. 8 is an output terminal of the delay circuit section. In the variable delay circuit section of the ultrasonic diagnostic apparatus configured in this way, the voltage control circuit 5 controls the reverse voltage applied to the variable capacitance diode 4 to create a desired time delay (delay amount) for the input signal. ), and performs phase control etc. when receiving ultrasonic waves.

(Problem to be Solved by the Invention) However, in the variable delay line circuit configured as described above, when the voltage level of the input signal is large, the reverse voltage applied to the variable capacitor varies depending on the input voltage, causing a delay. The amount fluctuates. FIG. 5 is a diagram illustrating such variations in the amount of delay. In Figure 5, E (
to) is the waveform of the input signal, E- (at to+) in the lower row
(solid line) is the waveform of the output signal. In FIG. 5, when the input signal E (to) is at a higher level (+) than OV, the reverse voltage applied across the variable capacitance diode 4 decreases relatively, and the capacitance of the variable capacitance diode 4 increases. As a result, the amount of delay increases.

Therefore, as shown in the figure, the output signal E'(to+
τ), the culm extension increases when the voltage level is high, and the waveform is distorted to the right (in the direction of delay) on the time axis from the input waveform E(to+τ) (dotted line). Similarly, when the signal is at a lower level (-) than OV, the reverse voltage applied across the variable capacitance diode increases relatively, and the capacitance of the variable capacitance diode 4 decreases, resulting in a small amount of delay. Become.

Therefore, as shown in the figure, the lower the voltage level of the output signal is, the lower the delay is, and the waveform is distorted to the left compared to the input waveform (dotted line). By sequentially repeating this waveform distortion, the final output signal waveform contains harmonics that do not actually exist. For this reason, especially in ultrasonic diagnostic equipment, this does not cause much of a problem in B-mode images that display the voltage level of the waveform, but in the Doppler mode that uses the frequency information of the waveform, it causes harmonic distortion, which has an adverse effect on the speed information obtained. effect.

Therefore, the present invention has been made to solve the above problems, and its purpose is to provide a variable delay that reduces waveform distortion caused by variations in the capacitance of the variable capacitance diode caused by the voltage of the input signal. The purpose is to provide line circuits.

(Means for Solving the Problem) A plurality of inductances are connected in series to a signal transmission path, a plurality of variable capacitance diodes are connected in parallel to this path, and a voltage is applied to the variable capacitance diode. In a variable delay line circuit comprising voltage control means for generating a control voltage, half of the plurality of variable capacitance diodes are connected in complementary directions and controlled by voltages having equal absolute values and opposite polarities. It is characterized by Furthermore,
The voltage control means is characterized by comprising means for outputting voltages of a desired magnitude in parallel, and voltage inverting means for inputting one of the outputs, changing the positive or negative polarity of the input voltage, and outputting it. do.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a variable delay line circuit according to an embodiment of the present invention. In FIG. 1, the same functions as those in FIG. 4 are denoted by the same symbols as in FIG. 4, so the explanation thereof will be omitted here. In FIG. 1, a variable capacitance diode 4a
The anode ends of each of them are alternately connected to the inductance 3, and a positive reverse voltage is applied in parallel to the cathode end from the voltage control circuit 5. The variable capacitance diodes 4b are provided in a complementary direction (opposite direction) to the variable capacitance diodes 4a, and each cathode end is connected to the inductance 3 alternately with the variable capacitance diode 4a, and the negative terminal from the inverter circuit 9 is connected to the anode end. Reverse voltages are applied in parallel.

The inverter circuit 9 inputs the output of the voltage control circuit 5 and outputs a reverse voltage having the same absolute value as the input voltage and opposite polarity. 5a and 5b are leakage current prevention capacitors connected in parallel to the anode and cathode sides of the variable capacitance diodes 4a and 4b, respectively, and whose other ends are grounded. In the above configuration, the operation of the variable delay line circuit of this embodiment will be explained using FIG. 1 and FIG. 2. Second
The figure is a diagram illustrating waveform changes caused by the variable delay line circuit of this embodiment. In Fig. 2, the upper waveform shows that the input signal is connected to the first stage inductance 3 and the variable diode 4a.
The delayed signal waveform E = (tl)
(solid line), and the lower waveform is a signal waveform E(t2) (solid line) that passes through the second stage inductance 3 and variable capacitance diode 4b and is further delayed. Since the reverse voltage applied to the cathode end of the variable capacitance diode 4a is positive, when the input signal is at a high level, the voltage applied between both ends of the variable capacitance diode 4a decreases.
The amount of delay increases as the capacity increases. As a result, as shown in FIG. 2, the output signal E-(tl) is the input waveform E(t
l) (The waveform is distorted to the right on the time axis from point I!>, and conversely, when the signal is at a low level, the waveform is distorted to the left. However, in the second stage, the anode of the variable capacitance diode 4b Since the reverse voltage applied to the terminal is negative, when the input signal is at a high level, the voltage applied across the variable capacitance diode 4b increases, and the amount of delay decreases due to the decrease in capacitance.As a result, As shown in Figure 2, the output signal E (t2) is distorted to the left of the input waveform, that is, the first stage output waveform E'' (t2) (dotted line), and conversely, when the signal is at a low level, it is distorted to the right. Therefore, in the second stage, the waveform is distorted in the opposite direction to that in the first stage, so the waveform distortion in the first stage is canceled out in the second stage, and by repeating this sequentially, the final output In the signal waveform, waveform distortion due to fluctuations in the reverse voltage is reduced, and harmonic distortion becomes slight.Here, the reason why the waveform distortion is not completely removed is due to the capacitance a of the variable capacitance diode.
This is because the change is not rectangular with respect to the reverse voltage.

In this way, according to the variable delay line circuit of this embodiment, the distortion of the signal waveform caused by the variable capacitance diode 4a in the first stage is suppressed by the distortion in the signal waveform caused by the variable capacitance diode 4a in the first stage. This is canceled out by the variable capacitance diode 4b, and by repeating this process sequentially, it is possible to reduce waveform distortion due to the fluctuation of the reverse voltage from the final output signal waveform. Further, since an inverter circuit is used as the means for generating voltages having the same positive and negative magnitudes, only one voltage generation source is required, so the structure can be constructed at low cost.

Note that the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.

FIG. 3 is a diagram showing a variable delay line circuit according to another embodiment of the present invention. In FIG. 3, the same symbols are used for parts having the same functions as in FIG. 1, so the explanation here will be omitted. Figure 3 shows the circuit configuration shown in Figure 1, with only the order of the variable capacitance diodes 4a and 4b being changed without changing the number. The waveform distortion caused by the controlled variable capacitance diode 4a is offset by the same number of variable diodes 4b for each floor, which are provided in a complementary direction and controlled by a negative reverse voltage, and the final output waveform is as described above. Similarly, waveform distortion is reduced. Therefore, the variable capacitance diodes 4a, 4b
Even if the order is arbitrarily changed, as long as the number of variable capacitance diodes with opposite directions is approximately the same, waveform distortion can be reduced from the final output waveform.

(Effects of the Invention) As explained above, according to the variable delay line circuit of the present invention,
The following effects can be obtained. That is, (1) a plurality of inductances connected in series to a signal propagation path, a plurality of variable inter-conductor diodes connected in parallel to this path, and a control voltage applied to the variable capacitance diode. In the variable delay line circuit equipped with a generating voltage control means, half of the plurality of variable capacitance diodes are connected in complementary directions and controlled with voltages having equal absolute values and opposite polarities. , due to the variation in the reverse voltage, the waveform distortion caused by the variable capacitance diodes controlled by the positive reverse voltage is canceled by the waveform distortion caused by the same number of variable capacitance diodes controlled by the negative reverse voltage, and the final output Harmonic distortion caused by the waveform distortion can be reduced from the signal waveform. Therefore, good signal delay can be obtained.

(2) The voltage control means consists of a means for outputting a desired positive voltage in parallel, and a voltage inverting means for inputting one of the outputs, changing the positive or negative polarity of the input voltage, and outputting it. Since there is no need to separately provide means for generating voltages having the same positive and negative magnitudes, only one voltage generation source is required, and the configuration can be made at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a variable delay line circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing waveform changes due to the variable delay line circuit of this embodiment, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a block diagram showing a conventional variable delay line circuit, and FIG. 5 is a diagram showing waveform changes caused by the conventional variable delay line circuit. 1...Input terminal, 2...Delay line, 3...
Inductance, 4.4a, 4b...variable capacitance diode, 5...
Voltage control circuit, 6.6a, 6b... Leakage current prevention capacitor, 7
a, 7b... matching resistor, 8... output terminal, 9...
inverter circuit,

Claims (2)

[Claims] (1) A plurality of inductances connected in series to a signal propagation path, a plurality of variable capacitance diodes connected in parallel to this path, and a voltage controller that generates a control voltage to be applied to the variable capacitance diodes. In the variable delay line circuit, half of the plurality of variable capacitance diodes are connected in complementary directions and have equal absolute values,
A variable delay line circuit characterized in that it is controlled by voltages with opposite polarities. (2) The voltage control means shall consist of means for outputting voltages of a desired magnitude in parallel, and voltage inverting means for inputting one of the outputs, changing the positive or negative polarity of the input voltage, and outputting the same. The variable delay line circuit according to claim 1, characterized in that: