JPH03196709A - Variable delay circuit and ultrasonic diagnostic device using the same - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the S/N and to obtain a variable delay circuit possible for circuit integration by connecting a delay circuit whose delay time is continuously variable and a capacitor memory circuit in cascade and to improve the picture quality of an ultrasonic picture by employing the said variable delay circuit. CONSTITUTION:A delay time of a variable delay circuit is varied with a change in a reverse voltage of a varactor diode of a variable delay line 6 comprising of an inductor and the varactor diode to vary the resistance of variable resistor circuits 7a, 7b with a change in the delay time of the delay line 6. Thus, the impedance of the circuit 7 and the delay line 6 of the delay circuit 1' are matched to prevent deterioration in the delay characteristic thereby making a clock signal of the capacitor memory circuit 2 to be a constant period. Moreover, the ultrasonic diagnostic device employs the circuit 1' as a delay circuit 18 in a phase matching circuit 20 thereby improving the picture quality of an ultrasonic picture.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a variable delay circuit that can be integrated into an integrated circuit and can prevent deterioration of the S/N ratio, and a variable delay circuit that can be used as a delay circuit in a phasing circuit. The present invention relates to an ultrasound diagnostic device that can be used as a circuit to improve the quality of ultrasound images.

[Conventional technology]

A conventional variable delay circuit is described in Japanese Unexamined Patent Publication No. 123819/1982 and as shown in FIG. It comprises a sample hold control means 3 and a capacitor memory control means 4 for controlling writing and reading of the capacitor memory circuit 2, and the sample hold means 1 and the capacitor memory circuit 2 are connected in a subordinate manner.

And the sampling frequency fs is assumed to be constant.

In capacitor memory circuit 2, the sampling period is 1/
A maximum delay of N/fs is performed every fs, and a short delay of less than the sampling period of 1/fs is executed by controlling the hold time of the sample hold means 1.

That is, in FIG. 6, a signal input from the input terminal IN is sampled and held by the sample and hold means 1, and then delayed by the capacitor memory circuit 2, and then a delayed signal is outputted to the output terminal OUT. Here, the sampling frequency fs is the signal maximum frequency f + m
It is necessary to have at least twice as much as ax, and the delayed output signal is obtained as a discrete signal value for each fs. In this case, in order to return the above-mentioned discrete signal to the original analog signal, the low-pass filter circuit 5
may be added. Further, the sample hold control means 3 controls the sampling clock CLX and the delay data DS.
By reading , the sample signal φS of the sample and hold means 1 is generated in order to execute an arbitrary delay. Further, the capacitor memory control means 4 reads the sampling clock CL and the delay data DL to generate a write signal φ9 and a read signal φg for the capacitor memory circuit 2 in order to execute an arbitrary delay.

A specific circuit configuration example of such a conventional variable delay circuit is shown in FIG.

The output of the sample and hold means 1 consisting of the following is written into the memory capacitors 01 to Cn by the write switches X0 to Xn, and is outputted with a delay by the read switches Y□ to Yn. In addition, in FIG.

Symbol X0 indicates a reset switch, symbol A2 indicates an operational amplifier, and symbols 5HR-V and 5HR-R indicate write switches X1 to Xn and read switches Y1 to Yn, respectively.
The shift register that controls the is shown.

FIG. 8 shows the sampling signal φS of the switch X of the sample and hold means l shown in FIG.
, 5HR-H is a timing diagram showing the timing of the write signal φ and the read signal φ9. Here, the phase difference τL between φ9 and φ is the sampling period T =
1/f s and delay data DL=i.

τL =: (i+ −)T where i=0, 1, 2
．． ...N-1...(1) is set by the capacitor memory control means 4. Further, the period of the write signal φY and the read signal φ6 is NXT, and the shift registers 5HR-W, 5HR-R(1) and the clock CL
Writing and reading are performed alternately to the capacitors Cm and Cmt+ which are shifted by period T from K2 and shifted by i. At this time, the hold time τ1 of the signal in each capacitor Cm and Cmu corresponds to the delay time. Therefore.

By capacitor memory circuit 2, buffer amplifier A8
It is output to the output terminal OUT as a sampling signal delayed by an amount corresponding to the output signal of .

Next, a short delay less than or equal to the sampling period T is.

As shown in FIG. 8, with respect to the write signal φ, the hold time of the sample and hold means 1 in the previous stage is τS (τs <
The sampling signal φS is set so that T ). The short delay τS mentioned above can be arbitrarily set by controlling the phase of the sampling clock CLK by the sample and hold control means 3. Therefore, the delay time τ of the conventional variable delay circuit as a whole is τ = τS + τ.
...(2), and an arbitrary delay was realized while the sampling period remained constant.

[Problem to be solved by the invention]

However, in such a conventional variable delay circuit, the summing signal φS of the switch X of the sample and hold means 1 has a hold time of τ
S, and this τS can be arbitrarily set by controlling the phase of the sampling clock CLK, so the timing of the sampling signal φS does not match the phase of the sampling clock CLK, The signal from the sampling clock CL may enter the capacitor memory circuit 2 as noise. Therefore, the S/N ratio of the variable delay circuit deteriorates. In addition, when such a variable delay circuit is applied to the delay circuit in the phasing circuit of an ultrasound diagnostic device,
The quality of the obtained ultrasound images deteriorated.

Therefore, the present invention solves these problems and improves the S/N
To provide a variable delay circuit which can prevent ratio deterioration and which can be integrated into an integrated circuit, and an ultrasound diagnostic device which can improve the quality of ultrasound images by using this variable delay circuit as a delay circuit in a phasing circuit. The purpose is to

[Means to solve the problem]

In order to achieve the above object, the variable delay circuit according to the present invention uses an inductor and a variable capacitance diode whose capacitance changes depending on the magnitude of the reverse voltage, and the delay time changes depending on the change in the reverse voltage of the variable capacitance diode. A variable resistance circuit is used as the signal source resistance and terminating resistance of this variable delay line to provide feedback with a constant resistance to an amplifier whose gain can be controlled by an electrical signal, thereby making the resistance value of the circuit variable. a delay circuit consisting of a delay circuit, a capacitor memory circuit sub-connected to the delay circuit, a control unit that sends a control voltage to the delay circuit and controls its delay time, and controls writing and reading of the capacitor memory circuit. This includes a write/read control circuit.

Further, as a related invention, an ultrasound diagnostic apparatus includes a probe in which a plurality of transducer elements are arranged and transmits and receives ultrasonic waves, and a predetermined delay in the received signal from each transducer element of the probe. A phasing circuit that has a delay circuit that gives time and adds and outputs received signals whose phases are aligned by these delay circuits, and an output obtained by processing the signal that has been phased by this phasing circuit. In an ultrasonic diagnostic apparatus comprising a display device that displays signals as images, graphs, etc., the variable delay circuit described above is used as a delay circuit in the phasing circuit.

[For production]

The variable delay circuit configured as described above changes the delay time by changing the reverse voltage of the variable capacitance diode of the variable delay line composed of an inductor and a variable capacitance diode, and is provided at both ends of the variable delay line. By changing the resistance value of the variable resistance circuit as a matching resistor according to the change in the delay time of the variable delay line, impedance matching between the variable delay line of the delay circuit and the variable resistance circuit is achieved, and the delay time changes. In addition, the clock signal of the capacitor memory circuit connected in cascade to the delay circuit is made to have a constant period to prevent noise from being mixed in.

In addition, the ultrasonic diagnostic device configured as described above always matches the impedance of the variable delay line and variable resistance circuit as a delay circuit in its phasing circuit, so that the delay characteristics do not deteriorate due to changes in delay time. In addition, by using a variable delay circuit that can prevent noise from being mixed in by making the clock signal of the capacitor memory circuit have a constant period.

This improves the quality of ultrasound images.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a variable delay circuit according to the present invention. This variable delay circuit has a delay time that changes continuously depending on the electrical signal applied to the control terminal, and can prevent deterioration of the S/N ratio, as shown in the figure.
A delay circuit 1', a capacitor memory circuit 2 connected in series to the delay circuit 1', and a control section 3' that sends a control voltage to the delay circuit 1' and controls its delay time.

The write/read control circuit 4 controls writing and reading of the capacitor memory circuit 2.

Assuming that the sampling frequency fs is constant, the capacitor memory circuit 2 has a sampling period of 1/f s
A delay of up to N/fs is performed for each sampling period, and a short delay of less than the sampling period 1/fs is executed by controlling the delay time of the delay circuit 1'.

That is, a signal input from the input terminal IN passes through a delay circuit 1' whose delay time is controlled by a control section 3' that generates a control voltage based on delay data DS, and is delayed by a capacitor memory circuit 2. A delayed signal is output to the output terminal OUT. Here, the sampling frequency f
A low-pass filter circuit 5 may be added in order to return the delayed output signal obtained as a discrete signal value every s to the original analog signal.

During its control, the delay time τS of the delay circuit 1' is between the sampling period T and zero of the delay circuit consisting of the capacitor memory circuit 2 and the write/read control circuit 4.
That is, it can be changed continuously within the range O≦τS≦T. Here, as explained with reference to FIG. 8, the phase difference between the write signal φ and the read signal φ of the capacitor memory circuit 2, that is, the delay time τL, is expressed by the above equation (1). Therefore, the delay time τ of the variable delay circuit as a whole having the configuration shown in FIG.

When τ=τS+, L=τg + (i+−)T. Therefore, τ can take continuous values greater than 1/2T, and a variable delay circuit in which the delay time changes continuously is constructed.

A specific circuit example of the variable delay circuit of the present invention configured in this way is shown in FIG. 2. In FIG. A delay line 6 is used, and the capacitor memory circuit 2 is constructed with a buffer amplifier A1 provided at its input section, and the other features are the same as in FIG.

The delay circuit 1' differs from conventional delay lines in that its delay time changes continuously depending on the electrical signal applied to its control terminal. This will be explained with reference to FIGS. 3(a) and 3(b).

First, FIG. 3 shows the circuit configuration of a unit part of a lumped constant delay line used in a conventional phasing circuit.

This unit part is a T-shaped symmetrical circuit as shown in the figure (a) or (b), and the circuit in the figure (a) has an inductor L/2. L/2 and a capacitor C,
It is commonly called a shaped low-pass filter, as shown in figure (b).
The circuit is an equivalent circuit obtained as a result of the two inductors L/2 shown in (a) being electromagnetically coupled, and is called an inductive m-type bandpass filter. A lumped constant delay line is constructed by cascading a large number of the above unit parts. By using a lumped constant delay line having such a configuration, the necessary delay time can be obtained with smaller signal attenuation than a distributed constant delay line, and in a smaller size.

Here, in the constant-shaped low-pass filter shown in FIG. 3(a),
It is assumed that both ends of the filter are terminated with characteristic impedance R0=2. Now, if we add an ideal step voltage as input.

The delay time ts and rise time t1 of the output voltage are t
s = 1.07 for you...(4)
t1= 1.13 sα...(
5). The overall delay time td and rise time tr when n unit parts are connected in series are td=n-ts-(
6) tr = t, -3(i
−(7). Therefore, when the above td and tr are given, the required number of sections n, inductor L, and capacitor C are given by the following equation.

1.07n d c=-□ 1.07nR.

...(10) Moreover, if the inductive m-type power-pass filter shown in FIG. 3(b) is used as the unit part, the delay time td and the rise time t
When the ratio with r is the same, the number of sections n to be cascaded can be reduced by about 6% compared to using the constant-shaped low-pass filter shown in (a) of the same figure. ), for example, if m = 1.27, the overshoot of the waveform of the transmitted signal and t, /ls are better than using the constant-shaped low-pass filter shown in FIG.

As described above, it can be seen that the delay time td of the lumped constant delay line composed of the inductor L and the capacitor C is given by equation (6). and.

Regardless of which type of filter shown in FIG. 3(a) or (b) is used, by changing the capacitance of the capacitor C,
The delay time of the lumped constant delay line can be made variable.

Therefore, in the present invention, FIG. 3(a) or (b)
By configuring the capacitor C in the lumped delay line, which is made up of a large number of unit parts connected in series as shown in FIG. 2, with a variable capacitance diode whose capacitance changes depending on the magnitude of the reverse voltage, the variable delay line shown in FIG. 6 is realized. A variable delay line similar to this variable delay 1lA6 was published in Japanese Patent Application Laid-Open No. 55-15
It is described in Japanese Patent No. 1280 and states that it is useful for ultrasonic diagnostic equipment. The delay circuit 1' according to the present invention, as shown in FIG.
A variable delay line 6 whose delay time changes according to changes in the reverse voltages of c and vc' is constructed, and a constant resistance is installed in an amplifier whose gain can be controlled by an electrical signal as a signal source resistance and a termination resistance of this variable delay line 6. It is constructed using variable resistance circuits 7a and 7b that provide feedback to vary the resistance value of the circuit.

The variable delay line 6 is made up of a large number of unit parts connected in a T-shaped symmetrical circuit, in which inductors L and L and sets of variable capacitance diodes vc and vc' are connected in series. It is configured. The cathode of one variable capacitance diode VC and the cathode of the other variable capacitance diode vC' are commonly connected, the anode of the one variable capacitance diode VC is grounded as it is, and the cathode of the other variable capacitance diode vC' The anode of is grounded via an inductor L and a resistor R. Therefore, the same DC potential is applied to each of the variable capacitance diodes VC and vC'. In addition, the above two variable capacitance diodes vc
, vc' are connected in common to each other.
A reverse voltage Ec is applied from each resistor r through a resistor r, and the delay time is controlled by changing the capacitance by this reverse voltage Ec. The above-mentioned resistor r is designed to prevent a signal from flowing through the control signal line 8 to each set of variable capacitance diodes vc, vc' and to prevent interference between the sets of variable capacitance diodes VC2vC'. It was established.

In FIG. 2, the symbol R indicates a resistor for grounding the input end a or the output end of the variable delay line 6, respectively, and is a part of the signal source resistance or termination resistance of the variable delay line 6. By grounding this resistor R, the DC potential of the anode of each set of variable capacitance diodes Vc, vc' is made the same as the ground level. Further, symbol C is a coupling capacitor for blocking direct current.

Here, when the capacitance of the variable delay line 6 is changed depending on the magnitude of the reverse voltage of each set of variable capacitance diodes vc and vc', the characteristic impedance also changes with the delay time. Therefore, in order to prevent deformation of the signal waveform or fluctuation of transmission efficiency due to impedance mismatch at the signal input/output terminals a and b, the signal source resistance and the termination resistance are always set in accordance with delay time control. It is necessary to change it to match the variable delay line 6 described above. Therefore, nine variable resistance circuits 7a and 7b whose resistance value changes depending on the electric signal are provided in the signal source resistance and termination resistance portions, respectively. As shown in FIG. 4, the variable resistance circuits 7a and 7b are capable of continuously changing the input resistance by changing the gain G of the variable gain amplifier 9 using its control voltage Ee.

The operation of variable resistance circuits 7a and 7b will be explained below with reference to FIG. The circuit of FIG. 4 consists of a variable gain amplifier 9 whose voltage gain G can be controlled by a control voltage Ec, and a constant resistor R.
Feedback is performed at f to make the resistance value of the circuit variable. The variable gain amplifier 9 described above can be realized by a commonly used Gilbird cell, etc., and the control voltage EC2 and voltage gain G of this circuit have a constant relationship, so that fluctuations in the gain G due to changes in ambient temperature are small. It's practical.

Here, the impedance seen from the input terminal 10 of the variable gain amplifier 9 is determined. At this time, the input impedance of the variable gain amplifier 9 is infinite, the output impedance is zero, and if the input voltage at the input terminal 10 is Ein, the current is i, and the output voltage at the output terminal 11 is E out, the following equation holds. .

Ein −Rf−i −Eout = O−(11)E
out = −G−Ein −(1
2) If Eout is eliminated from equations (11) and (12), Rf Ein = i - (13)
1+G, and when we partially differentiate this equation for input terminal Ein with respect to current i, the impedance Zin seen from input terminal 10 becomes
is as follows.

(1 line margin) ai 1+G If the gain G is changed in this equation (14), input terminal 1
The impedance Zin seen from 0 will change. That is, the resistance between the input terminal 10 of the circuit shown in FIG. It will change from Rf to 0.2Rf. As a result, the circuit shown in FIG. 4 becomes a variable resistance circuit. In the above description, the case of negative feedback has been described, but the variable resistance circuit also becomes a variable resistance circuit when positive feedback is applied. In this case, the gain G can be considered to take a negative value.

In FIG. 2, a voltage-current converter 12 is provided at the input terminal a of the variable delay line 6 of the delay circuit 1', and the input signal voltage is regulated via this voltage-current converter 12. The constant current signal is converted into a current signal, and the variable delay line 6 is driven by this constant current signal. Also, at the output end of the variable delay line 6.

A multiplier 13 is provided. This multiplier 13 is used to compensate for the fact that when the characteristic impedance R0 of the variable delay line 6 changes, the signal voltage appearing at the output end of the variable delay line 6 becomes iRo, which changes depending on the magnitude of Ro. It is. The magnification of this multiplier 13 is controlled by a control voltage Ec sent from the control section 3'.

The delay circuit 1' configured in this manner matches the impedance of the variable delay line 6 and the variable resistance circuits 7a and 7b to prevent deterioration of delay characteristics due to changes in delay time, and also prevents deterioration of delay characteristics due to changes in delay time. By making the clock signal of the capacitor memory circuit 2 cascade-connected to have a constant cycle, it is possible to prevent noise from entering.

FIG. 5 is a block diagram showing an embodiment of an ultrasonic diagnostic apparatus as a related invention to the variable delay circuit shown in FIGS. 1 and 2. FIG. This ultrasonic diagnostic apparatus uses ultrasonic waves to obtain a tomographic image of a diagnostic region of a subject, and is of an electronic linear scanning type.

For example, a plurality of transducer elements 14twi formed in a strip shape
ce... A probe 15 in which 14n are arranged in a line and transmits and receives ultrasonic waves, and each transducer element 14 of this probe 15.
and a switch group 16 that sequentially selects and switches only one group of transducer elements among the transducer elements 1 to 14n.

The received signals from one group of the transducer elements 141 to 14n of the probe 15 are inputted via the switch group 16, and the gain is increased over time to correct the signal strength according to the examination depth. It has amplifiers 17a to 17a and a plurality of delay circuits 18a to 18e that give predetermined delay times to the output signals from each of the amplifiers 1117a to 17e, and these delay circuits 18a to 18e output received signals whose phases are aligned. A phasing circuit 20 including an adder 19 for addition, and a detector 21 for detecting the signal phased by the phasing circuit 20.

It also includes a display device N22 that displays the output signal from the detector 21 as an image. In addition, in Fig. 5,
The switch group 16 is configured to sequentially select five vibrator element groups from one end and connect them to the next-stage amplifiers 17a to 17a, respectively.

The five transducer element groups mentioned above are sequentially switched and translated.Therefore, there are five amplifiers (178 to 17
e) Provided. In addition, the amplifiers 17a to 17e
The operation of is controlled by a control signal S□ from the control circuit 23.

Here, in the present invention, the delay circuits 11t18a to 18a in the phasing circuit 20 are shown in FIGS.
A variable delay circuit having the circuit configuration shown in the figure and whose delay time can be continuously changed by an electric signal input to its control terminal is used. The delay circuits 18a to 18e are connected to the fifth delay circuit 18a to 18e.
In the figure, the convergence point of the ultrasonic beam is set by 5, and the convergence point of the ultrasonic beam is determined over one hour by the control signal SX from the control circuit 23 (the control signal output from the control unit 3' and the write/read control circuit 4 in FIG. 2). Its convergence position is controlled so that it moves deep. Note that each of the delay circuits 18a to 18e described above may be constructed by cascading a plurality of stages as necessary.

With this configuration, in the electronic linear scanning ultrasonic diagnostic apparatus of this embodiment, each of the delay circuits 18a to 18e in the phasing circuit 20 can have a continuous delay time simply by inputting an electric signal to its control terminal. Therefore, dynamic focusing in which the convergence point of the ultrasonic beam is continuously moved can be realized with only one system of phasing circuit 20.

〔Effect of the invention〕

Since the variable delay circuit according to the present invention (see FIGS. 1 and 2) is configured as described above, the delay circuit 1' whose delay time can be continuously changed by an electric signal and the capacitor memory circuit 2 are connected in a subordinate manner. By doing so, it is possible to prevent the delay characteristics from deteriorating due to changes in delay time, and also to ensure that the clock signal of the capacitor memory circuit 2 has a constant period. Therefore, it is possible to prevent the clock signal from entering the capacitor memory circuit 2 as noise as in the conventional case, and to prevent deterioration of the S/N ratio of the variable delay circuit as a whole. Also.

The delay circuit section consisting of the capacitor memory circuit 2 and the write/read control circuit 4 can be formed into an integrated circuit. Therefore, even if the number of capacitors is increased to increase the delay time, a small and inexpensive delay circuit section can be realized. Furthermore, a variable capacitance diode vc shown in FIG.
Since the maximum delay time of the variable delay line 6 consisting of vc' may be smaller than the period of the clock signal of the capacitor memory circuit 2, the number of stages required may be small, and the required performance can be achieved at low cost.

Another ultrasonic beam according to the present invention! (See FIG. 5) is configured as described above, so by using the variable delay circuits having the circuit configurations shown in FIGS. 1 and 2 as the delay circuits 18a to 18e in the phasing circuit 20, noise can be reduced. It is possible to prevent contamination, improve the qS/N ratio, and improve the image quality of ultrasound images.Therefore, it becomes easier to see one image, making diagnosis easier.In addition, the delay circuit 18a Since the convergence point of the ultrasonic beam can be moved to a desired position by continuously changing the delay time simply by applying an electric signal to the control terminal of ~18e, dynamic focusing can be achieved with only one phasing circuit 20. This makes it possible to reduce the size of one circuit, making the device more compact and reducing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable delay circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific circuit configuration of this variable delay circuit, and FIGS. 3(a) and (b) are A circuit diagram to explain the thought process that led to the configuration of the variable delay circuit, Figure 4 is a circuit diagram showing the internal configuration of the variable resistance circuit, and Figure 5 is the variable delay circuit shown in Figures 1 and 2. FIG. 1 is a block diagram showing an embodiment of an ultrasonic diagnostic apparatus as a circuit-related invention. FIG. 6 is a block diagram showing a conventional variable delay circuit, and FIG. 7 is a circuit diagram showing a specific circuit configuration of the variable delay circuit.
FIG. 8 is a timing diagram for explaining the operation of a conventional variable delay circuit. 1'...Delay circuit, 2...Capacitor memory circuit. 3'...control unit, 4...write/read control circuit,
6... Variable delay line, 7a, 7b... Variable resistance circuit. 9... Variable gain amplifier, 141-14n... Transducer element, 15... Probe, 16... Switch group, 17a-17e... Amplifier, 18a-
18e...Delay circuit, 19 1...Detector, VO2...Adder, 20...Phasing circuit, 222...
Display device, L... implant vC'... variable capacitance diode.

Claims (2)

[Claims] (1) Using an inductor and a variable capacitance diode whose capacitance changes depending on the magnitude of the reverse voltage, a variable delay line whose delay time changes according to changes in the reverse voltage of the variable capacitance diode is constructed, and the delay time of this variable delay line is A delay circuit that uses a variable resistance circuit that changes the resistance value of the circuit by giving feedback with a constant resistance to an amplifier whose gain can be controlled by an electrical signal as a signal source resistance and a terminating resistance, and a variable resistance circuit that is connected in series to this delay circuit. It is characterized by comprising a capacitor memory circuit, a control section that sends a control voltage to the delay circuit and controls its delay time, and a write/read control circuit that controls writing and reading of the capacitor memory circuit. variable delay circuit. (2) A probe with a plurality of transducer elements arranged to transmit and receive ultrasonic waves, and a delay circuit that gives a predetermined delay time to the received signal from each transducer element of this probe. A phasing circuit that adds and outputs received signals whose phases have been aligned in a delay circuit, and a display that displays the output signal obtained by processing the signal phased by this phasing circuit in images, graphs, etc. 2. An ultrasonic diagnostic apparatus comprising: a variable delay circuit according to claim 1 as a delay circuit in said phasing circuit.