JPH04373212A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit with a small size, high efficiency at a low cost by providing a 1st delay means delaying the rise of a PWM signal and a 2nd delay means delaying the rise of an inverted PWM signal to the circuit. CONSTITUTION:A 1st delay circuit receiving a PWM signal and delaying the rise of the PWM signal for a prescribed time consists of buffers 3A, 6A, a resistor 4 and a capacitor 5, etc. A 2nd delay circuit receiving an inverted PWM signal and delaying the rise of the PWM signal for a prescribed time consists of buffers 3B, 6B, a resistor 9 and a capacitor 10, etc. Thus, the delay PWM signal by the 1st delay circuit is outputted therefrom and the inverted PWM signal with an inverted logic to the delayed PWM signal and having a pause period opposite to that of the PWM signal is outputted therefrom to attain the circuit with a small size and a high efficiency at the low cost.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to pulse modulation circuits, and more particularly to pulse width modulation circuits.

0002

[Prior Art] Conventional technologies for PWM modulation circuits include, for example, Kazuo Shimizu, published by Sogo Denshi Publishing Co., Ltd., "High-speed Switching Regulator", pages 72 to 79, or published by NEC Corporation, "Industrial Linear IC 1990”,
Some are described on pages 1008 to 1033.

FIG. 3 shows a PWM output signal C corresponding to an input signal A (see FIG. 4), and a signal (which has the opposite logic and whose rising and falling portions are removed for a necessary period of time).
A prior art pulse shaping circuit for obtaining an inverted PWM signal J (hereinafter referred to as an inverted PWM signal J) is shown. The conventional pulse shaping circuit includes comparators 21, 27, 29, an inverter 23, an operational amplifier 26, and an AND circuit 31. Comparator 21 is connected to triangular wave generator 22 and an input signal terminal, and comparators 27 and 29 are connected to reference power supplies 28 and 30. Further, in FIG. 4, signal waveforms of this prior art are indicated by corresponding symbols A to F. As shown in waveform C and waveform J in FIG. 4, the two output signals (PWM signal, inverted PWM signal) of the pulse shaping circuit that are output alternately after a certain pause period are as follows:
Each switch circuit uses this output signal as a drive signal (
(not shown) are used alternately to control the output to be controlled relative to a target value. In this case, the pause period between the two signals is set in consideration of the delay in switch operation time, etc., so that, for example, both switches do not become conductive at the same time.

[0004] The operation of this prior art will be explained as follows.
Since the input signal to be subjected to PWM modulation is applied to the positive input terminal of the comparator 21, and the triangular wave signal is applied to the negative input terminal, the PWM output signal C shown by waveform C is output. can get. The operational amplifier 26 is
This PWM output signal C is integrated to generate a triangular wave shown by waveform E. This triangular wave E and the voltages of the reference power supplies 28 and 30 are compared by two comparators 27 and 29, and the resulting outputs G and I are inputted together with the output D of the inverter 23 to an AND circuit 31 having three input terminals. As a result, an inverted PWM signal J shown in waveform J can be obtained. As shown in FIG. 4, waveforms C and J are signals having mutually opposite logic and having a predetermined pause period.

[0005]

[Problems to be Solved by the Invention] However, in such a conventional pulse shaping circuit, when the modulation frequency is set to about 1 MHz, for example, the operating cycle is 10
It becomes 00nsec. Therefore, unless high-speed comparators with a response time delay of at least about 50 nsec are used for the comparators 27 and 29, the delay of the waveforms G and I relative to the waveform E shown in FIG. 4 will be large. Also,
For the same reason, the operational amplifier 26 used as an integrating circuit also needs to be a product with a high slew rate and a high bandwidth. Therefore, in conventional pulse shaping circuits, by using high-speed comparators and operational amplifiers with high slew rates and high bandwidths, it is impossible to obtain an inverted PWM output, or only an output with an extremely small duty can be obtained. I was avoiding the problem. However, these high-speed comparators and high-slew-rate, high-bandwidth operational amplifiers all have large current consumption, which increases power loss in the entire circuit, makes it difficult to make them compact and highly efficient, and increases cost. .

The present invention eliminates these drawbacks of the prior art, and makes it possible to obtain an inverted PWM signal without requiring a high-speed comparator, high slew rate, or high-bandwidth operational amplifier even when the modulation frequency is increased. By doing so, the purpose is to simplify the circuit, reduce the number of elements, and provide a small, highly efficient, and low-cost pulse width modulation circuit.

[0007]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a PWM signal by inputting an input signal to the positive input terminal and a triangular wave to the negative input terminal, and comparing these signals. The pulse width modulation circuit has a comparison means for outputting a PWM signal and an inverted PWM signal obtained by inverting the PWM signal. , input the PWM signal, invert the PWM signal and convert it to the inverted PW
An inverter that outputs an M signal and an inverted P signal from the inverter.
A second delay means inputs the WM signal and delays the rise of the inverted PWM signal by a predetermined time, and the PWM signal delayed from the first delay means is mutually inputted with the delayed PWM signal by an inverse logic. The second delay means outputs an inverted PWM signal having a rest period.

[0008]

[Operation] According to the present invention, the PW output from the comparison means
The M signal is input to the first delay means, and its logic is inverted by the inverter and input to the second delay means. The first delay means and the second delay means each delay the rise of the input signal by a predetermined time and output the delayed signal. Therefore, the PW output from the comparing means
A PWM signal whose rise is delayed by a predetermined time from the M signal is outputted from the first delay means and the PWM signal outputted from the comparison means.
An inverted PWM signal whose rise is delayed by a predetermined time from the fall of the M signal is output from the second delay means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a pulse width modulation circuit according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a circuit diagram illustrating an embodiment of a pulse width modulation circuit according to the present invention is shown. The pulse width modulation circuit in this embodiment includes a comparator 1, an inverter 7, a first delay circuit, and a second delay circuit. A signal voltage is input to the positive input terminal of the comparator 1, and the triangular wave generator 2 is connected to the negative input terminal. The comparator 1 is a comparator that inputs a signal having a waveform A shown in FIG. 2 to a positive input terminal, inputs a triangular wave shown by a waveform B to a negative input terminal, and outputs a PWM signal shown by a waveform C. The output terminal of the comparator 1 is connected to the input terminal of the inverter 7 and the input side of the first delay circuit.

The first delay circuit is a circuit that delays the rise of the input PWM signal by a predetermined time, and is composed of an open collector type buffer 3A, a normal buffer 6A, a resistor 4, and a capacitor 5. The input terminal of open collector type buffer 3A is connected to the output terminal of comparator 1, and this output terminal is connected to buffer 6.
Connected to the input terminal of A. Further, the output terminal of the buffer 3A and the input terminal of the buffer 6A are connected to the power supply Vcc via a resistor 4 and to the ground via a capacitor 5. The first delay circuit outputs the PWM signal whose rise has been delayed from the buffer 6A.

The inverter 7 is a negative circuit that reverses the logic of the input PWM signal and outputs an inverted PWM signal, and its output terminal is connected to the second delay circuit. The second delay circuit is a circuit that delays the inverted PWM signal by a predetermined time, and includes an open collector type buffer 3B,
It is composed of a normal buffer 6B, a resistor 9 and a capacitor 10. That is, the second delay circuit has the same circuit configuration as the first delay circuit, but the values of the resistor and capacitor are determined so that a delay time different from that of the first delay circuit can be obtained. The second delay circuit is a delayed inversion PW
The M signal is output from the buffer 6B.

Next, the operation of this embodiment will be explained using FIGS. 1 and 2. In addition, waveforms A to H shown in FIG.
The waveforms appearing in each part A to H of FIG. 1 are shown respectively.

In the circuit shown in FIG. 1, when the power is first turned on, the output of the comparator 1 is a PWM signal that remains High during the period in which the signal voltage A exceeds the triangular wave voltage B. During the period when the PWM signal C is High, the capacitor 5 is charged by the power supply Vcc through the resistor 4, so that the terminal voltage gradually increases. Also, PWM output C is Low
At this point, the capacitor 5 becomes short-circuited, and its terminal voltage becomes almost zero. When the terminal voltage of the capacitor 5 exceeds the input threshold voltage of the buffer 6A as shown in waveform D, the output of the buffer 6A, that is, the output E of the first delay circuit, is delayed by T1 time from the PWM signal C as shown in FIG. stand up. The falling edge of waveform E is the same as that of the input signal. Similarly, the output H of the second delay circuit rises in waveform G with a delay of T2 time relative to the input signal F, as shown in FIG. 2, due to the time constant determined by the resistor 9 and capacitor 10.

Here, the output of comparator 1, PW
The rising edge of the M signal C is the same as the falling edge of the output H of the second delay circuit 2, and the falling edge of the PWM signal C is the same as the falling edge of the output H of the first delay circuit. In this way, the signals obtained from these delay circuits are signals of opposite logic having pause periods of T1 and T2. The signal E obtained from the first delay circuit has a duty shorter by T1 than the regular PWM signal C that is the output of the comparator 1, but
If T1 is selected to be 10% or less of the period T, there will be no practical problem. Therefore, if the output obtained from the first delay circuit is the PWM output E, then an inverted PWM signal H having a mutual pause period is obtained from the second delay circuit.

In this embodiment, the speed required for the buffer and inverter used in FIG. 1 is sufficient for practical use with a bipolar logic IC, such as the 74LS series, or a high-speed CMOS logic IC, the HC series. Therefore, compared to the conventional technology of a pulse width modulation circuit that uses a conventional high-speed comparator, high slew rate, and high band operational amplifier, this embodiment has a
The current consumption is 10 or less. Also, buffers 3A and 3B
, 6A, and 6B can all be of open collector type, and in this embodiment, these buffers can also be configured with one IC containing four circuits.

[0017]

[Effects of the Invention] As described above, according to the pulse width modulation circuit of the present invention, even when the modulation frequency is high and the operating cycle becomes fast, a high-speed comparator and a high-slew rate, high-bandwidth operational amplifier are not required. , it becomes possible to obtain a PWM signal and an inverted PWM signal that appear alternately with a predetermined pause period. Therefore, it is possible to provide a compact, highly efficient, and low-cost pulse width modulation circuit with little power loss.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a pulse width modulation circuit according to the present invention;

FIG. 2 is an operational waveform diagram for explaining the operation of the pulse width modulation circuit in this embodiment;

[Fig. 3] Pulse width modulation circuit in the prior art,

[Figure 4]
FIG. 2 is an operational waveform diagram of a pulse width modulation circuit in the prior art.

[Explanation of symbols]

1 Comparator 3A, 3B, 6A, 6B Buffer

Claims (2)

[Claims] 1. Comparing means for inputting an input signal to a positive input terminal and a triangular wave to a negative input terminal, and outputting a PWM signal by comparing these signals,
In a pulse width modulation circuit that outputs an M signal and an inverted PWM signal obtained by inverting the PWM signal, the circuit
a first delay means that receives a WM signal and delays the rise of the PWM signal by a predetermined time; an inverter that receives the PWM signal, inverts the PWM signal and outputs an inverted PWM signal; a second delay means that inputs an inverted PWM signal and delays the rise of the inverted PWM signal by a predetermined time; the PWM signal delayed from the first delay means is inversely A pulse width modulation circuit characterized in that a second delay means outputs an inverted PWM signal having a mutually paused period based on logic. 2. The pulse width modulation circuit according to claim 1, wherein the first delay means and the second delay means each include a first buffer for inputting a signal, a second buffer, a resistor, and a capacitor. , the resistor is connected between the power supply and these buffers, and the capacitor is connected between the ground and these buffers, and when a voltage higher than the threshold is input to the second buffer, the input signal is output by outputting a high level signal. A pulse width modulation circuit characterized by delaying the rise of the pulse width modulation circuit.