JPS6168505U - - Google Patents

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Publication number
JPS6168505U
JPS6168505U JP15351084U JP15351084U JPS6168505U JP S6168505 U JPS6168505 U JP S6168505U JP 15351084 U JP15351084 U JP 15351084U JP 15351084 U JP15351084 U JP 15351084U JP S6168505 U JPS6168505 U JP S6168505U
Authority
JP
Japan
Prior art keywords
delay line
output
electromagnetic delay
input
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15351084U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15351084U priority Critical patent/JPS6168505U/ja
Publication of JPS6168505U publication Critical patent/JPS6168505U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の電磁遅延線装置の一実施例を
示す回路図、第2図は第1図中の第1の電磁遅延
線の一例を示す要部斜視図、第3図は本考案の電
磁遅延線装置における第1の電磁遅延線の他の実
施例を示す要部正面図である。 1…導線路、3,3a…回路パターン、5…接
続片、7,7a…入力点、9,11…出力端、D
L1,DL1a…第1の電磁遅延線(マイクロス
トリツプライン)、DL2…第2の電磁遅延線、
Un…電磁遅延線装置。
Fig. 1 is a circuit diagram showing an embodiment of the electromagnetic delay line device of the present invention, Fig. 2 is a perspective view of essential parts showing an example of the first electromagnetic delay line in Fig. 1, and Fig. 3 is a circuit diagram showing an embodiment of the electromagnetic delay line device of the present invention. FIG. 3 is a front view of main parts showing another example of the first electromagnetic delay line in the electromagnetic delay line device of FIG. 1... Conductive line, 3, 3a... Circuit pattern, 5... Connection piece, 7, 7a... Input point, 9, 11... Output end, D
L1, DL1a...first electromagnetic delay line (microstrip line), DL2...second electromagnetic delay line,
Un...Electromagnetic delay line device.

Claims (1)

【実用新案登録請求の範囲】 (1) 両端を各々出力端として途中に信号の入力
される入力点を複数形成した第1の電磁遅延線と
、 この第1の電磁遅延線の前記入力点を選択して
信号を入力する入力点選択手段と、 前記第1の電磁遅延線の各出力点からの出力信
号のいずれかを切り換えて出力する信号切り換え
手段と、を具備し、 選択された前記入力点から入力した信号を前記
出力端から各々相互に異なる遅延時間を伴う信号
で出力するとともに、これら出力信号を切り換え
出力させてなることを特徴とする電磁遅延線装置
。 (2) 第1の電磁遅延線の少なくとも一方の出力
端と信号切り換え手段の間に第2の電磁遅延線を
接続してなる実用新案登録請求第1項記載の電磁
遅延線装置。
[Claims for Utility Model Registration] (1) A first electromagnetic delay line having output terminals at both ends and a plurality of input points along the way into which signals are input; and the input point of the first electromagnetic delay line. input point selection means for selectively inputting a signal; and signal switching means for switching and outputting one of the output signals from each output point of the first electromagnetic delay line, the input point being selected. 1. An electromagnetic delay line device characterized in that a signal input from a point is output from the output terminal as a signal with a mutually different delay time, and these output signals are switched and output. (2) The electromagnetic delay line device according to claim 1, wherein a second electromagnetic delay line is connected between at least one output end of the first electromagnetic delay line and the signal switching means.
JP15351084U 1984-10-09 1984-10-09 Pending JPS6168505U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15351084U JPS6168505U (en) 1984-10-09 1984-10-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15351084U JPS6168505U (en) 1984-10-09 1984-10-09

Publications (1)

Publication Number Publication Date
JPS6168505U true JPS6168505U (en) 1986-05-10

Family

ID=30711526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15351084U Pending JPS6168505U (en) 1984-10-09 1984-10-09

Country Status (1)

Country Link
JP (1) JPS6168505U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54162945A (en) * 1978-06-14 1979-12-25 Mitsubishi Electric Corp Programable delay circuit
JPS58145211A (en) * 1982-02-22 1983-08-30 Elmec Corp Variable delay line

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54162945A (en) * 1978-06-14 1979-12-25 Mitsubishi Electric Corp Programable delay circuit
JPS58145211A (en) * 1982-02-22 1983-08-30 Elmec Corp Variable delay line

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