WO1996029785A1

WO1996029785A1 - Variable loop gain frequency synthesizer

Info

Publication number: WO1996029785A1
Application number: PCT/JP1995/000477
Authority: WO
Inventors: Kazuyuki Hori; Masaru Kokubo
Original assignee: Hitachi, Ltd.
Priority date: 1995-03-17
Filing date: 1995-03-17
Publication date: 1996-09-26

Abstract

A frequency synthesizer comprising a phase frequency comparator (1), switching circuits (3n and 3p), constant-current sources (4n and 4p), a loop filter (5), a voltage-controlled oscillator (6), and a frequency divider (7) is provided with a first signal generator (8) which detects the absolute value of phase difference based on the output signal of the phase-frequency comparator (1), a second signal generator (9) which generates a pulse signal whose temporal ratio between the high and low levels is determined based on the output of the generator (8), switching circuits (11n and 11p) which are driven by the output signal of the generator (9), and constant-current sources (12n and 12p) connected to the circuits (11n and 11p). The temporal ratio between the high and low levels of the output of the generator (9) changes during the period when the circuits (3n and 3p) conduct. The electric current supply from the constant-current sources (12n and 12p) is effected or stopped based on the signal. Therefore, the loop gain is increased or decreased in accordance with the phase difference.

Description

Description Loop gain variable frequency synthesizer Technical field

The present invention relates to a frequency synthesizer that oscillates at a specified frequency, and more particularly to a frequency synthesizer suitable for performing high-speed frequency switching when a specified number is changed, and a wireless communication device using the same. Related background art

The mainstream type of the conventional PLL synthesizer is a type that uses a phase frequency »comparator (hereinafter abbreviated as PFC) and a charge pump. Fig. 13 shows the configuration diagram of a basic PLL synthesizer. 13 In Fig. 13, PFC 1 detects the phase difference between reference signal R and input signal V and outputs pulse signals UB and DB. The charge pump determines the inversion time (S2 and switch circuits 3 n and 3 p). It consists of power sources 4 n and 4 p, and controls the output current by opening switch circuits 3 n and 3 p according to the pulse signals UB and DB output from PFC 1. The loop filter 5 smoothes the output current from the charge pump, converts the smoothed current into a voltage, and assists VC06 with JB. VC06 is the JS wave number corresponding to the output voltage from the loop filter 5. And this is the output of the PLL synthesizer The output signal from VC 06 is frequency-divided by a frequency divider 7 externally specified by the frequency divider 7 and input to the PFC 1 as an input signal V. With the above configuration, the output of the PLL synthesizer is output. As a result, the oscillation wave number obtained by multiplying the frequency of the reference signal by the frequency division specified by the outer section is obtained. Therefore, by changing the specified frequency, the frequency can be switched. Be done.

FIG. 14 is a diagram showing a specific circuit configuration example of the PFC 1 used in the PLL synthesizer shown in FIG. PFC 1 in Fig. 13 has four resets: NAND 61a and 61b, NAND 62a and 62b, NAND 63a and 63b, NAND 64a and 64b. It consists of a type flip-flop (RS-FF) circuit and a NAND 65, and is connected so that the output of the ND 65 resets each RS-FF circuit. Fig. 14 shows an example of a PFC using an inverted logic edge (NAND) circuit, but other PFCs using an inverted OR (NOR) circuit are also known. Have been.

Fig. 15 (a) to (c) show timing diagrams showing the operation of the PFC 1 shown in Fig. 14. As shown in Fig. 15 (a), the reference signal R and the input signal When the phase difference of V is zero, the output signals UB and DB are both at a high level, so that the switch circuits 3 n and 3 p in FIG. 13 are both non-conductive. On the other hand, as shown in FIG. 15 (b), when the phase difference of the input signal V with respect to the reference signal R is positive (when the phase of the input signal V is advanced), the output signal DB becomes a pulse signal, The switch circuit 3n shown in Fig. 13 repeats conduction and non-conduction, and draws a current to the constant current source 4n during the period when the output signal DB is at a low level. As shown in the figure, when the phase difference of the input signal V with respect to the reference signal R is negative (when the phase of the input signal V is carried), the output signal UB becomes a pulse signal. The switch circuit 3 p repeats conduction and non-conduction, and the current flows from the constant current source 4 p during the period when the output signal UB is at the low level. Here, the time ratio at which the pulse signal DB or the pulse signal UB per unit time in FIG. 15 (b) or FIG. 15 (c) becomes low level is determined by the order of the reference signal R and the input signal V. Is proportional to the phase difference · The phase difference between input signal V and reference signal R is 2π At this time, the output signal DB is at the mouth level, and when the phase difference is 12π, the output signal UB is at the low level.

Now, the phase difference of the input signal V with respect to the reference signal R in a steady state of the PLL synthesizer (a state in which the oscillation frequency of the PLL synthesizer holds a constant value determined by an externally specified frequency division frequency and a reference signal frequency). (Hereinafter, this is referred to as the steady-state phase error.) Force Assume a positive constant value as shown in Fig. 15 (b). If this phase difference increases in the positive direction due to disturbance or the like, the time ratio at which the output signal DB of the PFC 1 becomes the a-level will increase. Therefore, the average S drawn by the charge pump 4 n will be increased. The flow increases. As a result, the position of the VCO 6 driving point decreases, so that when the VCO gain is positive, the frequency of the output signal from the VCO 6 decreases, and the phase difference decreases. In this way, control is performed so as to converge the phase difference to a constant, so that the frequency of the input signal V of the PFC 1 and the frequency of the reference signal R after convergence match. As a result, the frequency of the output signal from VC 06, that is, the oscillation frequency of the PLL synthesizer, becomes the frequency division number times the frequency of the reference signal R,

By the way, in the PLL synthesizer shown in FIG. 13, the constant current values (I 1 in FIG. 13) of the constant current sources 4 n and 4 p are constant values. Therefore, if the loop is widened by selecting I1 large and increasing the loop gain in order to shorten the frequency switching time, the phase noise component included in the reference signal R will depend on the frequency characteristics of the closed loop. It is output without being sufficiently removed. Conversely, if the loop is narrowed by selecting a small I 1 and reducing the loop gain in order to remove the phase noise component contained in the reference signal R, the frequency is switched. The contradictory problem of longer time arises. To solve this problem, the phase difference between the input signal V of the PFC 1 and the reference signal R is detected, and the output S from the charge pump is determined according to the magnitude of the phase difference. A method of making the flow value variable is known. As a conventional example of this technique, Japanese Patent Application No. 3-172024 discloses a loop gain variable type PLL synthesizer that changes the output current value based on the phase difference.

FIG. 16 shows the configuration of a loop gain variable PLL synthesizer using such a conventional technique. In this conventional example, the basic configuration of the PLL synthesizer shown in FIG. 13 is based on changing the gain of the loop consisting of the inverting circuit 52, the switch circuits 53n and 53p, and the constant current sources 54n and 54p. A second charge pump circuit is added. The function of generating the second charge pump control signals UFB and DFB is added to the PFC 51 of FIG.

Here, FIG. 17 shows a specific circuit configuration example of the PFC 51. FIG. 17 shows a configuration in which NANDs 71 a and 71 b and inverting circuits 72 a and 72 b are added to the PFC 1 of FIG.

FIGS. 18 (a) to 18 (d) are timing diagrams showing the operation of the PFC 51 shown in FIG.

FIG. 18 (a) corresponds to the case where the phase difference of the input signal V with respect to the reference signal R is between zero and π, and FIG. 18 (c) is the phase difference of the input signal V with respect to the reference signal R. Is equal to or more than 1π and equal to or less than zero. As shown in FIGS. 18 (a) and (c), when the absolute value of the phase difference is equal to or less than π, both of the second charge pump control signals UF Β and DF なる become high level. The switch circuits 53 η and 53 ρ in the figure are both non-conductive. In other words, the output compress value from the charge pump in this case is I 1.

Fig. 18 (b) corresponds to the case where the phase difference of the input signal V with respect to the reference signal R is between π and 2π, and Fig. 18 (d) is the phase difference of the input signal V with respect to the reference signal R. Is equal to or greater than 12π and equal to or less than 1π. As shown in Fig. 18 (b) and Fig. 18 (d), when the absolute value of the phase difference is π or more, Since one of the second charge pump control signals UFB and DFB is a pulse signal, one of the switch circuits 53 or 53p in FIG. 16 repeats conduction and non-conduction. Therefore, during the period when the second charge pump control signal UFB is at a low level, a positive current flows from the constant current source 4 p as well as the constant S current source 54 p, and the second charge pump control signal DFB During the period when is low, the S flow is drawn not only to the constant flow source 4 n but also to the constant S flow source 54 n. That is, in this case, the output current value from the charge pump becomes I 1 +12, and the operation of the second charge pump increases the output current value, thereby broadening the bandwidth of the PLL synthesizer.

In the conventional loop gain variable method described above, the second charge pump does not operate unless the absolute value of the phase difference reaches π or more due to the circuit configuration. Therefore, when the frequency switching width of the PLL synthesizer is small, the second charge pump does not operate at high speed, that is, the response time from the change of the designated frequency to the operation of the second charge pump. The problem is that it is long,

FIG. 19 (a) or (b) shows the case where the designated frequency of the frequency divider 7 is changed from 1 to 3Z4 or 7Z8 in the loop gain variable type PLL synthesizer shown in FIG. 51 is a diagram illustrating a phase difference when the frequency of the input signal V of (2) is switched between R at time t1. FIG. 19 (a) shows a case where the frequency of the input signal V is increased by about 33% from the frequency of the reference signal R (the period is reduced by 25%). It takes 1.5T for the phase difference to reach π. Fig. 19 (b) shows the case where the frequency of the input signal V is increased by about 14% from the frequency of the reference signal R (the period is reduced by 12.5%), and the phase difference reaches π. It takes 3.5Τ of the period. As shown in this example, as the frequency switching 钃 becomes smaller, the time until the phase difference reaches π, in other words, The delay time until the second charge pump starts operating will increase. This operation delay is a hindrance to speeding up the pull-in operation to the specified frequency after frequency switching.

In the variable loop gain method described above, when the range of the frequency division number specified from the outside and the oscillation collection frequency with respect to the input voltage of the VCO are designed so that the absolute value of the steady-state phase error is less than π, In the steady state, the band of the closed loop is a narrow band. For example, if the steady-state phase error is zero and a phase noise component of a magnitude less than π is added to the input signal V of the PFC 2 due to disturbance or the like, the conventional technology detects this noise and detects the charge pump output current Since it cannot be changed, it takes a long time to return to the steady state.

In order to solve these problems, it is effective to reduce the detectable phase difference and change the output S flow value from the charge pump even for a small phase difference. Disclosure of the invention

(1) In the present invention, a positive phase difference with respect to a reference signal used as input is detected, and a first pulse signal which determines a temporal ratio between a high level and a low level depending on this is output, and A PFC that detects a negative phase difference of the input signal with respect to the reference signal, and outputs a second pulse signal that determines a temporal ratio between a high level and an α-level depending on the negative phase difference; A first signal generator that outputs a pulse signal in which a time ratio between a high level and a low level is determined based on an absolute value of a phase difference between an input signal and a reference signal based on the pulse signal of A charge pump having a power source and a switch circuit, and supplying or shutting off a current based on the first and second output signals of the PFC to output an S current corresponding to a phase difference between the input signal and a reference signal. And The output of the charge pump is a loop filter that outputs a DC voltage by removing noise components superimposed on the flow and converting it to a low pressure, and a VCO that oscillates at a frequency corresponding to the output S pressure of the loop filter. A PLL synthesizer comprising a frequency divider that divides the VCO output signal based on a frequency division number specified from the outside and feeds it back to the PFC input, depending on the first signal generator output signal. A second signal generator that generates at least one or more pulse signals that determines a ratio of a high level to a low level during a period in which the charge pump switch circuit conducts is provided, and the charge pump circuit includes a plurality of types of S currents. A constant current source having a constant value, and an auxiliary switch circuit for switching the current value, wherein the output signal of the second signal generator is output during a period in which the switch circuit of the charge pump conducts. The auxiliary switch circuit is switched based on the switch signal, and the average value of the current value passed by the switch circuit of the charge pump is eliminated, whereby the loop characteristic is changed according to the phase difference between the input signal and the reference signal. (2) In addition, since the steady-state phase difference after pulling in the frequency of the PLL synthesizer is set to zero, the transfer impedance of the loop filter must be infinite at DC. Configuration is used.

In contrast to the conventional method, in the present invention, by using the configuration (1) for the PFC and the charge pump circuit, even if the phase difference between the input signal V and the reference signal R is a small value less than π, By detecting this, the output value of the charge pump can be changed. In addition, by using the configuration of the above (2) for the loop filter, the stationary phase error becomes zero. Therefore, in the frequency switching process, the bandwidth is automatically increased and the transient response of the PLL synthesizer becomes faster, and after the frequency is switched, the bandwidth is automatically narrowed and the phase noise component included in the reference signal R of the PLL synthesizer is removed. can do. Even small phase noise of less than π in the PFC input signal V due to disturbance in the steady state is detected and automatically widened, so that it is possible to quickly return to the steady state.

Further, by mounting the PLL synthesizer according to the present invention as a local oscillator in a wireless communication device, communication quality can be improved. Simple explanation of the drawing Si

FIG. 1 is a circuit configuration diagram showing a first embodiment of the PLL synthesizer of the present invention, and FIG. 2 shows the operation of the phase frequency comparator and the first signal generator of FIG. FIG. 3 is a diagram showing the phase difference versus the average output of the charge pump in FIG. 1, and FIG. 4 is a circuit diagram showing a second embodiment of the PLL synthesizer of the present invention. FIG. 5 is a timing chart showing the operation of the delay element and the OR circuit in FIG. 4, and FIG. 6 is a view showing the phase difference versus the average output of the charge pump in FIG. FIG. 7 is a circuit diagram showing a third embodiment of the PLL synthesizer of the present invention. FIG. 8 is a timing chart showing the operation of the delay element and the exclusive OR circuit of FIG. FIG. 9 is a circuit diagram showing a fourth embodiment of the PLL synthesizer of the present invention. FIG. 10 is a circuit diagram showing a fifth embodiment of the PLL synthesizer of the present invention. FIG. 11 is a diagram showing the phase difference versus the average output of the charge pump in FIG. 10. FIG. 12 is a circuit configuration diagram of a wireless communication terminal using the PLL synthesizer of the present invention. FIG. 13 is a typical circuit configuration diagram of a conventional PLL synthesizer. FIG. 13 is a circuit configuration diagram of the phase / wave number comparator used in the PLL synthesizer of FIG. 13, and FIG. 15 is a timing chart showing the operation of the phase / wave number comparator of FIG. Figure 16 shows the conventional FIG. 17 is a circuit configuration diagram showing a variable gain type PLL synthesizer. FIG. 17 is a circuit configuration diagram of a phase frequency comparator used in the PLL synthesizer shown in FIG. 16, and FIG. FIG. 17 is a timing chart showing the operation of the phase frequency comparator of FIG. 17, and FIG. 19 is a timing chart showing the phase difference when the input frequency is switched. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a first embodiment of a PLL synthesizer of the present invention. In this example, the PLL synthesizer detects a positive phase difference of the input signal V with respect to the reference signal R, and generates a first pulse signal DB from which a high-level and low-level temporal ratio is determined. PFC 1 that outputs a second pulse signal UB that detects the negative phase difference of the input signal V with respect to the reference signal R and that determines the ffl-like ratio between the high level and the mouth level Based on the first pulse signal DB and the second pulse signal UB, a pulse signal LD having a time ratio between a high level and a low level is determined depending on the absolute value of the phase difference between the input signal V and the reference signal R. The time ratio between the first signal generator 8 to be output and the high level and the π level during the period in which the switch circuit of the charge pump conducts depends on the output signal LD of the first signal generator 8. A second signal that generates a pulse signal Based on the output signal of the generator 9, the constant S current source 12 n, 12 p, the inverting circuit 10, and the second signal generator 9, the current of the constant current source 12 n, 12 Auxiliary switch circuit 1 In, lip for supplying or interrupting I 2, constant current sources 4 n, 4 p, inverting circuit 2, and first and second output signals DB, UB of PFC 1 Constant-current switch 4 n, 4 p Current I 1 and auxiliary switch circuit 1 1 n, 1 1 p Output current of the switch circuit 3n, 3 p A filter 5 that removes a noise component superimposed on the charge pump output current ft and outputs a DC voltage by converting the signal into an S pressure, so that the transfer impedance in the DC is infinite. The VCO 6 oscillates at a frequency corresponding to the output S pressure of the active filter, and the V C06 output signal is frequency-divided based on an externally specified frequency division number and returned to the PFC 1 input. It is composed of a frequency divider 7.

Next, the operation of this embodiment will be described. The PFC 1 in FIG. 1 uses the configuration shown in FIG. 14, and when the phase difference between the input signal V and the reference signal R is positive, the symbol DB becomes a pulse signal, and the phase difference becomes negative. In this case, the signal UB becomes a pulse signal. Otherwise, each signal remains high. The IW-like ratio of these pulse signals when they are at a low level per unit time is proportional to the magnitude of the phase difference. Further, the output LD of the first signal generator 8 is at a high level when the phase difference is zero, and is at an α-level when the absolute value of the phase difference is 2π, since the output LD of the first signal generator 8 is DB and UB. In other cases, the pulse ratio is such that the temporal ratio of the CI level per unit time ffl is proportional to the absolute value of the phase difference. FIGS. 2 (a) to 2 (c) show typical timing diagrams showing the operation of the PFC 1 and the first signal generator 8.

(a) corresponds to the case where the phase difference of V with respect to R is zero, and (b) and (c) correspond to the case where the phase difference is positive and negative, respectively. (B),

According to (c), the period during which the output signal LD of the first signal generator 8 takes the low level (T1 in the figure) is the period during which either the signal UB or DB is at the mouth level, that is, the charge pump It corresponds to the period during which one of the switch circuits 3 p and 3 n is conducting.

Here, the period in which LD takes the α-level is T 1, the period in which the LD takes the high level is D 2, and the time ratio duty at which the LD is at the high level per unit time is defined by Equation 1. From this, duty = 0 corresponds to the absolute value of phase difference 2 π And duty = 1 corresponds to zero phase difference.

T 2

d u y = number

T 1 + T 2

Next, the operation of the second signal generator 9 will be described. The second signal generator 9 generates a pulse signal in which the time ratio between the high level and the low level within one period is determined based on the output signal LD of the first signal generator 8. Here, the ratio of the time during which the output of the second signal generating circuit 9 takes a high level to the 期間 1 period is defined as r ate. As the input / output characteristics of the second 侰 signal generator 9, the configuration is such that r ate is an increasing function with respect to d uty. Although the functional form of the input / output characteristics of the second signal generation circuit is not particularly limited, it is assumed that r ate = duty in the present embodiment.

As shown in FIG. 1, the auxiliary switch circuits l ln and 11 p are configured to conduct when the output of the second 侰 signal generator 9 is at the mouth level. Therefore, the smaller the duty (the larger the phase difference), the smaller the rate, so that when the auxiliary switch circuits 11n and 11p conduct, the W-like ratio accumulates. Also, the larger the duty (the smaller the phase difference), the larger the ratate, so that the intermittent ratio decreases when the auxiliary switch circuits 1 ln, 11 p conduct. From the above, the average ¾ow value I a V e that the charge pump supplies to the loop filter 5 is expressed as in Equation 2.

I ave = (ld uty) {Il + (l- rate) I21 ··· 2 where I l = l mA, I 2 = 2 mA, calculated for the duty (phase difference) of I ave Figure 3 shows the characteristics. The lave shows nonlinear characteristics with respect to the phase difference, and the slope in Fig. 3 corresponds to the loop gain. As can be seen from Fig. 3, the larger the phase difference is, the larger the loop gain is (increased slope) and the PLL synthesizer is broadband. On the contrary, the smaller the phase difference is, the smaller the loop gain is (decreased slope). PLL Synthesizers And

Since the transfer impedance of the loop filter is infinite at DC, the steady-state phase error is zero. Therefore, during the frequency switching process, the bandwidth is automatically widened and the transient response of the PLL synthesizer becomes fast, and after the frequency switching, the bandwidth is automatically narrowed to remove the phase noise component contained in the reference signal R of the PLL synthesizer. can do.

FIG. 4 is a configuration diagram showing a second embodiment of the PLL synthesizer according to the present invention. The PLL synthesizer of the present embodiment has the same PFC 1 as in the first embodiment, the first signal generator 8 as in the first embodiment, and the output signal of the first signal generator 8. A delay element 21 for delaying the LD by the dt time, a first signal generator output LD and an delay circuit 21 for obtaining the sum of the outputs of the delay element 21 1 and the same as in the first embodiment. A charge pump, the same loop filter 5 as in the first embodiment, the transfer impedance of which is infinite at DC, the VCO 6 as in the first embodiment, and the first embodiment. Composed of the same diversion device 7 as

Next, the operation of this embodiment will be described. The PFC1 detects a phase difference between the input signal R and the reference signal V, and generates pulse signals DB and UB. The first signal generator 8 detects the absolute value of the phase difference between the input signal R and the reference signal V by determining the logical precision of DB and UB, and generates a pulse signal LD. 1 indicates that the LD is delayed for dt time, and the OR circuit 22 determines the logical sum of the output of the delay element and the LD.

FIGS. 5 (a) to 5 (c) show typical timing diagrams illustrating an operation example of the delay element 21 and the OR circuit 22. FIG. As in FIG. 2, the time when the output signal of the first signal generator 8 takes a single level is T1, and the time when the output signal takes a high level is T2. Here, duty is defined by using Equation 1. Also, the ratio of the delay time dt to T 1 + T 2 is de 1 ta, and the logic for T 1 period is The ratio of the time during which the output of the sum circuit 22 takes the high level is defined as rate. Where (1 6 1 1 & the relationship between d 1, d 2, and d 数 is expressed by Equation 3.

d t

d e l t a = number 3

T 1 + T 2

Fig. 5 (a) corresponds to the case where de l t a ≥ d u t y, where r a t e is represented by equation (4).

d u t

r a t e = number 4

1—d u t y

Also, FIG. 5 (b) corresponds to the case where delta <duty, delta <(1-duty), and rate in this case is expressed by Equation 5.

d e l t a

r a t e = number 5

1—d u t y

Also, FIG. 5 (c) corresponds to the case of del t a≥ (1-1 d u t y), where r a t e is represented by Equation 6.

r ate = 1 Equation 6 Here, the average output current of the charge pump is obtained using Equations 1 to 6. Fig. 6 shows the average current lave with respect to duty (phase difference) when I l = lmA and I 2 = 2mA. From Fig. 6, I ave is nonlinear with two break points for phase difference. When the phase difference is large, the loop gain is increased (increased slope) and the PLL synthesizer is widened. On the contrary, when the phase difference is small, the loop gain is decreased (slope is small) and the PLL is reduced. The synthesizer will be narrowed. As shown in Fig. 6, the position of the break point can be controlled by adjusting the traveling time d t of the traveling element to W and changing de 1 ta.

The transfer impedance of the loop filter is infinite at DC. Therefore, the stationary phase difference is zero. Therefore, in the frequency switching process, the band width is automatically widened and the transient response of the PLL synthesizer becomes faster, and after the frequency switching, the band is automatically narrowed and the phase noise component included in the reference signal R of the PLL synthesizer is removed. can do.

FIG. 7 is a configuration diagram showing a third embodiment of the PLL synthesizer according to the present invention. The PLL synthesizer of the present embodiment includes the same PFC 1 as in the first embodiment, the same first signal generator 8 as in the first embodiment, and the same traffic control as in the second embodiment. An element 21; an exclusive-OR circuit 31 for obtaining an exclusive-OR of the first signal generator output LD and the output of the delay element 21; the same charge pump as in the first embodiment; From the same loop filter 5 as in the embodiment, in which the transfer impedance in the direct current is infinite, the same VCO 6 as in the first embodiment, and the same divider 7 as in the first embodiment. Composed,

Next, the operation of the present embodiment will be described. The PFC 1 detects a phase difference of the input signal R with respect to the reference signal V, and generates pulse signals DB and UB. The first signal generator 8 detects the absolute value of the phase difference between the input signal R and the reference signal V by calculating the logical value of the DB and UB, and generates a pulse signal LD. Delays the LD by dt time, an exclusive OR circuit 31 obtains the exclusive OR of the delay element output and the LD, and FIG. Exclusive »A typical timing diagram showing an example of the operation of the logical sum circuit 31. A comparison between Figs. 8 (a) to (c) and Figs. 5 (a) to (c) shows that The output of the exclusive-OR circuit 31 in Fig. 7 is exactly the same as the output of the OR circuit 22 in Fig. 4. Therefore, the third embodiment has the same functions as the second embodiment.

Here, the average output current of the charge pump is obtained using Equations 1 to 6. The average S flow I a V e has the characteristics shown in Fig. 6, and the phase difference is large. As the loop gain increases (increased slope), the PLL synthesizer has a wider bandwidth, and conversely, as the phase difference is smaller, the loop gain decreases (increased slope), and the PLL synthesizer has a narrower band.

Since the transfer impedance of the loop filter is infinite at DC, the steady-state phase error is zero. Therefore, in the frequency switching process, the frequency band is automatically widened and the transient response of the PLL synthesizer becomes fast, and after the frequency switching, the frequency band is automatically narrowed and the phase noise component included in the reference signal R of the PLL synthesizer is removed. be able to.

FIG. 9 is a configuration diagram showing a fourth embodiment of the PLL synthesizer according to the present invention.

The PLL synthesizer of the present embodiment includes the same PFC 1 as in the first embodiment, the same first signal generator 8 as in the first embodiment, and the first LD generator 8 output LD. Oversampling type digital filter 41 that has a transmission zero at the frequency of the reference signal R and an integer multiple of the frequency of the reference signal R, and a delta-sigma that converts the output of the digital filter 41 into a 1-bit digital signal sequence. A transformer W 42, the same charge pump as in the first embodiment, the same loop filter 5 as in the first embodiment, the transfer impedance of which is infinite at DC, and the first It is composed of the same VCO 6 as the embodiment of the first embodiment and the same frequency divider 7 as the first embodiment.

Next, the operation of this embodiment will be described. The PFC 1 detects a phase difference between the input signal R and the reference signal V, and generates pulse signals DB and UB. The first signal generator 8 detects the absolute value of the phase difference between the input signal R and the reference signal V by calculating the logical precision of the DB and UB, and generates a pulse signal LD. The digital filter 41 samples the LD at a high speed, and outputs the frequency component of the reference signal and its high frequency. Since the wave component is removed, numerical data proportional to the phase difference is output. The number of bits of the digital filter 41 is not particularly limited. However, if the number of bits is set to 4 bits for simplicity and the phase difference 2π is configured to correspond to the numerical value "10000", the output numerical data and The relationship in Table 1 holds for the absolute value of the phase difference,

table 1

When the most significant bit of the numerical data is “0”, the delta-sigma converter 8H converter 42 converts the lower 3 bits of the numerical data into a 1-bit digital signal sequence DS. If the phase difference is 1.25π, the input data of the delta 'sigma converter is "101", so that DS is synchronized with the high sampling frequency and 5 samples out of 8 samples are high level. When the * high-order bit of the numerical data is "1", the delta-sigma modulator is configured to output and control a high level. The high level at the delta-sigma modulator output DS Table 1 shows the rate of occurrence of

The generation ratio of the single level and the high level of such a 1-bit digital signal sequence DS is inverted by the inverting circuit 43. The output of the inverting circuit 43 controls the auxiliary switch circuits 11n and lip. charge The time ratio in which the auxiliary switch circuits 11n and 11p conduct during the period in which the pump switch circuits 3n and 3p conduct is proportional to the phase difference. Here, duty is defined by Equation 1. If the ratio of the time when the output of the first signal generator 8 takes the high level to the time when the output signal of the first signal generator 8 takes the triangular level is defined as rate, then rate = duty holds.

Therefore, the average current I a V e that the charge pump supplies to the loop filter 5 can be obtained from Equation 2.

Here, when I l = lm A and I 2 = 2 mA, the characteristics of I a V e with respect to duty (phase difference) are as shown in Fig. 3 when the number of bits of digital filter 41 is selected to be sufficiently large. Be the same. From Fig. 3, the lave shows nonlinear characteristics with respect to the phase difference. The larger the phase difference is, the more the loop gain increases (increased gradient), and the PLL synthesizer becomes broader. As the loop gain decreases (increases in slope), the bandwidth of the PLL synthesizer becomes narrower.

Since the transfer impedance of the loop filter is infinite at DC, the steady-state phase error is zero. Therefore, during the frequency switching process, the frequency band is automatically widened to increase the transient response of the PLL synthesizer, and after the frequency switching, the band is automatically narrowed to remove the phase noise component contained in the reference signal R of the PLL synthesizer. can do.

In the four embodiments described above, the breakpoint occurs in the average output S flow characteristic with respect to the phase difference shown in FIG. 6 in the second and third embodiments, so that the loop gain of the PLL synthesizer increases at the breakpoint. As a result of the discontinuous change, the effect of this discontinuous change is that a small jump in frequency occurs during the frequency switching process. Depending on the application, this jump in frequency may not be desirable, but the number of break points Can be reduced by increasing the loop gain change by adding Here, as a fifth embodiment, a method of increasing the number of the break points to reduce the change in the slope (loop gain) at the break points will be described. FIG. 10 shows four break points. FIG. 4 is a configuration diagram for the case of having an inverting circuit 23, a traveling rod 24, an OR circuit 25, an auxiliary switch circuit 26n, 26p, and a constant S flow source 2 in the configuration of FIG. 7 n and 27 p (current value I 3) are added. Assuming that the running time of the extending element 24 is dt ′, de 1 ta ′ is defined in the same manner as in Equation 3, and this is shown in Equation 7.

d t '

d e l t a '=

Number 7

T 1 + T 2

Also, r ate 'is defined in the same way as Equations 4 to 6. If d e 1 t a '≥ d u t y, r a t e' is expressed by Equation 8.

d u t y

r a t e 'number 8

1—d u t y

In addition, in the case of delta, dduty, delta '(11-duty), rate' is expressed by equation (9).

d e l t a '

r a t e '= your 9

1—d u t y

In the case of d e l t a '≥ (l-d u t y), r a t e' is expressed by the number 10.

r a t e '= 1 Equation 1 0 Here, the average output I a V e' supplied by the charge pump to the loop filter is expressed as Equation 1 1.

Iave '= (1 -duty) {I 1 + (1 -rate) I 2 + (1 -rate') I 3} Number 1 1 Here, for example, delta = 0.1, delta '= 0. 4, I

Fig. 11 shows the characteristics of l ave e 'with respect to duty (phase difference) when 1 = 1 2 = 1 3 = l mA. As shown in Fig. 11, the number of break points is

18

Four The change in the slope at the break point can be reduced.The configuration in Fig. 10 is for the case where the number of break points is four, but the constant current source, auxiliary switch circuit, and inverting circuit It is possible to further increase the number of breakpoints by increasing the number of delay elements and OR circuits. This further reduces the change in the slope of the average output compressibility at the break point.

Although the above description is for the second embodiment, the same method can be used for the third embodiment.

The configuration and characteristics of the loop filters in the first to fifth embodiments are not particularly limited, except that the transfer impedance is infinite at direct current in order to reduce the stationary phase error to zero. For example, a configuration of a series connection type of a resistor and a capacitor, or a configuration of a refiner using an arithmetic operation unit is used.

* An embodiment of a wireless communication device using the frequency synthesizer of the present invention will be described later with reference to FIG. The wireless communication device includes a PLL synthesizer 82, a transmission circuit 81 that generates a transmission signal based on an oscillation signal from the PLL synthesizer 82, and a duplexer 84 that band-limits the transmission signal. An antenna 85 for transmitting and receiving a radio signal, a receiving circuit 83 for decoding a received signal based on the oscillation signal of the PLL synthesizer, and a control circuit 86 for controlling these. Done,

The control circuit 86 controls the state of the wireless communication device based on the data received by the receiving circuit 83, and instructs the frequency to oscillate to the PLL synthesizer 82. The PLL synthesizer 82 receives the instruction. The supplied oscillation frequency is supplied to the transmission circuit 81 and the reception circuit 83. Based on the oscillation frequency given from the synthesizer 82, a transmission wave is generated by modifying the transmission signal from the control circuit 86, and after the unnecessary signal component is suppressed by the duplexer 84, the antenna Sent from 8 5

The signal received from the antenna 25 is input to the receiving circuit 83 after the unnecessary signal component is suppressed by the splitter 84. The receiving circuit 83 recovers the received signal using the torsion wave number from the PLL synthesizer 82 and supplies the recovered result to the control circuit 86.

The control circuit 86 converts the transmitted / received signals into input / output signals (audio, image, data, etc.).

As described above, by using any of the configurations shown in FIGS. 1 to 9 and FIG. 10 for the PLL synthesizer, when the phase difference is large, the loop band is widened, and the frequency is rapidly increased. Can be withdrawn. Also, when the phase difference becomes smaller due to the frequency pull-in, the loop band can be narrowed and the noise can be reduced.

In addition, by applying the high-speed frequency switchable and low-noise PLL synthesizer according to the present invention to a wireless communication terminal, the quality of communication can be improved.

As described above, the PLL synthesizer of the present invention can be used as a variable loop gain type PLL synthesizer capable of reducing loop gain even for a small phase difference, and a variable loop gain type PLL synthesizer used in a wireless communication terminal or the like. Useful as

Claims

The scope of the claims

1. a phase frequency comparator that detects a phase difference between an input signal and a reference signal, and outputs a first pulse signal that determines a time ratio between a high level and a mouth level depending on the phase difference; Providing a constant current source and a first switch circuit, controlling the first switch circuit based on the first pulse signal, and supplying or interrupting the current of the first constant current source. A charge pump for outputting a current corresponding to the phase difference; removing noise having the same frequency component as the reference signal in the output S flow from the charge pump; smoothing the output current; A loop filter that outputs a DC voltage by converting to a voltage, a voltage-controlled oscillator that oscillates at a frequency corresponding to the DC voltage output from the loop filter, and a frequency division number specified from the outside. In a PLL synthesizer including a frequency divider that divides an output signal of the voltage-controlled oscillator and outputs a frequency as the input signal, the first switch circuit becomes conductive depending on the absolute value of the phase difference. A pulse signal generator that outputs a third pulse signal that determines a specific ratio between the high level and the low level of the period ffl, wherein the charge pump includes a second constant current source and a second switch circuit. During the period in which the first switch circuit is conducting, the second switch circuit is controlled based on the third pulse signal, and the second constant S flow source is controlled. PLL synthesizer characterized by supplying or blocking S flow,

2. a first signal generator that outputs a second pulse signal in which a high-level / low-level closed ratio is determined depending on an absolute value of the phase difference; A second pulse signal for outputting a third pulse signal in which the ratio between the high level and the single level during the period in which the first switch circuit is conducting is determined depending on the second pulse signal. And a signal generator 3. The PLL synthesizer according to claim 1, wherein the PLL synthesizer is characterized in that:

3. The time ratio between the high level and the α-level of the third pulse signal during the period when the first switch circuit is conducting 18] is determined by the difference between the high level and the low level of the second pulse signal. The PLL synthesizer according to claim 2, wherein the PLL synthesizer has the same temporal ratio.

4. The second signal generator samples the second pulse signal at a high speed, and removes a frequency of a reference signal and a frequency that is an integral multiple thereof, and an over-sampling digital filter. 3. The PLL synthesizer according to claim 2, wherein the PLL synthesizer comprises a delta-sigma converter that converts an output from the sampling type digital filter into a 1-bit digital signal sequence.

5. A phase frequency comparison S that detects a phase difference of the input signal with respect to the reference signal and outputs a first pulse signal in which the time ratio between the high level and the α-level is determined depending on the phase difference; A first constant current source and a first switch circuit are provided, and the first switch circuit is controlled based on the first pulse signal to supply a current of the first constant current source. Or a charge pump that outputs a current corresponding to the phase difference by cutting off or shutting off, and removing noise having the same frequency component as a reference signal that is output to the output tt stream from the charge pump. A loop filter that outputs DC S pressure by smoothing the S flow and converting it to a voltage, an S pressure controlled oscillator that generates at a frequency corresponding to the DC S pressure output from the loop filter, and is specified externally Above In a PLL synthesizer composed of a frequency divider that divides an output signal of a pressure-controlled oscillator and outputs the divided signal as an input signal, a time ratio between a high level and a low level is determined depending on the absolute value of the phase difference. A first signal generator for outputting a whole second pulse signal, a grinding element for propagating the second pulse signal, a second pulse signal and the delay element An OR circuit that outputs a logical sum of the delay signal from the first and second delay circuits, and the charge pump includes a second constant current source and a second switch circuit, and the first switch circuit conducts. A PLL synthesizer that controls the second switch circuit based on an output signal from the OR circuit during a period during which the current flows from the second constant current source. ,

6. The loop gain of the PLL synthesizer is switched even when the phase difference is less than π by making the delay time of the delay element smaller than a certain value. The PLL synthesizer according to claim 5, which is in the scope of demand.

7. A phase frequency comparator that detects a phase difference between the input signal and the reference signal, and outputs a first pulse signal that determines a time ratio between a high level and a low level depending on the phase difference; : Provide a g source and a first switch circuit, control the first switch circuit based on the first pulse signal, and supply or cut off the flow of the first constant S flow source By doing so, a charge pump that outputs an S current corresponding to the phase difference, and a noise having the same frequency component as a reference signal superimposed on the output from the charge pump are removed, and the output current is reduced. A loop filter that outputs DC S pressure by smoothing and converting it to S pressure, a pressure-controlled oscillator that oscillates at a frequency corresponding to the DC voltage output from the loop filter, and a frequency division number specified from the outside Based on the above In a PLL synthesizer composed of a frequency divider that divides an output signal of a pressure-controlled oscillator and outputs the divided signal as an input signal, a time ratio between a high level and a low level is determined depending on the absolute value of the phase difference. A first signal generator that outputs a second pulse signal, a delay element that delays the second pulse signal, and delay elements that are different from each other (Ν is an integer of 2 or more); Second pulse signal and each delay from the 遅延 delay elements N logical sum circuits for outputting a logical sum with a signal, wherein the charge pump is composed of N constant current sources, the first constant S current source being different from the first constant S current source, and the first constant S current source being the first constant S current source. N switch circuits different from the above switch circuits, and based on each output signal from the N pieces of Rika circuits during the period when the first switch circuit is conducting. A PLL synthesizer that controls each of the N switch circuits and supplies or shuts off each of the N constant S current sources.

8. A phase frequency comparator that detects a phase difference between the input signal and the reference signal and outputs a first pulse signal that determines a time ratio between a high level and a low level depending on the phase difference; ¾ Lowering the flow source and the first switch circuit, controlling the first switch circuit based on the first pulse signal, and supplying or blocking the compress flow of the first constant S flow source Thus, a charge pump that outputs an S flow corresponding to the phase difference, a noise having the same frequency component as the reference signal fi * in the output S flow from the charge pump is removed, and the output flow is A loop filter that outputs a DC voltage by smoothing and converting it to a Fob pressure; a voltage controlled oscillator that oscillates at a frequency corresponding to the DC S pressure output from the loop filter; Based on the above In a PLL synthesizer composed of a frequency divider which divides the output signal of the voltage controlled oscillator and outputs it as the input signal, the time ratio between the high level and the π-level depends on the absolute value of the phase difference. A first signal generator that outputs a determined second pulse signal; a delay element that delays the second pulse signal; and an exclusive control of the second pulse signal and the delay signal from the delay element. An exclusive OR circuit for outputting a logical sum, wherein the charge pump includes a second constant current source and a second switch circuit, and a period during which the first switch circuit is conducting. In the above, the second switch circuit is controlled based on the output signal from the exclusive-OR circuit. And a PLL synthesizer characterized in that the current of the second constant source is supplied or cut off.

9. The characteristic feature is that the loop gain of the PLL synthesizer is switched even when the phase difference is smaller than π by making the delay time of the delay element smaller than a certain value. 9. The PLL synthesizer according to claim 8, wherein:

10. A phase frequency comparator that detects a phase difference between the input signal and the reference signal and outputs a first pulse signal whose time ratio between high level and low level is determined depending on the phase difference; By providing a current source and a first switch circuit, controlling the first switch circuit based on the first pulse signal, and supplying or interrupting the current of the first constant current source, A charge pump that outputs the S current corresponding to the phase difference, and a noise from the delta charge pump that has the same frequency component as the reference signal superimposed on the current * is removed, and the output current is smoothed and the voltage is reduced. A loop filter that outputs a DC voltage by converting to a DC voltage, a voltage-controlled oscillator that oscillates at a frequency corresponding to the DC voltage output from the loop filter, and a frequency division number specified from the outside In a PLL synthesizer consisting of a frequency divider that divides the output signal of the S-pressure controlled oscillator and outputs it as the input signal, the ratio of the high level to the low level depends on the absolute value of the phase difference. A first signal generator that outputs a second pulse signal that defines the following, and N (N is an integer of 2 or more) delay elements having different delay times for delaying the second pulse signal. And N exclusive OR circuits for outputting exclusive OR of the second pulse signal and each of the N signals from the N N elements. And N switch circuits other than the first constant S flow source and N switch circuits different from the first switch circuit.

In period ra 內 when one switch circuit is conducting, the N exclusive A PLL synthesizer characterized by controlling each of the N switch circuits based on each output signal from the Riwa circuit, and supplying or interrupting each current of the N constant current sources.

11. The PLL synthesizer according to claim 1, wherein a transfer impedance of the loop filter is infinite at direct current.

12. A control circuit for controlling a wireless communication device, a frequency synthesizer, a transmission circuit for generating a transmission signal based on an oscillation signal from the control circuit and the frequency synthesizer, and a band for transmitting the transmission signal. A frequency divider for limiting the signal, an antenna for transmitting and receiving a radio signal, and a receiving circuit for demodulating a received signal based on an oscillation motherboard of the frequency synthesizer, and via the control circuit. 12. A wireless communication device for inputting and outputting audio and a plane image, wherein the frequency synthesizer is the PLL synthesizer according to any one of claims 1 to 11.