KR20080077515A - Method of detecting locking of a phase and phase locked loop circuit for performing the same - Google Patents

Method of detecting locking of a phase and phase locked loop circuit for performing the same Download PDF

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Publication number
KR20080077515A
KR20080077515A KR1020070017162A KR20070017162A KR20080077515A KR 20080077515 A KR20080077515 A KR 20080077515A KR 1020070017162 A KR1020070017162 A KR 1020070017162A KR 20070017162 A KR20070017162 A KR 20070017162A KR 20080077515 A KR20080077515 A KR 20080077515A
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KR
South Korea
Prior art keywords
signal
phase
output
phase detection
flip
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KR1020070017162A
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Korean (ko)
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이한수
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엠텍비젼 주식회사
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Priority to KR1020070017162A priority Critical patent/KR20080077515A/en
Publication of KR20080077515A publication Critical patent/KR20080077515A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

A phase locking detection method and a PLL circuit for performing the same are provided to compensate a locking error generated in a window section of a control voltage by using a counting circuit in the PLL circuit. A PLL circuit for performing a phase locking detection method includes a phase detector(104), a charge pump(106), a loop filter(108), a voltage controlled oscillator(110), and a locking detection unit(114). The phase detector compares the phase of a first frequency signal with that of a second frequency signal, and outputs a first phase detection signal and a second phase detection signal based on the comparison result. The charge pump outputs predetermined charges in response to the phase detection signals outputted from the phase detector. The loop filter outputs a control voltage corresponding to the charge quantity outputted from the charge pump. The voltage controlled oscillator outputs a frequency signal in response to the control voltage outputted from the loop filter. The locking detection unit compares the phase detection signals outputted from the phase detector in a digital manner, and detects a locking state of the PLL circuit.

Description

TECHNICAL OF DETECTING LOCKING OF A PHASE AND PHASE LOCKED LOOP CIRCUIT FOR PERFORMING THE SAME

1 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

2 is a circuit diagram showing the configuration of the phase detector of FIG.

3 is a circuit diagram illustrating the locking detection unit of FIG. 1 according to an exemplary embodiment of the present invention.

4A and 4B are timing diagrams illustrating a phase locking detection process in an unlocked state.

4C is a timing diagram illustrating a phase locking detection process in the locked state.

5 is a circuit diagram illustrating a locking detector according to another exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating the sub counting unit of FIG. 5.

7A and 7B are timing diagrams illustrating a phase locking detection process in an unlocked state.

7C is a timing diagram illustrating a phase locking detection process in the locked state.

7D is a timing diagram showing a change in control voltage over time.

The present invention relates to a phase locking detection method and a phase locked loop circuit for performing the same, and more particularly, to a phase locking detection method for detecting whether a lock is compared by digitally comparing the outputs of a phase detector and a phase lock for performing the same. Relates to a loop circuit.

A phase locked loop circuit (PLL circuit) is a circuit for generating a frequency signal having a fixed frequency and includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator.

However, in the conventional phase locked loop circuit, when the phase difference between the reference frequency signal and the feedback frequency signal input to the phase detector falls within a predetermined range, the phase difference is not accurately recognized. As a result, the voltage controlled oscillator recognized that it was locked even though it was not locked, and stopped operating after outputting a specific frequency signal. As a result, the device using the phase locked loop circuit was operated with the unwanted frequency signal as the reference signal, so that the device could malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase locking detection method capable of accurately detecting whether or not locking and a phase locked loop circuit for performing the same.

In order to achieve the above object, a phase locked loop circuit according to a preferred embodiment of the present invention includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a locking detector. The phase detector compares a phase of a first frequency signal and a second frequency signal and outputs a first phase detection signal and a second phase detection signal according to the comparison result. The charge pump outputs predetermined charges in response to the phase detection signals output from the phase detector. The loop filter outputs a control voltage corresponding to the amount of charge output from the charge pump. The voltage controlled oscillator outputs a frequency signal according to the control voltage output from the loop filter. The locking detection unit digitally compares phase detection signals output from the phase detector to detect whether the phase locked loop circuit is locked.

According to a preferred embodiment of the present invention, a phase locking detection method compares phases of a first frequency signal and a second frequency signal to detect a first phase detection signal having a first pulse width and a second phase detection having a second pulse width. Outputting a signal; And comparing the output phase detection signals to detect whether the frequency signals are phase locked, and outputting an output signal having information on the detection result. Here, the logic of the output signal when the pulse widths are the same is different from the logic of the output signal when the pulse widths are different.

Since the phase locking detection method and the phase locked loop circuit for performing the same detect the digital lock using the outputs of the phase detector, it is possible to precisely detect the locking. In particular, when the phase locked loop circuit uses a counting circuit, it is possible to compensate for a locking mistake that may occur in the window period of the control voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the phase locked loop circuit 100 (PLL circuit) of the present embodiment may include a first divider 102, a phase detector 104, and a charge pump. Charge Pump 106, Loop Filter 108, Voltage Controlled Oscillator 110, VCO, Second Divider 112, and Locking Detector 114. .

The first divider 102 divides the first frequency signal, that is, the reference frequency signal F1, into 1 / N (an integer of 2 or more) to output the first divided signal DF1. Here, the first frequency signal F1 is a high frequency signal used as the reference frequency of the phase locked loop circuit 100, and therefore should be generated constantly without being influenced by external temperature or the like. However, a high frequency oscillator (not shown) that generates a high frequency signal is sensitive to temperature and the like, and thus it is difficult to generate a high frequency signal that is kept constant. On the other hand, the low frequency oscillator may generate a low frequency signal which is kept constant while being hardly influenced by temperature or the like when using a crystal or the like. Therefore, the phase locked loop circuit 100 of the present embodiment divides and uses the first frequency signal, which is a high frequency signal, at low frequency using the first divider 102.

The second divider 112 divides the second frequency signal F2 output from the voltage controlled oscillator 110 into 1 / M (an integer of 2 or more) and outputs a second divided signal (DF2).

The phase detector 104 compares the phase of the first divided signal DF1 and the phase of the second divided signal DF2, and according to the comparison result, the first phase detection signal UP and the second having the first pulse width. A second phase detection signal DOWN having a pulse width is output. Here, the pulse width difference between the phase detection signals UP and DOWN corresponds to a phase difference between the first divided signal DF1 and the second divided signal DF2 as described later.

The charge pump 106 outputs charges corresponding to the pulse width difference between the phase detection signals UP and DOWN, and the output charges are stored in the loop filter 108. For example, the charge pump 106 retrieves the charges stored in the loop filter 108 when the second divided signal DF2 is earlier than the first divided signal DF1, and the second divided signal DF2 is the first. When charge is slower than the divided signal DF1, predetermined charges are supplied to the loop filter 108.

The loop filter 108 consists of, for example, a low pass filter (LPF) to store the charges output from the charge pump 106 and to remove unnecessary frequency bands. In addition, the loop filter 108 outputs a control voltage Vc corresponding to the stored resistance and a DC voltage. Here, the control voltage Vc becomes smaller when the second divided signal DF2 is faster than the first divided signal DF1, and becomes larger when the second divided signal DF2 is slower than the first divided signal DF1.

The voltage controlled oscillator 110 outputs a second frequency signal F2 having a frequency corresponding to the control voltage Vc in response to the control voltage Vc output from the loop filter 108. In detail, the voltage controlled oscillator 110 outputs the second frequency signal F2 having a lower frequency according to the smaller control voltage Vc when the second divided signal DF2 is faster than the first divided signal DF1. When the second divided signal DF2 is slower than the first divided signal DF1, the second frequency signal F2 having a higher frequency is output according to the increased control voltage Vc. The second frequency signal F2 thus output is divided into the second divider 112 and then input to the phase detector 104 again, and then the above process is repeated.

In other words, the phase locked loop circuit 100 forms a closed loop loop, and the above-mentioned until the phase of the first frequency signal (F1) and the second frequency signal (F2) is the same, that is, until the locked (Locking) Repeat the locking process. In particular, when the pulse width difference between the phase detection signals UP and DOWN falls within a predetermined range, unlike the conventional phase locked loop circuit which determines that the pulse width difference is locked even though it is not locked, The phase locked loop circuit 100 of the embodiment accurately detects whether or not the locking is performed using the locking detector 114 as described later.

The locking detector 114 receives the phase detection signals UP and DOWN from the phase detector 104 and compares the received phase detection signals UP and DOWN to determine whether the phase locked loop circuit 100 is locked. Detect whether or not. Then, the locking detection unit 114 outputs an output signal LDout having the detection result.

Hereinafter, the configuration and operation of the components of the phase locked loop circuit 100 will be described in detail.

2 is a circuit diagram showing the configuration of the phase detector of FIG.

Referring to FIG. 2, the phase detector 104 includes a plurality of D flip-flops 200 and 202, a delay unit 204, and a NAND gate 206.

The D flip-flops 200 and 202 output phase detection signals UP and DOWN using the divided signals DF1 and DF2 as clocks. In this case, the outputs of the D flip-flops 200 and 202 are fed back after being delayed by the delay unit 204 for a predetermined time so that a dead zone does not occur. Since such delay and feedback methods are well known methods, detailed descriptions thereof will be omitted.

3 is a circuit diagram illustrating the locking detection unit of FIG. 1 according to an exemplary embodiment of the present invention. 4A and 4B are timing diagrams showing a phase locking detection process in the unlocked state, and FIG. 4C is a timing diagram showing a phase locking detection process in the locked state.

Referring to FIG. 3, the locking detector 114 of the present embodiment includes a comparator 300 and a locking unit 302.

The comparator 300 includes a plurality of flipflops 304 and 306 and a plurality of delay elements. Here, flip-flops 304 and 306 are D flip-flops, but are not limited to D flip-flops.

The first phase detection signal UP is input to the data input terminal of the first flip-flop 304 without delay, and the delayed second phase detection signal DOWN is input to the clock input terminal. As a result, the first flip-flop 304 outputs the first comparison signal DFO1 corresponding to the first phase detection signal UP using the second phase detection signal DOWN as a clock.

The second phase detection signal DOWN is input to the data input terminal of the second flip-flop 306 without being delayed, and the delayed first phase detection signal UP is input to the clock input terminal. As a result, the second flip-flop 306 outputs the second comparison signal DFO2 corresponding to the second phase detection signal DOWN using the first phase detection signal UP as a clock.

The locking unit 302 includes an AND gate, and performs an AND operation on the comparison signals DFO1 and DFO2 output from the flip-flops 304 and 306 to determine whether the phase locked loop circuit 100 is locked. It determines whether or not, and outputs an output signal LDout having a determination result.

Hereinafter, an operation process of the phase locked loop circuit 100 having such a configuration will be described in detail with reference to FIGS. 4A to 4C.

First, an operation process of the locking detector 114 when the second divided signal DF2 is earlier than the first divided signal DF1 will be described with reference to FIG. 4A.

As shown in FIG. 4A, the second divided signal DF2 advances faster than the first divided signal DF1 by T time. In this case, the phase detector 104 outputs the first phase detection signal UP having a pulse width equal to the delay time τ of the internal delay unit 204, and the delay time τ and the phase difference T. The second phase detection signal DOWN having a pulse width corresponding to the sum of the time corresponding to the output is output. Thus, signals A, B, C, and D input to flip-flops 304 and 306 have a pulse signal as shown in FIG. 4A.

If the flip-flops 304 and 306 are D flip-flops and the input signal is triggered at the rising edge, then the first comparison output from the flip-flop 304 because the A signal is triggered at the rising edge of the B signal. Signal DFO1 has low logic as shown in FIG. 4A. In addition, since the D signal is triggered at the rising edge of the C signal, the second comparison signal DFO2 output from the flip-flop 306 has a high logic after a predetermined time. Subsequently, the comparison signals DFO1 and DFO2 are ANDed by the AND gate of the locking unit 302, so that the output signal LDout output from the locking unit 302 has low logic. Accordingly, the locking unit 302 detects that the phase locked loop circuit 100 is not locked, and transmits a detection result to a control unit (not shown). In this case, the controller detects that the phase locked loop circuit 100 is not yet locked, and continues the locking process of the phase locked loop circuit 100.

Secondly, the operation of the locking detector 114 when the second divided signal DF2 is slower than the first divided signal DF1 will be described in detail with reference to FIG. 4B.

As shown in FIG. 4B, the second divided signal DF2 proceeds slower by T time than the first divided signal DF1. In this case, the phase detector 104 outputs the second phase detection signal DOWN having a pulse width equal to the delay time τ of the internal delay unit 204, and the delay time τ and the phase difference T. The first phase detection signal UP having a pulse width corresponding to the sum of the corresponding time periods is output. Thus, signals A, B, C, and D input to flip-flops 304 and 306 have a pulse signal as shown in FIG. 4B.

If the flip-flops 304 and 306 are D flip-flops and the input signal is triggered at the rising edge, then the first comparison output from the flip-flop 304 because the A signal is triggered at the rising edge of the B signal. Signal DFO1 has high logic after a predetermined time as shown in FIG. 4B. In addition, since the D signal is triggered at the rising edge of the C signal, the second comparison signal DFO2 output from the flip-flop 306 has low logic. Subsequently, the comparison signals DFO1 and DFO2 are ANDed by the AND gate of the locking unit 302, so that the output signal LDout output from the locking unit 302 has low logic. Accordingly, the locking unit 302 detects that the phase locked loop circuit 100 is not locked and transmits a detection result to the control unit. In this case, since the controller is not locked yet, the controller continuously performs the locking process of the phase locked loop circuit 100.

Third, an operation process of the locking detector 114 when the phase locked loop 100 is locked will be described in detail with reference to FIG. 4C.

As shown in FIG. 4C, since the second divided signal DF2 is in phase with the first divided signal DF1, the phase detector 104 has a pulse width corresponding to the delay time τ of the delay unit 204. The first and second phase detection signals UP and DOWN are output. Signals A, B, C and D input to flip-flops 304 and 306 have a pulse signal as shown in FIG. 4B.

If the flip-flops 304 and 306 are D flip-flops and the input signal is triggered at the rising edge, then the first comparison output from the flip-flop 304 because the A signal is triggered at the rising edge of the B signal. Signal DFO1 has high logic after time t1 as shown in FIG. 4C. In addition, since the D signal is triggered at the rising edge of the C signal, the second comparison signal DFO2 output from the flip-flop 306 has a high logic after t1 time. Then, the comparison signals DFO1 and DFO2 are ANDed by the AND gate of the locking unit 302, so that the output signal LDout output from the locking unit 302 has a high logic after t1 time. Accordingly, the locking unit 302 detects that the phase locked loop circuit 100 is locked and transmits a detection result to the control unit. In this case, since the controller is locked, the locking process of the phase locked loop circuit 100 is stopped.

In other words, the locking detection unit 114 of the present invention outputs an output signal LDout having a first logic, for example, low logic, when the phase locked loop circuit 100 is not locked, and the phase locked loop circuit 100. Outputs an output signal LDout having logic different from the first logic, for example, high logic, when is locked. That is, the locking detector 114 detects whether the phase locked loop circuit 100 is locked through logic of the output signal LDout.

FIG. 5 is a circuit diagram illustrating a locking detector according to another exemplary embodiment of the present invention, and FIG. 6 is a circuit diagram illustrating the sub counting unit of FIG. 5. 7A and 7B are timing diagrams showing a phase locking detection process in the unlocked state, and FIG. 7C is a timing diagram showing a phase locking detection process in the locked state, and FIG. A timing diagram showing a change in the control voltage.

Referring to FIG. 5, the locking detection unit 114 of the present embodiment includes a comparator 500, a counting unit 502, and a locking unit 504.

Since the comparator 500 performs the same function as the comparator 300 of FIG. 3, a description thereof will be omitted.

The counting unit 502 includes a first sub counting unit 518 and a second sub counting unit 520.

At least one of the sub counting units 518 and 520 includes one or more D flip-flops 600, 602, and 604 as shown in FIG. 6, and compares the DFO1 and the output signals from the comparator 500. DFO2) is counted to output a first counting signal comprising Q1, Q2 and Q3 and a second counting signal comprising Q4, Q5 and Q6. These flip-flops 600, 602 and 604 are connected in series with each other and are a kind of shift register. In other words, the flip-flops 600, 602, and 604 serve to shift the corresponding comparison signal.

In general, the control voltage Vc input to the voltage controlled oscillator 110 is shaken before t3 time and has a constant value after t3 time as shown in FIG. 7D. That is, the phase locked loop circuit 100, which has not been locked before t3 time, is locked at t3 time. However, the phase locked loop circuit 100 may incorrectly determine that the control voltage Vc is small in the window period CW between t1 and t3 and thus is locked without detecting such a shake. Therefore, the locking detector 114 of the present embodiment shifts and counts the comparison signals DFO1 and DFO2 so that the phase locked loop circuit 100 does not recognize that the phase locked loop circuit 100 is locked in the window period CW. As a result, the phase locked loop circuit 100 using the locking detection unit 114 of the present embodiment can accurately track the time that is actually locked, so that various devices using the phase locked loop circuit 100 are stable frequency signals. Can be provided.

The locking unit 504 logically combines the counting signals output from the sub-counting units 518 and 520 to detect whether the phase locked loop circuit 100 is locked. For example, the three AND gates 522 may be used. 524 and 526).

Hereinafter, an operation process of the phase locked loop 100 including the locking detector 114 having such a configuration will be described in detail with reference to FIGS. 7A to 7D.

First, an operation process of the locking detector 114 when the second divided signal DF2 is earlier than the first divided signal DF1 will be described in detail with reference to FIG. 7A. However, since the process of generating the comparison signals DFO1 and DFO2 is the same as that of FIG. 4A, the process is omitted.

As shown in FIG. 7A, the second divided signal DF2 advances faster than the first divided signal DF1 by T time. In this case, the comparator 500 outputs the first comparison signal DFO1 having the low logic and the second comparison signal DFO2 having the high logic after a predetermined time.

Subsequently, the flip-flops included in the first sub counting unit 518 use the first divided signal DF1 as a clock to receive the first counting signals Q1, Q2 and Q3 corresponding to the first comparison signal DFO1. Output As a result, Q1, Q2 and Q3 each have low logic, so output NA1 of first end gate 522 has low logic.

In addition, the flip-flops included in the second sub counting unit 520 use the first divided signal DF1 as a clock to receive the second counting signals Q4, Q5 and Q6 corresponding to the second comparison signal DFO2. Output As a result, Q4 has high logic after t2 time, Q5 has high logic after t3 time, and Q6 has high logic after t4 time. Thus, the output NA2 of the second AND gate 524 has a high logic after t4 time.

Subsequently, the outputs NA1 and NA2 of the AND gates 522 and 524 are ANDed by the third AND gate 526, so that the output signal LDout of the third AND gate 526 is low logic. Has Therefore, the locking detector 114 determines that the phase locked loop circuit 100 is not locked.

Secondly, the operation of the locking detector 114 when the second divided signal DF2 is slower than the first divided signal DF1 will be described in detail with reference to FIG. 7B. However, since the process of generating the comparison signals DFO1 and DFO2 is the same as that of FIG. 4B, the process is omitted.

As shown in FIG. 7B, the second divided signal DF2 proceeds slower by T time than the first divided signal DF1. In this case, the comparator 500 outputs the first comparison signal DFO1 having the high logic and the second comparison signal DFO2 having the low logic after a predetermined time.

Subsequently, the flip-flops included in the first sub counting unit 518 use the first divided signal DF1 as a clock to receive the first counting signals Q1, Q2 and Q3 corresponding to the first comparison signal DFO1. Output As a result, Q1 has high logic after t2 time, Q2 has high logic after t3 time, and Q3 has high logic after t4 time. Accordingly, the output NA1 of the first AND gate 522 has a high logic after t4 time.

In addition, the flip-flops included in the second sub counting unit 520 use the first divided signal DF1 as a clock to receive the second counting signals Q4, Q5 and Q6 corresponding to the second comparison signal DFO2. Output As a result, Q4, Q5 and Q6 each have low logic.

Subsequently, the outputs NA1 and NA2 of the AND gates 522 and 524 are ANDed by the third AND gate 526, so that the output signal LDout of the third AND gate 526 is low logic. Has Therefore, the locking detector 114 determines that the phase locked loop circuit 100 is not locked.

Third, when the second divided signal DF2 is in phase with the first divided signal DF1, an operation process of the locking detector 114 will be described with reference to FIG. 7C. However, since the process of generating the comparison signals DFO1 and DFO2 is the same as that of FIG. 4C, the process is omitted.

As shown in FIG. 7C, the second divided signal DF2 proceeds with the same phase as the first divided signal DF1. In this case, the comparator 500 outputs the first comparison signal DFO1 and the second comparison signal DFO2 having high logic after t1.

Subsequently, the flip-flops included in the first sub counting unit 518 use the first divided signal DF1 as a clock to receive the first counting signals Q1, Q2 and Q3 corresponding to the first comparison signal DFO1. Output As a result, Q1 has high logic after t1 time, Q2 has high logic after t2 time, and Q3 has high logic after t3 time. Therefore, the output NA1 of the first AND gate 522 has a high logic after t3 time.

In addition, the flip-flops included in the second sub counting unit 520 use the first divided signal DF1 as a clock to receive the second counting signals Q4, Q5 and Q6 corresponding to the second comparison signal DFO2. Output As a result, Q4 has high logic after t1 time, Q5 has high logic after t2 time, and Q6 has high logic after t3 time. Therefore, the output NA2 of the second AND gate 524 has a high logic after t3 time.

Subsequently, the outputs NA1 and NA2 of the AND gates 522 and 524 are ANDed by the third AND gate 526, so that the output signal LDout of the third AND gate 526 is after t3. Have high logic Therefore, the locking detector 114 determines that the phase locked loop circuit 100 is locked.

In other words, the locking detection unit 114 of the present invention outputs an output signal LDout having a first logic, for example, low logic, when the phase locked loop circuit 100 is not locked, and the phase locked loop circuit 100. Outputs an output signal LDout having logic different from the first logic, for example, high logic, when is locked. That is, the locking detector 114 detects whether the phase locked loop circuit 100 is locked through logic of the output signal LDout. In addition, since the locking detection unit 114 of the present embodiment counts the comparison signals DFO1 and DFO2 in consideration of the window period CW as shown in FIG. 7D, the phase locked loop circuit 100 locks more precisely. It can check whether or not and output a stable frequency signal.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art having ordinary knowledge of the present invention will be able to make various modifications, changes, additions within the spirit and scope of the present invention, such modifications, changes and Additions should be considered to be within the scope of the following claims.

As described above, the phase locking detection method according to the present invention and the phase locked loop circuit for performing the same detect whether or not the digital lock using the output of the phase detector, the advantage that can accurately detect whether the locking There is this. In particular, when the phase locked loop circuit uses a counting circuit, there is an advantage of correcting a locking mistake that may occur in a window period of a control voltage.

Claims (15)

In a phase locked loop circuit, A phase detector for comparing phases of the first frequency signal and the second frequency signal and outputting a first phase detection signal and a second phase detection signal according to the comparison result; A charge pump for outputting predetermined charges in response to phase detection signals output from the phase detector; A loop filter outputting a control voltage corresponding to the amount of charges output from the charge pump; A voltage controlled oscillator for outputting a frequency signal according to the control voltage output from the loop filter; And And a locking detector for detecting whether the phase locked loop circuit is locked by comparing the phase detection signals outputted from the phase detector in a digital manner. The method of claim 1, wherein the locking detection unit, A comparison unit comparing the phase detection signals output from the phase detector; And And a locking unit detecting whether the phase locked loop circuit is locked according to the comparison result. The method of claim 2, wherein the comparison unit, A first flip-flop that outputs a first comparison signal corresponding to the first phase detection signal using the second phase detection signal as a clock; And A second flip-flop that outputs a second comparison signal corresponding to the second phase detection signal by using the first phase detection signal as a clock; And when the phase detection signals are used as clocks, the phase detection signals used as clocks are inputted to corresponding flip-flops after a predetermined time delay. 4. The PLL circuit of claim 3, wherein at least one of the flip-flops is a D flip-flop. The method of claim 3, wherein the locking unit, And an AND gate receiving the comparison signals output from the flip-flops to detect whether the phase locked loop circuit is locked. The method of claim 1, wherein the locking detection unit, A comparison unit comparing the phase detection signals output from the phase detector to output a first comparison signal and a second comparison signal; A counting unit counting the comparison signals output from the comparing unit and outputting counting signals; And And a locking unit detecting whether the phase locked loop circuit is locked according to counting signals output from the counting unit. The method of claim 6, wherein the comparison unit, A first flip-flop that outputs a first comparison signal corresponding to the first phase detection signal using the second phase detection signal as a clock; And A second flip-flop that outputs a second comparison signal corresponding to the second phase detection signal by using the first phase detection signal as a clock; And when the phase detection signals are used as clocks, the phase detection signals used as clocks are inputted to corresponding flip-flops after a predetermined time delay. 8. The phase locked loop circuit of claim 7 wherein at least one of the flip-flops is a D flip-flop. The method of claim 7, wherein the counting unit, A first sub counting unit counting a first comparison signal output from the first flip-flop; And And a second sub counting unit counting a second comparison signal output from the second flip-flop. 10. The method of claim 9, wherein at least one of the sub counting units, At least one third flip-flop connected to one of the first flip-flop and the second flip-flop to count one of the first comparison signal and the second comparison signal, And the third flip-flop uses the first frequency signal as a clock. 11. The phase locked loop circuit of claim 10 wherein at least one of the third flip-flops is a D flip-flop. The method of claim 9, wherein the locking unit, A first AND gate connected to the first sub counting unit; A second AND gate connected to the second sub counting unit; And And a third AND gate receiving the output of the first AND gate and the output of the second AND gate, and detecting whether the phase locked loop circuit is locked according to the outputs of the AND gates. Fixed loop circuit. Comparing the phases of the first frequency signal and the second frequency signal to output a first phase detection signal having a first pulse width and a second phase detection signal having a second pulse width; And Comparing the output phase detection signals to detect whether the frequency signals are locked by phase, and outputting an output signal having information on the detection result; And the logic of the output signal when the pulse widths are the same is different from the logic of the output signal when the pulse widths are different. The method of claim 13, wherein the outputting of the output signal comprises: Outputting a first comparison signal corresponding to the second phase detection signal by using the first phase detection signal as a clock; And Outputting a second comparison signal corresponding to the first phase detection signal by using the second phase detection signal as a clock; And logic of the output signal is generated by combining logic of the comparison signals. The method of claim 13, wherein the outputting of the output signal comprises: Outputting a first comparison signal corresponding to the second phase detection signal by using the first phase detection signal as a clock; Counting the output first comparison signal to output a first counting signal; Outputting a second comparison signal corresponding to the first phase detection signal by using the second phase detection signal as a clock; And Counting the output second comparison signal to output a second counting signal; The logic of the output signal is generated by combining logics of the counting signals.
KR1020070017162A 2007-02-20 2007-02-20 Method of detecting locking of a phase and phase locked loop circuit for performing the same KR20080077515A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100987072B1 (en) * 2010-01-27 2010-10-11 삼성탈레스 주식회사 Apparatus and method for improving phase noise of phase locked loop
KR101007391B1 (en) * 2009-06-15 2011-01-13 삼성탈레스 주식회사 Apparatus and method for improving phase noise of phase locked loop
US10031169B2 (en) 2015-01-22 2018-07-24 Samsung Electronics Co., Ltd Apparatus and method for detecting phase lock in an electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101007391B1 (en) * 2009-06-15 2011-01-13 삼성탈레스 주식회사 Apparatus and method for improving phase noise of phase locked loop
KR100987072B1 (en) * 2010-01-27 2010-10-11 삼성탈레스 주식회사 Apparatus and method for improving phase noise of phase locked loop
US10031169B2 (en) 2015-01-22 2018-07-24 Samsung Electronics Co., Ltd Apparatus and method for detecting phase lock in an electronic device

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