JP2009237882A - Input signal filter processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an input signal filter processing method for performing the filter processing of an input signal without generating any error regardless of the entry of edge pulse in view of such situations that malfunction may occur when a noise is applied to an input terminal in a timing synchronizing with a sampling cycle. <P>SOLUTION: The input signal filtering processing method for performing the sampling of an input signal in a prescribed sampling cycle T includes: a step of detecting an edge pulse PE in the middle of a sampling period; a routine for, when the edge pulse is not detected, copying a backup value BU to a status ST, and for holding the next sampling value SG as the backup value BU; and a routine for, when the edge pulse is detected, skipping the copy of the backup value BU to the status ST, and for holding the next sampling value SG as a backup value BU. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an input signal filtering method for sampling an input signal at a predetermined sampling period, and relates to a technique for correctly filtering an input signal while suppressing the influence of disturbance noise and the like.

  As a factory automation (FA) control device installed in a production factory or the like, a programmable controller (PC) that is a controller that can freely replace a logic circuit is used. This programmable controller is composed of a plurality of modules. As the plurality of modules, there are a power supply module, a CPU module, an input module, an output module, a communication module, and the like. The CPU module includes a CPU, an I / O memory, a program memory, and the like (see, for example, Patent Document 1). An input device such as a sensor is connected to the input module, and an external device such as an actuator is connected to the output module. The input module and the output module are linked by the CPU module. An input device such as a sensor senses the state of the object to be controlled, inputs the information to the input module, performs a calculation in the CPU module, and outputs to the output module based on the calculation result. Drives and controls external equipment.

  In the above-described programmable controller, the input module inputs an ON / OFF signal to the CPU module using a switch, a sensor, or the like as an external contact. In the output module, the internal contact is turned on / off in response to the control signal of the CPU module to supply / shut off the power to / from an external device such as an actuator to drive the external device on / off. Input signals such as ON / OFF signals for such contacts need to be stabilized by filtering so as not to be affected by noise due to the input / output module arrangement environment in the control operation of the programmable controller.

  FIG. 5 shows an outline of the input module. 1 is an input module, 2 is an input circuit, 3 is an input filter circuit, 4 is a signal input terminal, 5 is a power input terminal, 6 is a sensor, 7 is a power supply, and 8 is a CPU module. An input signal Sin from the sensor 6 is taken into the input filter circuit 3 of the input circuit 2 from the signal input terminal 3. The input filter circuit 3 takes the “H” and “L” changes of the input signal Sin changing to “H” and “L” into the inside as faithfully as possible, shapes the waveform, and passes it to the CPU module 8.

  The input filter circuit 3 samples and filters the input signal Sin at a constant sampling period T. In the prior art, sampling is performed only at the sample timing for each sampling period T. FIG. 6 is a flowchart showing the operation.

  In step n1, it is determined whether the sampling value SG matches the backup value BU. If they match, step n2 is skipped and the sampling value SG is backed up at step n3 (backup value BU ← sampling value SG).

  If it is determined in step n1 that they do not match, the process proceeds to step n2, the sampling value SG is copied to the status ST (filter output), and the sampling value SG is further backed up in step n3 (backup value BU ← sampling value SG). ).

  First, an operation when an edge pulse caused by noise or the like does not enter the input signal will be described with reference to FIG. Downward arrows t1 to t9 are sample timings. In FIG. 7, parallel lines are equal, meaning that the sampling value SG is equal to the backup value BU. Further, the crossing of the diagonal lines with the parallel lines is not equal, which means that the sampling value SG does not match the backup value BU.

  At the sample timing t1, the sampling value SG of the input signal is “L” (low level). Until this time, the backup value BU is “L”. Accordingly, since the determination at step n1 is the sampling value SG = the backup value BU, step n2 for copying the backup value BU to the status ST is skipped, and the process proceeds to step n3 to back up the sampling value SG = “L” ( Backup value BU ← “L”). The status ST at this time is “L” from the history up to now (status ST = “L”).

  At the next sample timing t2, since the sampling value SG is “L” and the backup value BU is “L”, the operation is the same as that at the sample timing t1. That is, in step n1, the sampling value SG = the backup value BU, step n2 is skipped, and in step n3, the sampling value SG = “L” is backed up (backup value BU ← “L”).

  The same operation is performed at the next sample timing t3 and further at the next sample timing t4 (backup value BU ← “L”).

  At the next sample timing t5, the sampling value SG is “H” (high level). Until this time, the backup value BU is “L”. Accordingly, since the determination at step n1 is that the sampling value SG is not equal to the backup value BU, the process proceeds to step n2 where the sampling value SG = “H” is copied to the status ST (status ST ← “H”; status ST change) ). In step n3, the sampling value SG = "H" is backed up (backup value BU ← "H"). As a result, the filter output (status ST) is inverted to “H”.

  At the next sample timing t6, since the sampling value SG = “H” and the backup value BU is “H”, step n2 is skipped and the sampling value SG = “H” is backed up at step n3 (backup value). BU ← “H”).

  The same operation is performed at the next sample timing t7 (backup value BU ← “H”).

  At the next sample timing t8, the sampling value SG is “L”, the backup value BU is “H”, and the judgment at step n1 is a mismatch between the sampling value SG ≠ the backup value BU. SG = “L” is copied to status ST (status ST ← “L”; change in status ST). In step n3, the sampling value SG = “L” is backed up (backup value BU ← “L”). As a result, the filter output (status ST) is inverted to “L”.

  As described above, the change in the input signal “L” / “H” is correctly reflected in the filter output (status ST).

For example, Patent Document 2 has been proposed as a technique for filtering an input signal.
Japanese Patent Laying-Open No. 2005-259079 JP 2007-156847 A

  However, in the case of the prior art that performs processing according to the flowchart of FIG. 6, if an edge pulse due to noise or the like enters the input signal, an error may occur in the filter output. This will be described with reference to FIG.

  At the sample timing t1, the sampling value SG of the input signal is “L”. Until this time, the backup value BU is “L”. The judgment at step n1 is sampling value SG = backup value BU, step n2 is skipped, and sampling value SG = “L” is backed up at step n3 (backup value BU ← “L”). The status ST at this time is “L” from the history up to now (status ST = “L”).

  The edge pulse PE1 enters before the next sample timing t2. However, in the case of this prior art, sampling is performed only at the sample timings t1, t2, t3, t4... At every constant sampling period T, and thus the edge pulse PE1 itself is not sampled during this sampling period. Since there is no sampling, there is no direct effect.

  At the next sample timing t2, since the sampling value SG is “L” and the backup value BU is “L”, the operation is the same as that at the sample timing t1. That is, sampling value SG = backup value BU in step n1, step n2 is skipped, and sampling value SG = “L” is backed up in step n3 (backup value BU ← “L”).

  At the next sample timing t3, the edge pulse PE2 enters at exactly the same time. Therefore, the edge pulse PE2 is sampled. The sampling value SG = “H”. Until this time, the backup value BU is “L”. Accordingly, since the determination at step n1 is that the sampling value SG is not equal to the backup value BU, the process proceeds to step n2 where the sampling value SG = “H” is copied to the status ST (status ST ← “H”; status ST change) ). In step n3, the sampling value SG = "H" is backed up (backup value BU ← "H"). As a result, the filter output (status ST) is inverted to “H”. This inversion is a malfunction.

  The edge pulse PE3 enters before the next sample timing t4. However, this is not sampled.

  At the next sample timing t4, the edge pulse PE4 enters at exactly the same time. Therefore, the edge pulse PE4 is sampled. The sampling value SG = “H”. Until this time, the backup value BU is “H”. Therefore, since the sampling value SG is equal to the backup value BU, step n2 is skipped, and in step n3, the sampling value SG = "H" is backed up (backup value BU ← "H").

  The input signal is originally “L” from the sample timing t1 to immediately before the sample timing t5. Nevertheless, the filter output (status ST) is inverted to “H” from the sample timing t3 and is different from the input signal. That is, a malfunction occurs.

  Next, as another aspect, at the sampling timing t11, the sampling value SG of the input signal is “H”. Until this time, the backup value BU is “H”. The judgment at step n1 is sampling value SG = backup value BU, step n2 is skipped, and sampling value SG = “H” is backed up at step n3 (backup value BU ← “H”). The status ST at this time is “H” from the history up to now (status ST = “H”).

  At the next sample timing t12, the edge pulse PE5 enters at exactly the same time. Therefore, the edge pulse PE5 is sampled. The sampling value SG = “L”. Until this time, the backup value BU is “H”. Accordingly, the determination at step n1 is that the sampling value SG is not equal to the backup value BU, so the process proceeds to step n2 where the sampling value SG = “L” is copied to the status ST (status ST ← “L”; status ST change) ). In step n3, the sampling value SG = “L” is backed up (backup value BU ← “L”). As a result, the filter output (status ST) is inverted to “L”. This inversion is a malfunction.

  The edge pulse PE6 enters before the next sample timing t13. However, this is not sampled.

  At the next sample timing t13, the edge pulse PE7 enters at exactly the same time. Therefore, the edge pulse PE7 is sampled. The sampling value SG = “L”. Until this time, the backup value BU is “L”. Therefore, since the sampling value SG is equal to the backup value BU, step n2 is skipped, and in step n3, the sampling value SG = “L” is backed up (backup value BU ← “L”).

  The input signal is originally “H” from the sample timing t11 to immediately after the sample timing t14. Nevertheless, the filter output (status ST) is inverted to “L” from the sample timing t12, and is different from the input signal. That is, a malfunction occurs.

  As described above, in the prior art, when noise is applied to the input terminal at a timing synchronized with the sampling period, a malfunction may occur.

  The present invention has been created in view of such circumstances, and an object thereof is to provide an input signal filtering method capable of accurately filtering an input signal without error regardless of the intrusion of an edge pulse.

An input signal filter processing method according to the present invention is an input signal filter processing method for sampling an input signal at a predetermined sampling period,
Detecting an edge pulse during the sampling period;
When an edge pulse is not detected, a routine for copying the backup value at that time to the status and holding the next sampling value as a backup value;
When an edge pulse is detected, a routine for skipping copying of the backup value to the status and holding the next sampling value as a backup value is provided.

  In the above configuration, the routine when the edge pulse is detected is to clear the edge information flag, enable the input edge interrupt, set the edge information flag in the input edge interrupt processing, and then disable the input edge interrupt. There are aspects.

  In the above configuration, in addition to sampling the input signal every sampling period, edge pulse detection in the middle of the sampling period is added to the filter condition. If an edge pulse is detected, the next sampling value in that sampling period is not reflected in the filter output (status), and in the sampling period in which no edge pulse is detected, the backup value is reflected in the filter output (status). Therefore, the input noise synchronized with the sampling period that cannot be filtered by the prior art can be effectively removed from the filter output (status), and the input signal can be accurately filtered without error.

  In addition, because the input edge interrupt is prohibited, the edge pulse detection and the input edge interrupt processing are accepted only once within the sampling period. Therefore, even when a plurality of input signals having a small period are input to the input terminal, the load on the CPU is reduced. Little increase.

  According to the present invention, even when noise synchronized with the sampling period is applied, it is possible to perform a filtering process so that an input signal can be determined stably and early without causing a malfunction.

  Embodiments of an input signal filtering method according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 shows a hardware configuration. This hardware can be built in a programmable controller or the like, and is composed of, for example, a CPU, ROM, RAM, etc., a microcomputer including an interface, etc., and functionally a sampling circuit 10, a backup value memory 20, And an arithmetic processing unit 30. The sampling circuit 10 has a function of monitoring edge pulses at a cycle shorter than the sampling cycle T in addition to sampling at a predetermined sampling cycle T. The backup value BU backed up by the sampling value SG is stored in the backup value memory 20. The arithmetic processing unit 30 executes the input signal filter processing method of the present embodiment in cooperation with the sampling circuit 10 and the backup value memory 20.

  FIG. 2 is a flowchart showing a processing procedure of the input signal filter processing method according to the embodiment of the present invention. FIG. 2A is a flowchart showing a main routine, and FIG. 2B is a flowchart showing an input edge interrupt routine.

  In step S1, it is determined whether an edge pulse is detected during the sampling period. If no edge pulse is detected, the process proceeds to step S2. If an edge pulse is detected, the process proceeds to step S3.

  If no edge pulse is detected and the process proceeds to step S2, the current backup value BU is copied to the status ST (status ST ← backup value BU). Next, in step S4, the sampling value SG is backed up (backup value BU ← sampling value SG).

  On the other hand, when the edge pulse is detected and the process proceeds to step S3, the previous edge information flag Fe is cleared to zero (Fe ← 0). In this case, the previous edge information flag Fe may be “0” or “1”, but it is cleared to zero anyway. In step S3, an input edge interrupt is further permitted.

  The input edge interrupt routine is shown in FIG. When the process proceeds to this input edge interrupt, the edge information flag Fe is set to “1” (Fe ← 1). This means that the abnormal state in which the edge pulse is detected during the sampling period is held. Next, the input edge interrupt is prohibited. That is, once edge pulse detection is performed in the middle of the sampling period, the input edge interrupt is not performed in the middle of the sampling period thereafter, thereby reducing the load on the CPU. Then, the process returns to the main routine.

  It is random how many edge pulses are generated during the sampling period by the input edge interrupt processing, but when the first one edge pulse is detected, the second and subsequent edge pulses are not detected.

  When returning to the main routine, the sampling value SG at the next sampling timing is backed up as correct, and the backup value BU ← sampling value SG is set. In this edge pulse detection route (S1 → S3 → S4), the step of copying the backup value BU to the status ST is skipped. This corresponds to the treatment that the data value based on edge pulse detection during the sampling period is invalid.

  As described above, if the edge pulse is not detected in the middle of the sampling period, the sampling value SG is confirmed. Therefore, the current backup value BU is copied to the status ST and output to the display unit as a filter output. Then, the sampling value SG at the next sampling timing is backed up as correct, and the backup value BU ← sampling value SG is set.

  Next, a specific example will be described.

  First, an operation when an edge pulse caused by noise or the like does not enter the input signal will be described with reference to FIG.

  There is no edge pulse detection from sample timing t1 to sample timing t2 (NO in step S1). The backup value BU = “L” is copied to the status ST (step S2). As a result, the status ST = “L”. The sampling value SG at the sample timing t2 at this time is “L”, and the sampling value SG is backed up (step S4). Thus, the backup value BU = sampling value SG = “L”.

  Next, since there is no edge pulse detection from the sample timing t2 to the sample timing t3, the backup value BU = “L” is copied to the status ST (status ST = “L”). Further, the sampling value SG of “L” is backed up (backup value BU = “L”).

  Next, since no edge pulse is detected from sample timing t3 to sample timing t4, the backup value BU = “L” is copied to status ST (status ST = “L”). Further, the sampling value SG of “L” is backed up (backup value BU = “L”).

  Next, a rising edge pulse is detected from sample timing t4 to sample timing t5 (YES in step S1). The edge information flag Fe is cleared and the input edge interrupt is permitted (step S3). When the process proceeds to the input edge interrupt, the edge information flag Fe is set (Fe ← 1), and the input edge interrupt is prohibited (step S11). The sampling value SG = “H” at the next sampling timing t5 is backed up as correct, and the backup value BU ← “H” is set. In this edge pulse detection, the step of copying the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection in the middle of the sampling period is invalidated. The original “L” is maintained as the status ST.

  There is no edge pulse detection from sample timing t5 to sample timing t6 (NO in step S1). The backup value BU = “H” is copied to the status ST (step S2). As a result, the status ST = “H”. The sampling value SG at this time is “H”, and the sampling value SG is backed up (step S4). Thus, the backup value BU = sampling value SG = “H”.

  Next, since no edge pulse is detected from sample timing t6 to sample timing t7, the backup value BU = "H" is copied to status ST (status ST = "H"). Further, the sampling value SG of “H” is backed up (backup value BU = “H”).

  Next, a falling edge pulse is detected from sample timing t7 to sample timing t8 (YES in step S1). The edge information flag Fe is cleared and the input edge interrupt is permitted (step S3). When the process proceeds to the input edge interrupt, the edge information flag Fe is set (Fe ← 1), and the input edge interrupt is prohibited (step S11). The sampling value SG = “L” at the next sampling timing t8 is backed up as correct, and the backup value BU ← “L” is set. In this edge pulse detection, the step of copying the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection in the middle of the sampling period is invalidated. The original “H” is maintained as the status ST.

  As described above, the change of “L” / “H” of the input signal is correctly reflected in the filter output (status ST).

  Next, the operation when an edge pulse caused by noise or the like enters the input signal will be described with reference to FIG.

  The edge pulse PE1 is detected from the sample timing t1 to the sample timing t2 (YES in step S1). The edge information flag Fe is cleared and the input edge interrupt is permitted (step S3). When the process proceeds to the input edge interrupt, the edge information flag Fe is set (Fe ← 1), and the input edge interrupt is prohibited (step S11). The sampling value SG = “L” at the next sampling timing t2 is backed up as correct, and the backup value BU ← “L” is set. In this edge pulse detection, the step of copying the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection in the middle of the sampling period is invalidated. The original “L” is maintained as the status ST.

  Next, from the sample timing t2 to the sample timing t3, the edge pulse PE2 is detected, the same input edge interrupt processing as described above is performed, the sampling value SG = "H" at the next sampling timing t3 is backed up, and the backup value BU ← Set to “H”. The copy of the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection is invalid. The original “L” is maintained as the status ST.

  Next, the edge pulse PE3 is detected from the sample timing t3 to the sample timing t4, and the same input edge interrupt processing as described above is performed. The next edge pulse PE4 is not subject to detection because the interrupt is prohibited. The sampling value SG = “H” at the next sampling timing t4 is backed up, and the backup value BU ← “H” is set. The copy of the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection is invalid. The original “L” is maintained as the status ST.

  Next, there is a rising edge pulse detection from sample timing t4 to sample timing t5. Input edge interrupt processing similar to that described above is performed. The sampling value SG = “H” at the next sampling timing t5 is backed up, and the backup value BU ← “H” is set. The copy of the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection is invalid. The original “L” is maintained as the status ST.

  Next, since there is no edge pulse detection from the sample timing t5 to the sample timing t6, the original “L” is maintained as the backup status ST. The value BU = “H” is copied to the status ST (status ST = “H”; change in status ST). Then, the sampling value SG = “H” is backed up (backup value BU = “H”). In this process, the filter output (status ST) is inverted from “L” to “H”.

  Next, from the sample timing t6 to the sample timing t7, the edge pulse PE5 is detected, the input edge interrupt process similar to the above is performed, the sampling value SG = “L” at the next sampling timing t7 is backed up, and the backup value BU ← Set to “L”. The copy of the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection is invalid. The original “H” is maintained as the status ST.

  Next, the edge pulse PE6 is detected from the sample timing t7 to the sample timing t8, and the same input edge interrupt processing as described above is performed. The next edge pulse PE7 is not subject to detection because the interrupt is prohibited. The sampling value SG = “L” at the next sampling timing t8 is backed up, and the backup value BU ← “L” is set. The copy of the backup value BU to the status ST is skipped, and the data value based on the edge pulse detection is invalid. The original “H” is maintained as the status ST.

  As described above, the change of “L” / “H” of the input signal is correctly reflected in the filter output (status ST).

  The input signal is originally “L” from the sample timing t1 to immediately before the sample timing t5. However, edge pulses PE1 to PE4 have entered. The filter output (status ST) maintains “L” from the sample timing t1 to the sample timing t6, and the edge pulses PE1 to PE4 that have entered the input signal are neglected. That is, malfunction caused by the edge pulse is prevented. Also for the original “H” input signal from the sample timing t5 to the sample timing t9, the corresponding filter output (status) maintains “H” after the sample timing t6, and the edge pulses PE5 to PE7 that have entered the input signal are It has been neglected. That is, malfunction caused by the edge pulse is prevented.

  The input signal filter processing method of the present invention is a filter processing technique for stably and quickly determining an input signal without causing a malfunction even when noise synchronized with a sampling period is applied, particularly in an input module of a programmable controller. Useful.

1 is a schematic configuration diagram showing a hardware configuration for implementing an input signal filtering method according to an embodiment of the present invention. The flowchart which shows the procedure of the process of the input signal filter processing method in embodiment of this invention In the input signal filter processing method according to the embodiment of the present invention, a timing chart showing an operation when an edge pulse caused by noise or the like does not enter the input signal In the input signal filter processing method according to the embodiment of the present invention, a timing chart showing an operation when an edge pulse due to noise or the like enters an input signal Schematic configuration diagram of an input module of a programmable controller in the prior art The flowchart which shows the procedure of the process of the input signal filter processing method in a prior art Timing chart showing the operation when the edge pulse due to noise or the like does not enter the input signal in the conventional input signal filtering method Timing chart showing the operation when an edge pulse due to noise or the like enters the input signal in the conventional input signal filtering method

Explanation of symbols

10 Sampling circuit 1
20 Backup value memory 30 Processing unit PE1 to PE7 Edge pulse

Claims (2)

An input signal filter processing method for sampling an input signal at a predetermined sampling period,
Detecting an edge pulse during the sampling period;
When an edge pulse is not detected, a routine for copying the backup value at that time to the status and holding the next sampling value as a backup value;
And a routine for holding the next sampling value as a backup value after skipping copying of the backup value to the status when an edge pulse is detected.   The routine when the edge pulse is detected clears an edge information flag, enables an input edge interrupt, sets an edge information flag in an input edge interrupt process, and then disables an input edge interrupt. Input signal filtering method.

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