KR101192902B1 - Method and apparatus for detecting a clock signal in mobile communication system - Google Patents

Abstract

The present invention relates to a method and an apparatus for checking the presence or absence of a reference clock used for an internal block in a mobile communication system.

To this end, the mobile terminal inputs a clock signal supplied to the functional block and a signal twice as fast as the clock signal as a reference clock signal to output a signal indicating whether the clock is operating. The glitch remover removes and outputs a glitch signal among the output signals of the signal detector.

CDMA, UMTS, Clock Signals, Function Blocks, Logical Operators

Description

METHOD AND APPARATUS FOR DETECTING A CLOCK SIGNAL IN MOBILE COMMUNICATION SYSTEM}

1 is a block diagram illustrating a clock detector in a modem of a mobile terminal according to an exemplary embodiment of the present invention.

2 is a view illustrating in detail the signal detector of FIG.

3 is a view illustrating in detail the glitch removing unit of FIG.

4A is a timing diagram illustrating a case where a normal clock signal is introduced into the signal detector and the glitch remover of FIG. 1.

4B is an enlarged timing diagram of the S1 signal of FIG. 4A.

FIG. 5 is a timing diagram illustrating a case where an abnormal clock signal is supplied from the signal detector and the glitch remover of FIG. 1. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for detecting synchronization in a mobile communication system, and more particularly, to a method and apparatus for checking an abnormality of a reference clock used for an internal block in a mobile communication system.

In general, a clock system uses a clock to process data. For example, in a code division multiple access (CDMA) system, a modem includes a plurality of functional blocks such as modulation / demodulation, decoding, and interleaving. The modem supplies a clock signal introduced to each functional block for each functional block by using a mux in the form of an on / off switch.

In detail, the mobile terminal is divided into the sleep mode and the like in addition to the operation mode in order to minimize current consumption in order to control the clock signal supplied to each functional block. For example, when the mobile station from the base station is in the sleep mode (sleep mode), only the RF receiver operates so that the clock signal is not supplied to the functional blocks such as the decoder and the interleaver.

As such, since the CDMA modem turns on / off the clock signal when necessary, software control (S / W control) due to a malfunction occurs because the CDMA modem does not overcome the fine clock on / off timing difference. There is a problem that often occurs.

To check whether the clock signal is supplied to the internal functional blocks in the CDMA modem, the software sets the on / off by writing a certain value to the register and extracts it to the hardware external pin. This causes a problem of using external equipment such as an oscilloscope.

Accordingly, an object of the present invention is to provide an apparatus and method for detecting an internal clock signal supplied for each functional block in a mobile terminal of a mobile communication system.

Another object of the present invention is to provide a method and apparatus for coping with an error in an internal clock signal in real time in a mobile terminal of a mobile communication system.

According to an aspect of the present invention, there is provided an apparatus for detecting an internal clock signal supplied for each functional block from a mobile terminal to a mobile communication system, the clock signal being supplied to the functional block and a signal twice as fast as the clock signal. And a glitch removal unit for inputting a reference clock signal and outputting a signal indicating whether a clock is operating, and a glitch removal unit for removing a glitch signal among the output signals.

The apparatus may further include means for inputting an enable signal informing whether the signal detector and the glitch remover operate.

 The signal detection unit performs a beta logical operation on at least two means for storing the clock signal and the reference clock signal, a signal output from one of the at least two means, and a signal output from the other means. It is characterized by including the logical operator to perform.

The glitch canceling unit is a beta for at least two means for storing the output signal and the reference clock signal of the signal detector, a signal output from one of the at least two means and a signal output from the other means. It is characterized by including a logic element for performing a logic operation.

At least two means for storing the clock signal and the reference clock signal, and at least two means for storing the output signal of the signal detector and the reference clock signal are flip-flops.

The clock signal is characterized in that 9.8304 MHz.

According to an aspect of the present invention, there is provided a method of detecting a clock signal supplied to an internal block of a mobile terminal in a mobile communication system, wherein a clock signal supplied to the functional block and a signal twice as fast as the clock signal are referenced. And a second step of outputting a signal indicating whether the clock is operated by inputting a clock signal and a second step of removing and outputting a glitch signal among the output signals.

The method may further include inputting an enable signal informing whether the operation according to the first process and the second process is performed.

The first process includes storing the clock signal and the reference clock signal using at least two storage means, a signal output from one of the at least two means, and a signal output from the other means. It includes a process of performing a beta logical operation for.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that the same components in the drawings represent the same numerals wherever possible. Specific details are set forth in the following description, which is provided to aid a more general understanding of the invention. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The present invention provides an apparatus and method for checking in real time a clock signal supplied for each internal functional block in a mobile terminal of a mobile communication system. To this end, first, a modem of a mobile terminal according to an exemplary embodiment of the present invention will be described, and then a clock detection method according to the timing diagram will be described. In the present invention, the mobile communication system may represent CDMA, UMTS, and satellite communication, and the following description will focus on CDMA for convenience of description. However, it should be noted that the present invention can be applied to UMTS, satellite communication, and the like.

1 is a block diagram illustrating a clock detector 100 in a modem of a mobile terminal according to an exemplary embodiment of the present invention. In FIG. 1, F denotes a clock signal supplied to each functional block, and 2XF is a reference clock signal for detecting the F clock signal as a clock signal twice as fast as the F signal. The monitor enable (ME) is an enable signal for detecting the operation of the F clock signal.

Referring to FIG. 1, a clock detector includes a signal detect unit 110 and a glitch cancel unit 120. The signal detection unit 110 receives an F signal, an En, a 2XF signal. The signal detector 110 detects whether the clock of the F signal is supplied or not, and detects the 2XF signal as a reference clock. Here, F denotes a clock signal used in a CDMA system, respectively, as ChipX8 (9.8304 MHz), and 2XF denotes a ChipX16 clock signal that is twice as fast as the ChipX8. The two clock signals are reference clock signals introduced into each functional block in the modem, and the two clock signals are locked by a predetermined phase difference θ.

When the signal detection unit 110 detects whether the F signal is clocked by the enable signal En, the signal detection unit 110 detects the S1 signal indicating whether the clock of the F signal is operated using the reference clock 2XF signal. do. Here, the S1 signal generates a glitch signal such as a timing delay time between the two signals and a propagation delay time due to the logic elements in the signal detector 110.

The glitch remover 120 has an output signal S1 of the signal detector 110, the enable signal En, and a reference clock signal 2XF as an input signal. The glitch remover 120 deletes the glitch signal from the output signal S1 of the signal detector 110 to output the S2 signal. The reason for the deletion of the glitch signal is that a false determination can be made as to whether the F signal is supplied and normal. The S2 signal records the result of the normality in a predetermined register. In the present invention, the normal operation is represented by a low level, and in the case of a malfunction will be represented by a high level.

Here, the enable signal En inputted to the signal detector 110 and the glitch remover 120 is an optional item that varies depending on the system.

Next, the process of outputting the S1 signal by using the signal detector 110 will be described with reference to FIGS. 2 to 4A.

FIG. 2 is a detailed view of the signal detector 110 of FIG. 1, and FIG. 4A is a timing diagram illustrating signals output from the signal detector 110 and the glitch remover 120 when a normal clock signal is introduced. Indicates.

Referring to FIG. 2, the signal detection unit 110 includes two D flip flops 211 and 213 and a NON-EX-OR 215. The first flip-flop 211 and the second flip-flop 213 turn on the enable signal En from a controller (not shown) to detect a clock signal of the ChipX8 signal. The first flip-flop 211 outputs a? Signal using the twice faster ChipX16 signal as a reference clock to the input ChipX8 signal. The two clock signals are basically input with a fixed timing delay θ. Where θ = t2-t1.

The ① signal is shown in Figure 4a. The ① signal is a signal that the ChipX8 signal is output at the rising edge of the reference clock signal ChipX16, and outputs a signal shifted by the ChipX8 signal by θ. The ① signal is input to the second flip-flop 213 to output the ② signal by the reference clock signal ChipX16.

As shown in FIG. 4A, the signal ② is shifted by θ, and the signal ① is delayed by one clock by the ChipX16, thereby detecting a signal inverted from the signal ①.

동안 동일 레벨을 가지므로 글로치 신호가 발생하게 된다.The NON-EX-OR 215 is a logic gate that outputs the S1 signal by inputting the ① and ② signals. The S1 signal is shown in Figure 4a. The NON-EX-OR 215 becomes a low level when the levels of the two input signals are different, and becomes a high level when they are the same. Accordingly, referring to the S1 signal, the predetermined time is determined by the delay time between the ① and ② signals between the flip-flop and the timing delay between the logic gates.

Since they have the same level, a gloss signal is generated.

The glitches occur for a very small amount of time, but there are cases where the glitches can make error determinations during system operation. A detailed reason for this will be described with reference to FIG. 4B.

4B is an enlarged timing diagram of the S1 signal of FIG. 4A.

Referring to FIG. 4B, tg 401 and tb 403 indicate timings at which a central processing unit (CPU) reads data. Most systems use the clock and asynchronous control signals used by each function block to read data. That is, the data can be read at the time tg 401 or at the time tb 403. It is not a problem if the data is read at the time tg 401, but if the data is read at the rising edge of the flip-flop if the data is read at the tb time 403, even if a normal clock signal flows in, the logic level Becomes "1" and is recognized by the software (S / W) as an error message. Therefore, in order to prevent this, the glitch removing unit 120 should be provided.

Next, the configuration and operation method of the glitch removing unit 120 will be described.

3 is a view illustrating in detail the glitch removing unit 120 of FIG. 1.

Referring to FIG. 3, the glitch removing unit 120 includes two flip-flops 311 and 313 and an AND gate 315. The two flip-flops are composed of a first flip-flop 311 and a second flip-flop 313.

The first flip-flop 311 receives the signal S1 signal output from the signal detector 110 and uses ChipX16 as a reference clock signal. Also, the second flip-flop 313 also inputs the signal ③ to output the signal ④. The signals 3 and 4 are shown in FIG. 4A. Next, the signals 3 and 4 will be described with reference to FIG. 4A.

구간이 항상 chipx16 클럭 신호의 라이징 에지(Rising Edge) 뒤에 존재 한다. 따라서 도 4a에서 나타나듯이 정상적인 Clock이 유입되는 경우에도 발생하는 글리치 신호는 상기 ts 시점에서 데이터를 래치(Latch)하게 되므로 ③ 출력에서 알 수 있듯이 글리치 신호가 제거 된다. 이로서 S2는 논리 레벌 '0'을 유지하고 이는 정상상태임을 나타낸다.Referring to FIG. 4A, first, the 3 signal is an output signal from which the first flip-flop 311 receives the S1 signal and the reference clock signal 2XF. In FIG. 4A

The interval is always behind the rising edge of the chipx16 clock signal. Therefore, as shown in FIG. 4A, the glitch signal generated even when a normal clock flows in latches data at the time ts. Thus, the glitch signal is removed as can be seen from the output. This maintains a logical level of '0', indicating that S2 is steady.

The second flip-flop 313 receives the signal ③ and outputs the signal ④ using ChipX16 as a reference clock signal. As shown in Fig. 4a, the signal? Is delayed by one clock with Chipx16.

The AND gate 315 checks the output signal of the signal detector 110 twice in time by outputting the final signal S2 by inputting the signals ③ and ④. That is, by completely removing the glitches signal that may cause a malfunction of the system from the S1 signal, the final output signal S2 becomes a logic level '0' to store a message indicating that there is no error in a predetermined memory.

4A illustrates a case in which a clock signal is normally supplied to the functional blocks inside the modem.
Next, a case in which an abnormal clock signal is supplied to the functional blocks will be described.

FIG. 5 is a timing diagram illustrating a case in which an abnormal clock signal is supplied from the clock detector 100 according to the present invention. In the initial stage, an F signal is normally introduced, and at t6, an abnormal state in which the logic level is fixed to the clock signal is '1'. When the S2 signal, which is the final output, occurs from t7, the logic level of the fault message indicates a '1'.

Referring to FIG. 5, when an abnormal clock signal is introduced, the logic level '1' is maintained at the output of the ③ signal, which is clocked to Chipx16 once again, thus maintaining the logic level '1'. do. Thereafter, when the signals 3 and 4 are all passed through the AND gate 315, a fault message is set to 1 at time t7 of FIG.

The central processing unit (CPU) of the system latches data at an arbitrary time ts, that is, the rising edge of the chipx16 clock signal, so that signals generated in the subsequent blocks, i.e., internal signals ① and ② The generated S1 signal may encounter the rising edge of the reference clock signal Chipx16 in a state of logic 1.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the described embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

 As described above, the present invention provides a case in which a clock signal is turned on / off when the CDMA S / W is introduced into each block to minimize current consumption, such as a sleep mode, while the CDMA S / W is operating. The abnormal behavior that occurs can be detected in software in real time. Therefore, it is possible to take action at high speed in case of abnormal clock operation, which enables high efficiency software (S / W).

Claims (10)

An apparatus for checking in real time whether an internal clock signal supplied for each functional block by a mobile terminal of a mobile communication system is abnormal. A signal detector for inputting a clock signal supplied to the functional block and a signal twice as fast as the clock signal as a reference clock signal, and outputting a signal indicating whether a clock is operating; And a glitch remover configured to remove a glitch signal among the output signals. The method of claim 1, And means for inputting an enable signal informing whether the signal detector and the glitch remover are in operation. The method of claim 1, wherein the signal detection unit, At least two means for storing the clock signal and the reference clock signal; And a logical operator for performing a beta logical operation on a signal output from one of the at least two means and a signal output from the other means. The method of claim 1, wherein the glitch removing unit, At least two means for storing an output signal of the signal detector and the reference clock signal; And a logic element for performing a beta logic operation on a signal output from one of the at least two means and a signal output from the other means. 5. An inspection apparatus according to claim 3 or 4 wherein the means is a flip flop. The test apparatus of claim 1, wherein the clock signal is 9.8304 MHz. In the method for checking in real time whether the internal clock signal supplied for each functional block in the mobile terminal of the mobile communication system, A first process of inputting a clock signal supplied to the functional block and a signal twice as fast as the clock signal as a reference clock signal and outputting a signal indicating whether the clock is operating; And a second process of removing and outputting a glitch signal among the output signals. 8. The method of claim 7, And a step of inputting an enable signal informing whether the operation according to the first process and the second process is performed. The method of claim 7, wherein the first process, Storing the clock signal and the reference clock signal using at least two means; And performing a beta logical operation on a signal output from one of the at least two means and a signal output from the other means. 8. The method of claim 7, wherein the clock signal is 9.8304 MHz.

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