JP4962497B2 - Clock monitoring circuit, information processing apparatus, and clock monitoring method - Google Patents

Description

  The present invention relates to a clock monitoring circuit, an information processing apparatus, and a clock monitoring method for monitoring a clock of a device that operates in synchronization with a clock, and in particular, a clock monitoring circuit capable of monitoring a clock at high speed with less hardware, information The present invention relates to a processing device and a clock monitoring method.

  Conventionally, there is a mutual timeout monitoring as a method for monitoring whether or not the clock is operating normally. FIG. 6 is an explanatory diagram for explaining mutual timeout monitoring. As shown in the figure, in mutual timeout monitoring, one unit A activates the other unit B between units A and B operating at different clocks, and the unit B that has been activated is activated within a certain time. Report the response to unit A.

  Then, the unit A checks whether or not there is a response from the unit B after start-up transmission. If the response cannot be detected within a predetermined time, the unit A detects an error of the unit B as a timeout.

  Further, when the unit A detects an error of the unit B due to a timeout, for example, as shown in FIG. 7, the unit A performs a process of disconnecting the unit B in which the error has occurred and switching to the unit C that is an alternative unit. FIG. 7 shows a case where unit B and unit C are memories, and unit A and unit D share data on unit B or unit C.

  In addition to mutual timeout monitoring, the content of a specific FF is read using a JTAG scan of IEEE Standard 1149.1 (see, for example, Patent Document 1), and whether or not the data read by the scan matches an expected value. There is a method for detecting errors.

  As a technique related to the internal clock of the information processing apparatus, Patent Document 2 discloses a technique for detecting a data propagation area for the purpose of grasping a data propagation state between registers when the internal clock is stopped. ing.

Japanese Patent Laid-Open No. 10-143390 JP 62-115544 A

  In mutual timeout monitoring, unit B cannot accept a disconnection command from unit A in a state where the FF of the part B that accepts activation from unit A shown in FIG. 7 cannot operate normally due to a failure. . Here, unit A detects an error in unit B, so the data in unit B can not be used (or switched to another unit C), but unit D has a failure of unit B detected by unit A. A situation occurs in which the unit B is continuously used without knowing. Such a situation can be dealt with by duplicating the path / circuit for transmitting the disconnection command from the unit A to the units B and C, but there is a problem that the amount of hardware increases.

  For example, when JTAG defined in IEEE1149.1 is used, a circuit check is periodically performed by a program via an SVP (service processor). As a result, the OS may not be able to resolve the contradiction, and as a result, the system operation may not be continued.

  The present invention has been made to solve the above-described problems in the prior art, and provides a clock monitoring circuit, an information processing apparatus, and a clock monitoring method capable of monitoring a clock at a high speed with less hardware. For the purpose.

  In order to solve the above-described problems and achieve the object, a clock monitoring circuit according to the present invention includes a data output means for outputting data whose value is inverted by the input of a clock signal, and the data output by the data output means. When the data receiving means for receiving, the data change detecting means for detecting the change of the data received by the data receiving means, and the data received by the data change detecting means within a predetermined time do not change, It has an error detection means for detecting as an error.

  According to the present invention, when the data whose value is inverted by the input of the clock signal is output, the output data is received, the change of the received data is detected, and the received data does not change within a predetermined time. Since the detection is made as an error, the clock can be monitored with a simple mechanism.

  The data change detecting means of the clock monitoring circuit according to the present invention includes a data holding means for holding data by inputting a clock signal, and a logical operation for performing an exclusive OR operation between the input and output of the data holding means. It may be configured to have a means.

  According to the present invention, the data is held by the input of the clock signal, and the exclusive OR operation between the input and the output of the holding means is performed, so that the data change can be detected with a simple mechanism. .

  The information processing apparatus according to the present invention is an information processing apparatus having a first unit and a second unit, wherein the first unit receives data whose value is inverted by an input of a clock signal. Data output means for outputting to the unit, data receiving means for receiving the data output from the second unit by the data output means of the second unit, and changes in the data received by the data receiving means And a data change detecting means for detecting an error of the second unit when the received data does not change within a predetermined time by the data change detecting means. It is characterized by.

  According to the present invention, the first unit outputs data whose value is inverted by the input of the clock signal to the second unit, receives the data output from the second unit, and changes the received data. If the detected and received data does not change within a predetermined time, the clock is monitored with a simple mechanism because the second unit is detected as an error.

  The information processing apparatus according to the present invention is an information processing apparatus having a plurality of units, and one unit of the plurality of units receives data whose value is inverted by an input of a clock signal. The data output means for outputting to any one of the units and the data output means included in any one of the plurality of units receive data output from any of the plurality of units. Data receiving means, data change detecting means for detecting a change in data received by the data receiving means, and when the received data does not change within a predetermined time by the data change detecting means, And error detection means for detecting an error of the unit that outputs the received data.

  According to the present invention, one of the plurality of units outputs data whose value is inverted by the input of the clock signal to any one of the plurality of units, and any one of the plurality of units. The data output from the unit is received, the change of the received data is detected, and if the received data does not change within a predetermined time, the received data is detected as an error of the unit that output the data. Therefore, the clock can be monitored with a simple mechanism.

  The clock monitoring method according to the present invention is a clock monitoring method for monitoring a circuit that operates in synchronization with a clock signal, the step of outputting data whose value is inverted by the input of the clock signal, and the output Receiving the received data, detecting a change in the received data, and detecting the error if the received data does not change within a predetermined time. Features.

  According to the present invention, when the data whose value is inverted by the input of the clock signal is output, the output data is received, the change of the received data is detected, and the received data does not change within a predetermined time. Since the detection is made as an error, the clock can be monitored with a simple mechanism.

  According to the present invention, since the clock is monitored by a simple mechanism, there is an effect that the clock can be monitored at high speed with a small amount of hardware.

  According to the present invention, since a change in data for clock monitoring is detected with a simple mechanism, there is an effect that the clock can be monitored at high speed with less hardware.

  Exemplary embodiments of a clock monitoring circuit, an information processing apparatus, and a clock monitoring method according to the present invention will be explained below in detail with reference to the accompanying drawings.

  First, the clock monitoring mechanism according to the first embodiment will be described. FIG. 1 is an explanatory diagram for explaining the clock monitoring mechanism according to the first embodiment. As shown in the figure, in this clock monitoring mechanism, the unit W that operates with the clock to be monitored is divided into functional blocks or area blocks (X, Y, and Z in FIG. 1).

  Then, X inverts the data held in the clocked FF and sends it to Y at regular intervals. Similarly for Y, the data held in the FF is inverted at regular intervals and sent to Z. Similarly for Z, the data held in the FF is inverted at regular intervals and sent to X. X sends the inverted data to Y every certain time, and at the same time checks whether the data from Z changes within a certain time. If the data from Z does not change within a certain time, it is determined that there is an abnormality in the clock. The same applies to Y and Z.

  In this way, FF data that inverts every fixed time is transmitted in a loop between functional blocks or between area blocks, and it is checked whether the returned data changes within a fixed time. The clock can be monitored by hardware.

  Next, the configuration of the check circuit according to the first embodiment will be described. FIG. 2 is a block diagram illustrating the configuration of the check circuit according to the first embodiment. As shown in the figure, the check circuit 100 includes FFs 1 to 4, EORs 5 and 6, FF 10, and an error detection circuit 20.

  The FFs 1 to 4 are flip-flops (Flip-Flops) that are connected in series and operate as a clock, and are provided to synchronize a signal input to each block with a clock signal. The input of FF4 and the output of FF4 are respectively connected to two inputs of EOR5 that performs an exclusive OR operation for detecting a data change (edge trigger). When the data propagated to FF4 through 3 changes, the output of EOR5 that performs exclusive OR operation between the input of FF4 (output of FF3) and the output of FF4 becomes “1”, and the input 6a of EOR6 becomes “1” "become.

  Specifically, when the data held in FF4 is “0” and the data held in FF3 is “1”, “1” is input to EOR6 as a result of the exclusive OR operation by EOR5. By outputting to 6a, a change in data can be detected (edge trigger). In addition, when the clock signal is input, the data “1” held in FF3 propagates to FF4, and the data “0” held in FF2 propagates to FF3. As a result, “1” is output to the input 6 a of the EOR 6, so that a data change can be detected (edge trigger). Therefore, as long as the data held in the FF 4 for each clock signal continues to be inverted, the output of the EOR 5 becomes “1”.

  The FF 10 is a flip-flop that operates as a clock, and the data held for each clock is inverted and output by the EOR 6 that performs an exclusive OR operation. By connecting the output of EOR5 described above to one input 6a of EOR6 that performs exclusive OR operation and connecting the output of EOR6 to the input of FF10, when the other input 6b of EOR6 becomes "1", the output of FF10 Data is inverted and output.

  Specifically, as long as the data propagated through the above-described FF1 to 4 changes with the input of the clock signal, the data output from the EOR5 and input to the input 6a of the EOR6 is always "1". . Then, the data “1” is set in the FF 10 together with the input of the next clock signal, and the FF 10 outputs the data “1”. As a result, data “1” is input to the input 6b of EOR6, and data output from EOR5 by the exclusive OR operation is “0”. Accordingly, the data “0” is set in the FF 10 together with the input of the next clock signal, and the FF 10 outputs the data “0”.

  That is, when the output data of the FF 10 whose value changes with the input of the clock signal propagates to the unit X via the units Y and Z, the data set in the FF 4 in the unit X changes, and as a result, the output of the FF 10 is output. Data propagates while changing with the input of the clock signal.

  The error detection circuit 20 is a circuit that detects a clock error by detecting whether or not the value of the FF 10 changes within a certain time. If the value of the FF 10 does not change within a certain time, an error is detected. It is determined that it has occurred.

  FIG. 2 shows the check circuit 100 of the unit X, but it is assumed that the unit Y and the unit Z also have a similar check circuit, and all FFs on the check circuit are initially “0”. When starting the error check, “1” is set in the FF 10 of the unit X. Then, “1” propagates to the unit Y, and “1” is set to the FF 10 included in the unit Y. Similarly, “1” is set in the FF 10 of the unit Z and the unit X returns. Then, when “1” is propagated to the unit X, the FF 10 is set to “0”, and the FF 10 included in the unit X, the unit Y, and the unit Z is changed from “0” to “1” together with the input of the clock signal. Continues to change from '→' 0 '.

  When a sufficient time has passed since the first FF 10 was set to “1” and the unit X, unit Y, and unit Z started to operate, the error check by the check circuit 100 is validated. When an error is detected in the unit X, it can be determined that the operation of the FF 10 included in either the remaining unit Y or unit Z is not normal.

As described above, in the first embodiment, each unit is divided into a plurality of functional blocks or area blocks, and the check circuit 100 including the FF 10 that performs the clock operation is provided in each functional block or each area block. Data is inverted every time a change in input data is detected by EOR5 and transmitted in a loop between functional blocks or between area blocks, and whether or not the value of the shifted data changes within a predetermined time The clock can be monitored by the detection circuit 20 checking. The operations of the clock monitoring mechanism according to the first embodiment at the normal time and when an error occurs are shown in FIGS.

  In the first embodiment, the case where the clock is monitored by propagating data that changes with the input of the clock signal in a loop form between the units has been described. However, the clocks can also be monitored between the units. . Therefore, in the second embodiment, a case where the clocks are monitored between the units will be described.

  FIG. 3 is an explanatory diagram for explaining the clock monitoring mechanism according to the second embodiment. This figure shows a case where a unit U operating with the clock of the oscillator U and a unit V operating with a clock of the oscillator V different from the oscillator U monitor the clocks.

  As shown in FIG. 3, the unit U has an output circuit 211 and a check circuit 212, and the unit V similarly has an output circuit 221 and a check circuit 222. Then, the output circuit 211 of the unit U sends out a bit that is inverted every predetermined time, and the bit V sent out by the output circuit 211 is checked by the check circuit 222 of the unit V, while the output circuit 221 of the unit V also checks every predetermined time. When the check circuit 212 of the unit U checks the bit sent by the output circuit 221, the clock signal output from the oscillator U or the oscillator V operates correctly between the unit U and the unit V. Monitor whether or not

  Further, there is an error report path (interrupt in FIG. 3) so that a circuit that can operate independently of the oscillator U and the oscillator V can cope with the error when the check result in the unit U and the unit V is an error.

  FIG. 4 shows the output circuit 211 and the check circuit 222 shown in FIG. The output circuit 211 and the check circuit 222 include an SR (set reset) latch 211a and an SR latch 222a that hold a check circuit valid flag indicating the start of operation. After completion of the initialization of each unit, the check circuit valid flag SR latch 211a of the output circuit 211 and the check circuit valid flag SR latch 222a of the receiving circuit 222 are subsequently set at the timing after the clock starts (has). Set to 1 ”.

  Further, the output circuit 211 is equipped with a 3-bit incrementer 211b. This incrementer 211b is incremented as long as the clock enters when the check circuit valid flag SR latch 211a is "1", and the check circuit When the valid flag SR latch 211a is “0” or when a change in data from the unit V is detected, the reset is continued and no increment is performed. In other words, the increment condition of the incrementer 211b is that the value of the SR latch 211b for the check circuit valid flag is “1”, and the reset condition is for detection of a change in data from the unit V or for the check circuit valid flag. The value of the SR latch 211b is “0”. Note that the necessary number of bits of the incrementer 211b varies depending on the period difference between the oscillator U and the oscillator V.

  Then, the output circuit 211 sends the output of the most significant bit of the incrementer 211b to the unit V via the synchronization circuit 230. Therefore, if the clock of the unit U is in a normal state, the data sent to the unit V changes every 4 clocks in which a carry occurs in the most significant bit of the incrementer 211b. The synchronization circuit 230 is a circuit in which flip-flops that perform clock operation are directly connected, and is a circuit that is provided to synchronize with the clock signal of the most significant bit output of the incrementer 211b. The reason for performing synchronization is to prevent FF malfunction due to the metastable phenomenon. Metastable is a phenomenon in which the output of the FF stays at a potential near the threshold for a long time. When metastable occurs, it not only causes malfunction, but also causes deterioration of the element. By receiving using a synchronization circuit in which two or more stages of FFs are connected in series, the metastable phenomenon at the output Can be reduced to a practically acceptable level.

  On the other hand, the check circuit 222 of the unit V also has a 3-bit incrementer 222b. Similarly to the incrementer 211b of the output circuit 211, the incrementer 222b is incremented as long as the check circuit validity flag SR latch 222a is "1", and the check circuit validity flag SR latch 222a is "0" or If a change in data from the unit U is detected, the reset is continued and no increment is performed. That is, the increment condition of the incrementer 222b is that the value of the SR latch 222b for the check circuit valid flag is “1”, and the reset condition is that the change in data from the unit U is detected or the check circuit valid flag is used. The value of the SR latch 222b is “0”. Note that the necessary number of bits of the incrementer 222b varies depending on the period difference between the oscillator U and the oscillator V.

  Therefore, if the state is normal, the value of the incrementer 222b is reset every 4 clocks when a carry occurs in the most significant bit of the incrementer 222b, and the value of the incrementer 222b is, for example, “111”. Absent. Therefore, when the value of the incrementer 222b becomes “111”, no change in data from the unit U is detected within a certain time.

  The error detection circuit 222c is a circuit that detects an error by decoding that the value of the incrementer 222b is “111”, and can operate independently of the oscillator U and the oscillator V when an error is detected. Report an error to

  As described above, in the second embodiment, the incrementer 211b of the output circuit 211 of the unit U increments based on the clock input, sends the most significant bit to the check circuit 222, and sends the data sent from the output circuit 211. Is changed, the incrementer 222b of the check circuit 222 is reset, and when the value of the incrementer 222b becomes "111", the error detection circuit 222c reports an error, so the clock of the oscillator U can be monitored.

  In the second embodiment, the case where the clock operations are mutually monitored between the two units has been described. However, the clock operations can be similarly monitored between three or more units. FIG. 5 is a diagram illustrating mutual monitoring of clocks in three units. As shown in the figure, in three units of unit P, unit Q, and unit R, the data sent by the output circuit of unit P is checked by the check circuit of unit Q, and the data sent by the output circuit of unit Q is sent. The check circuit of the unit R checks and the check circuit of the unit P checks the data transmitted from the output circuit of the unit R, so that the clock operation can be monitored among the three units.

  Next, the normal operation and the error occurrence operation of the clock monitoring mechanism according to the second embodiment will be described. FIG. 8 is a timing chart showing an operation at a normal time, and FIG. 9 is a timing chart showing an operation at the time of occurrence of an error.

  In FIG. 8, “output clock” is the output of the oscillator U in FIG. 3, and “output circuit start_flag” is the output of the check circuit valid flag SR latch 211a on the unit 211 side in FIG. The 3BIT incrementer 211b performs a count operation. When the value is 1, the count operation is stopped by continuing to reset the 3BIT incrementer 211b. “Out CT” indicates the value of the 3BIT incrementer 211b in the unit 211 which is the output side counter of FIG. “CT0, CT1, CT2” represents the bit 0 output, bit 1 output, and bit 2 output of the 3BIT incrementer 211b, respectively.

  “Receiver clock” indicates the output of the oscillator V in FIG. 3, “Synchronization” indicates a signal synchronization process in the synchronization circuit 230 in FIG. The first, second, third, and fourth waveforms are the first-stage synchronization FF, second-stage synchronization FF, third-stage synchronization FF, and fourth-stage waveform of the synchronization circuit 230, respectively. Represents the output of the synchronized FF. The fifth waveform from the top represents the output of the reception FF in the reception-side unit 222 of FIG. Furthermore, the arrow that goes down from the fourth waveform from the top to the “Check CT” stage in the “Synchronization” column represents an edge trigger operation by the EOR circuit of the unit 222 in FIG. That is, by performing an exclusive OR operation between the input and output of the fifth-stage synchronization FF by EOR, the rising edge of the waveform and the falling edge of the waveform are detected, and the count value of the 3BIT incrementer 222b is set. Reset.

  “Check start flag” is the output of the SR latch 222b for the check circuit valid flag on the unit 222 side in FIG. 4. When the value is 0, the 3BIT incrementer 222b performs a count operation, and when the value is 1, 3BIT The count operation is stopped by continuing to reset the incrementer 222b.

  Here, the timing chart of the normal operation in FIG. 8 will be described. First, when the “output clock” is operating normally as the output of the oscillator U in FIG. 3, the check circuit on the unit 211 side in FIG. By setting “1” to the SR latch 211a for the valid flag, the “out circuit start_flag” on the timing chart becomes “1”, the 3BIT incrementer 211b on the unit 211 side in FIG. “CT0, CT1, CT2” of “CT” operates, and the output of bit 2, which is the most significant bit, that is, “CT2” in the timing chart becomes 1.

  The unit 211 outputs the bit 2 which is the most significant bit signal of the 3BIT incrementer 211b, and the most significant bit output signal is synchronized by the 4-stage FF of the “synchronization circuit 230”.

  By setting “1” to the SR latch 222b for the check circuit valid flag on the unit 222 side in FIG. 4, the “check start flag” on the timing chart in FIG. 8 becomes “1”, and the 3BIT on the unit 222 side in FIG. The incrementer 222b starts the counting operation, and “CT0, CT1, CT2” of “out CT” starts the counting operation. Here, by the edge trigger operation by the EOR circuit of the unit 222 in FIG. 4 described above, the rising and falling edges of the most significant bit signal after synchronization by the synchronization circuit 230 are detected, and the 3BIT incrementer on the unit 222 side is detected. Since the reset is performed every 4 clocks, the “check CT” does not perform the mounting operation until “111” which is an error detection condition. Therefore, in the second embodiment of FIG. 4, it can be seen that the error is not detected as long as the oscillator U of FIG. 3 operates normally.

  Next, the operation of the timing chart when an error occurs in FIG. 9 will be described. Specifically, a description will be given of a case where the “sending clock” is stopped during the normal operation described above. The description of the signal name is the same as the description in FIG.

  When the oscillator U in FIG. 3 stops during the above-described normal operation, first, the “sending clock” in FIG. 9 stops (at the time of “★” in FIG. 9). As a result, the count operation of the 3BIT incrementer 211b is stopped even though “1” is set in the SR latch 211a for the check circuit valid flag in FIG. Then, the most significant bit 2, that is, the output of “CT 2” in the timing chart is fixed to “0” or “1”, and the result of the exclusive OR operation of the EOR in the receiving side unit 222 is Since “3” is always “0”, the 3BIT incrementer 222b is not reset, and every time the clock of the oscillator V in FIG. 3 is input, the count operation of the 3BIT incrementer 222b is performed. “CT0”, “CT1”, and “CT2” are counted up to “111”, and an error is detected as a result of decoding the counter value “111” by the error detection circuit 222c.

  In the first and second embodiments, the case where the operation of the clock is monitored has been described. However, the present invention is not limited to this, and the same applies to the case where the abnormality of the FF control system that operates based on the clock is monitored. Can be applied to.

  As described above, the clock monitoring circuit, the information processing apparatus, and the clock monitoring method according to the present invention are useful for detecting an abnormality in the information processing apparatus, and are particularly suitable when clock monitoring is necessary with a small amount of hardware. .

FIG. 1 is an explanatory diagram for explaining the clock monitoring mechanism according to the first embodiment. FIG. 2 is a functional block diagram illustrating the configuration of the check circuit according to the first embodiment. FIG. 3 is an explanatory diagram for explaining the clock monitoring mechanism according to the second embodiment. FIG. 4 shows the output circuit 211 and the check circuit 222 shown in FIG. FIG. 5 is a diagram illustrating mutual monitoring of clocks in three units. FIG. 6 is an explanatory diagram for explaining mutual timeout monitoring. FIG. 7 is a diagram illustrating an example of processing after error detection. FIG. 8 is a timing chart showing the normal operation of the second embodiment. FIG. 9 is a timing chart showing the operation at the time of error according to the second embodiment. FIG. 10 is a timing chart showing the normal operation of the first embodiment. FIG. 11 is a timing chart illustrating the operation at the time of error according to the first embodiment.

Explanation of symbols

1-4 FF (flip-flop)
5,6 EOR (Exclusive OR operation circuit)
10 FF (flip-flop)
20 Error detection circuit 100 Check circuit 211 Output circuit 211a Check circuit valid flag 211b Incrementer 212 Check circuit 221 Output circuit 222 Check circuit 222a Check circuit valid flag 222b Incrementer 222c Error detection circuit

Claims (5)

Each clock monitoring circuit when a plurality of clock monitoring circuits are connected in a ring shape,
Data receiving means for receiving data output from the clock monitoring circuit in the previous stage;
Data change detecting means for detecting a change in data received by the data receiving means ;
Each time a change in the data by the previous SL data change detection means is detected, at the input timing of the clock signal, a data output means for outputting the inverted data to the subsequent clock monitoring circuit,
It is detected whether or not the output data of the data output means changes within a certain time obtained by summing the processing time from data input to data output in all clock monitoring circuits connected in the ring shape. Error detection means for determining that an error has occurred when no change is detected in
A clock monitoring circuit comprising: The data change detecting means includes data holding means for holding data by inputting a clock signal;
Logical operation means for performing an exclusive OR operation between the input and output of the data holding means;
The clock monitoring circuit according to claim 1, further comprising: Have a first and second units, the input and output of each unit is an information processing apparatus connected to each other,
The first unit is:
Data receiving means for receiving data output from the data output means of the second unit;
Data change detecting means for detecting a change in data received by the data receiving means ;
Each time a change in the data by the previous SL data change detection means is detected, at the input timing of the clock signal, a data output means for outputting the inverted data to the second unit,
Detecting whether the output data of the data output means changes within a certain time obtained by summing the processing time from data input to data output in each unit, and if no change is detected within the certain time, Error detection means for determining that an error has occurred in the second unit;
An information processing apparatus comprising: Have a plurality of units, the plurality of units is an information processing apparatus connected in a ring,
Among the plurality of units, one unit is:
Data receiving means for receiving data output from the data output means of the preceding unit of the plurality of units;
Data change detecting means for detecting a change in data received by the data receiving means ;
Each time a change in the data by the previous SL data change detection means is detected, at the input timing of the clock signal, a data output means for outputting the inverted data to the subsequent unit,
When it is detected whether the output data of the data output means changes within a certain time totaling the processing time from data input to data output in the plurality of units, and when no change is detected within the certain time, Error detection means for determining that an error has occurred in a unit other than the own unit;
An information processing apparatus comprising: A clock monitoring method for monitoring a circuit when a plurality of circuits operating in synchronization with a clock signal are connected in a ring shape ,
A data receiving step for receiving data output from the previous circuit;
A data change detecting step for detecting a change in the data received in the data receiving step ;
Each time a change in the data before Symbol data change detecting step is detected, at the input timing of the clock signal, a data output step of outputting the inverted data to the subsequent circuit,
Detects whether or not the data output by the data output step changes within a certain time obtained by summing the processing time from data input to data output in all the circuits connected in the ring shape, and within the certain time An error detection step for determining that an error has occurred when no change is detected in
A clock monitoring method comprising:

Images