JP2864663B2 - Watchdog timer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a watchdog timer, and more particularly to a watchdog timer built in a microcomputer.

[Conventional technology]

A conventional technique will be described with reference to the drawings. FIG. 3 is a block diagram of a conventional watchdog timer. The conventional watchdog timer includes a timer 301, a watchdog timer clear signal WCLR, a clock signal CLK, and a watchdog timer output signal WDTO.

The watchdog timer is usually used by being connected to a CPU (not shown) in the microcomputer. When the CPU decodes the instruction that generates the watchdog timer clear signal, the watchdog timer clear signal WCLR
To the logical value “1”. The watchdog timer clear signal WCLR is input to the timer 301.

The timer 301 is a timer having a period T, and has a clock signal CLK.
Is incremented at the rising edge of, and reset when the timer clear signal WCLR from the CPU has the logical value "1". Timer
When 301 overflows, the overflow signal OVF is set to the logical value “1”.

The overflow signal OVF is the watchdog timer output signal WDTO.

 Next, the operation of the conventional technique will be described.

When the CPU decodes the instruction that generates the watchdog timer clear signal WCLR, the watchdog timer clear signal WCLR becomes a logical value “1”, and the timer 301 is reset.

Since the cycle of the timer 301 is T, the timer 301 is cleared before overflowing by inserting an instruction to generate the watchdog timer clear signal WCLR at a shorter interval than T in the program executed by the CPU in advance. During the normal operation of the CPU, the overflow signal OVF of the timer 301 does not become the logical value “1”.
The watchdog timer output signal WDTO does not become the logical value “1”.

However, if an error occurs in the CPU and the instruction that generates the watchdog timer clear signal WCLR cannot be decoded, the timer 301 overflows without being cleared.
The overflow signal OVF becomes a logical value “1”, and the watchdog timer output signal WDTO becomes a logical value “1”. By outputting the watchdog timer output signal WDTO to the outside, it is possible to recognize that an abnormality has occurred in the CPU and take a predetermined countermeasure.

[Problems to be solved by the invention]

Conventional technology detects an error when a deadlock occurs in a loop containing an instruction that generates a watchdog timer clear signal, or when the watchdog timer clear signal is fixed to a logical value of “1”. There is a problem that can not be.

[Means for solving the problem]

The watchdog timer of the present invention is cleared by a predetermined clear signal, counts a predetermined clock, overflows when a predetermined time elapses, time elapse detection means for detecting elapse of a predetermined time period, A second counting means for counting a clear signal for clearing the first counting means during a predetermined period detected by the time lapse detecting means, wherein the overflow of the first counting means and the second counting means The abnormality detection signal is generated by the logical sum of the detection of counting the number of times.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a watchdog timer using the present invention. The watchdog timer is timer 101, timer 102,
It comprises a counter 103 and an OR gate 104.

The timer 101 is a timer having a period T1 and has a clock signal CLK.
Increments at the rising edge of the clock, and is reset when the watchdog timer clear signal WCLR from the CPU reaches the logical value “1”.
Set OVF1 to logical value "1". Overflow signal CVF1 is OR
Input to the gate 104.

The timer 102 is a timer having a period T2 and has a clock signal CLK.
Increment at the rise of
The overflow signal OVF2 is set to the logical value “1”. The overflow signal OVF2 is input to the counter 103.

The counter 103 is a 4-bit counter. The counter 103 is reset when the overflow signal OVF2 from the timer 102 becomes a logical value “1”, and is incremented when the timer clear signal WCLR from the CPU is a logical value “1”. Set carry signal CY to logical value “1”. Carry signal CY is OR gate
Entered in 104.

The OR gate 104 is a two-input OR gate, and includes an overflow signal OVF1 of the timer 101 and a carry signal C of the counter 103.
If any of Y is “1”, the watchdog timer output signal WDTO is set to the logical value “1”.

 Next, the operation of the present invention will be described.

The operation of the timer 101 is the same as that of the conventional technology. If the instruction that generates the watchdog timer clear signal WCLR cannot be decoded, the timer 101 is not cleared, the overflow signal OVF1 becomes a logical value “1”, and the OR operation is performed. Gate 204
Output signal WDTO becomes a logical value "1".

The counter 103 is a 4-bit counter. Since the cycle of the timer 102 is T2, when the instruction to generate the watchdog timer clear signal WCLR is decoded 16 times or more during the period of T2, the carry signal CY of the counter 103 is output. Is the logical value “1”
And the watchdog timer output signal WDTO becomes the logical value “1”. Thus, an interrupt can be generated even when the program is deadlocked in a loop including an instruction for generating the watchdog timer clear signal WCLR.

A second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the present invention.

Watchdog timer is timer 201, counter 203, OR
It comprises a gate 204, a NOR gate 205, and an AND gate 206.

The timer 201 is an 8-bit timer having a period T1 and is incremented at the rising edge of the clock signal CLK. The timer 201 is reset when the watchdog timer clear signal WCLR from the CPU becomes a logical value “1”. Set to logical value “1”. The overflow signal OVF1 is input to the OR gate 204,
７7 bits are input to the 4NOR gate 205.

The NOR gate 205 is a 4-input NOR gate, and the timer 201
When the 4 to 7 bits of the data of the timer 201 are all logical values "0", the output is set to the logical value "1". The output of the NOR gate 205 is input to the AND gate 206.

The AND gate 206 is a two-input AND gate, which receives the watchdog timer clear signal WCLR and the output of the NOR gate 205 and receives the watchdog timer clear signal WCLR and NOR.
When the output of each of the gates 205 is a logical value “1”, the output is set to a logical value “1”. The output of the AND gate 203 is input to the counter 203.

The counter 203 is a 4-bit counter. The counter 203 is reset when the fourth bit of the data of the timer 201 becomes a logical value “1”, and is incremented when the output of the AND gate 206 is a logical value “1”. Set the signal CY to the logical value “1”. Carry signal CY is input to OR gate 204.

The OR gate 204 is a two-input OR gate, and includes an overflow signal OVF1 of the timer 203 and a carry signal C of the counter 203.
If any of Y is logic value “1”, the watchdog
Set the timer output signal WDTO to “1”.

 Next, the operation of the present invention will be described.

The operation of the timer 201 is the same as that of the first embodiment. If the instruction for generating the watchdog timer clear signal WCLR cannot be decoded, the timer 201 is not cleared and the overflow signal OVF1 becomes a logical value "1". , OR gate 20
The output signal WDTO of 4 becomes the logical value “1”.

The counter 103 increments by the AND gate 206
Is when the logical value is “1”. The output of the AND gate 206 becomes the logical value “1” when the instruction for generating the watchdog timer clear signal WCLR is decoded while the output of the NOR gate 205 is the logical value “1”. Is timer 2
Counts the number of decoded instructions that generate the watchdog timer clear signal WCLR during the period from "0000000" to "00001111" of the 01 data. . Timer 201 data is “000
When the count reaches "1000", the counter 203 is cleared.

In this embodiment, since only one timer is used, the size of the circuit can be reduced.

〔The invention's effect〕

As described above, according to the present invention, the watch dog
An interrupt can be generated not only when the instruction that generates the timer clear signal is not decoded, but also when the watchdog timer clear instruction is continuously decoded, enabling early detection of CPU errors. Because it can be done, it is possible to build a safe system.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional technique. 101, 102, 201, 301 ... Timer, 103, 203 ... Counter, 10
4,204: OR gate, 205: NOR gate, 206: AND gate, CLK: Clock signal, WCLR: Watchdog timer clear signal, OVF, OVF1, OVF2: Overflow signal, CY: Carry signal WDTO: Watchdog timer output signal.

Claims (1)

(57) [Claims] 1. A first counting means which is cleared by a predetermined clear signal, counts a predetermined clock, and overflows when a predetermined time elapses, a time elapse detecting means for detecting elapse of a predetermined period, and the time elapse detection A second counting means for counting a clear signal for clearing the first counting means during a predetermined period detected by the means, wherein the overflow of the first counting means and the second counting means are performed by a predetermined number. A watchdog timer that generates an abnormality detection signal based on the logical sum of detection of counting.