JPH0425948A - Watch dog timer - Google Patents

Abstract

PURPOSE:To detect abnormality by generating an abnormality detection signal from OR detecting the overflow of a first counting means and that a second counting means counts for a prescribed number. CONSTITUTION:Since a counter 103 is that of four bits and the period of a timer 102 is T2, the carry signal CY of the counter 103 comes to a logical value '1' and a watch dog timer output signal WDTO comes to the logical value '1' when an instruction generating a watch dog timer clear signal WCLR is decoded for more than 16 times in the period of T2. Thus, interruption can be generated even if the program deadlocks a loop containing the instruction generating the watch dog timer clear signal WCLR. Thus, a safe system can be constructed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a watchdog timer, and particularly to a watchdog timer built into a microcomputer.

[Conventional technology]

A conventional technique will be explained with reference to the drawings. FIG. 3 is a block diagram of a conventional watchdog timer. The conventional watchdog timer is timer 3o1゜watchdog timer.
It consists of a timer clear signal WCLR, a clock signal cLK, and a watchdog timer output signal WDTO.

A watchdog timer is normally used by being connected to a CPU (not shown in the figure) in a microcomputer. C
When the PU decodes a command to generate a watchdog timer clear signal, it sets the watchdog timer clear signal WCLR to a logical value of "1". Watchdog timer clear signal WCLR is input to timer 301.

Timer 301 is a timer with period T, and clock signal C
It is incremented at the rising edge of LK, and is reset when the timer clear signal WCLR from the CPU has a logical value of ``1''. When the timer 301 overflows, the overflow signal OVF is set to a logical value "1".

Overflow signal OVF is watchdog timer output signal WDTO.

Next, the operation of the conventional technique will be explained.

When the CPU decodes the instruction to generate the watchdog timer clear signal WCLR, the watchdog timer clear signal WCLR becomes a logical value u I II and the timer 301 is reset.

Since the timer 3010 period is T, by inserting in advance an instruction to generate the watchdog timer clear signal WCLR at intervals shorter than T in the program executed by the CPU, the timer 301 can be cleared before it overflows. While the CPU is operating normally,
The overflow signal OVF of the timer 301 has a logical value of “1”.
'', and the watchdog timer output signal WDTO never becomes the logic value "'1".

However, if an abnormality occurs in the CPU and the instruction that generates the watchdog timer clear signal WCLR cannot be decoded, the timer 301 is not cleared and overflows, and the overflow signal OVF becomes the logical value "'1pa", causing the watchdog timer clear signal WCLR to be decoded. The dog timer output signal WDTO becomes a logical value of "1".

By outputting the watchdog tie and master output signal WDTO to the outside, it is possible to recognize that an abnormality has occurred in the CPU and take a prescribed countermeasure.

[Problem to be solved by the invention]

With conventional technology, an abnormality is detected when a deadlock occurs due to a loop containing an instruction that generates a watchdog timer clear signal, or when the watchdog timer clear signal is fixed at a logical value of II I 11. The problem is that it cannot be done.

[Means to solve the problem]

The watchdog timer of the present invention is cleared by a predetermined clear signal, counts a predetermined clock, and overflows when a predetermined time elapses.A first counting means, a time elapse detection means for detecting the passage of a predetermined period; and a second counting means for counting a clear signal that clears the first counting means during a predetermined period detected by the time elapse detection means, wherein the overflow of the first counting means and the second counting means are determined in a predetermined period. The abnormality detection signal is generated by the logical sum of the detected number of counts.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a watchdog timer using the present invention. The watchdog timer is timer 101.
Timer 102. Counter 103. It is composed of an OR gate 104.

The timer 101 is a timer with a period Tl, and increments at the rising edge of the clock signal CLK, and the watchdog timer clear signal WCLR from the CPU has a logic value of "1".
When the overflow occurs, the overflow signal 0VF1 is set to the logic value "1".The overflow signal 0VF1 is input to the OR gate 104.

The timer 102 is a timer with a period T2, and increments at the rising edge of the clock signal CLK, and when it overflows, sets the overflow signal ○VF2 to a logical value "l"
Make it. Overflow signal 0VF2 is counter 10
3 is input.

Counter 103 is a counter with 4 pins), and timer 1
Overflow signal from 02 ○VF2 has logical value “1”
It is reset when the timer clear signal WCLR from the CPU has a logical value of ``1'', and is incremented.
When the value becomes 16, the carry signal CY is set to the logical value II I
Make it II. Carry signal CY is input to OR gate 104.

OR game +-104 is an OR gate operated by two people, and the overflow signal ○VFI of timer 101 and counter 10
If any of the carry signals CY of 3 is 1°, the watchdog timer output signal WDTO is set to the logical value °'1.
Make it ゛.

Next, the present invention will be explained in detail.

The operation of the timer 101 is the same as that of the conventional technology, and if the command that generates the watchdog timer clear signal WCLR cannot be leveraged, the timer 101 is not cleared and the overflow signal OVF1 becomes the logical value "1". '', and the output signal WDTO of the OR gate 204 becomes the logical value I.
It becomes I 1 n.

The counter 103 is a 4-bit counter, and the timer 102
Since the 0 cycle is T2, there are 16 instructions to generate the watchdog timer clear signal WCLR during the T20 period.
When it is decoded more than once, the carry signal CY of the counter 103 becomes the logic value i+ 1 ++, and the watchdog timer output signal WDTO becomes the logic value II 1". As a result, the watchdog timer clear signal WCLR
An interrupt can also be generated when a program is putlocked in a loop that includes an instruction that generates an interrupt.

A second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the invention.

The watchdog timer is timer 201. counter 20
3. OR game) 204. It is composed of a NOR gate 205 and an AND gate 206.

The timer 201 is an 8-bit timer with a period Tl, and increments at the rising edge of the clock signal CLK.
It is reset when the watchdog timer clear signal WCLR from U becomes a logic value "1", and when an overflow occurs, the overflow signal OVF is set to a logic value "1".The overflow signal 0VF1 is input to the OR gate 204, 4 to 7 hits of the output of timer 201 are 4NOR
The information is input into the gate 205.

NOR gate 205 is a four-man powered NOR gate that inputs 4 to 7 bits of data from timer 201 and outputs data from timer 2.
When all 4 to 7 bits of data 01 have a logic value of "0°", the output is set to a logic value of 1°.NOR gate 20
The output of 5 is input to AND gate 206.

AND gate 206 is a two-person AND gate that inputs watchdog timer clear signal WCLR and the output of NOR gate 205, and both watchdog timer clear signal WCLR and the output of NOR gate 205 have a logical value "'l". ”, set the output to logical value “l 11.A
The output of the ND game 1-203 is input to the counter 203.

The counter 203 is a 4-bit counter, and the timer 20
It is reset when the fourth bit of data 1 becomes the logic value II 1)), and increments when the output of the AND gate 206 is the logic value 1", and when the value becomes 16, the carry signal CY is set to the logic value "1". do. Carry signal CY is input to OR gate 204.

The OR gate 204 is a two-man operated OR gate, and the overflow of the timer 203 (10VF1.!: Counter 2
Any of the carry signals CY of 03 has a logical value "l'"
If so, the watchdog timer output signal WDTO is set to '1'.

Next, the present invention will be explained in detail.

The operation of the timer 201 is the same as in the first embodiment, and when the instruction that generates the watchdog timer clear signal WCLR cannot be decoded, the timer 201 is not cleared and the overflow signal ○vFl becomes the logical value "1". Therefore, the output signal WDTO of the OR gate 2o4 has the logical value "1".
become.

The counter 103 increments when the AND gate 206 has a logical value of "1".AND gate 206
It is the NOR gate 205 that outputs the logical value “1”.
This is a case where the instruction to generate the watchdog timer clear signal WCLR is decoded during the period when the output of the timer 201 is a logic value of "'1", and the counter 203 changes the data of the timer 201 from "'oooooooo" to "'00001111". The number of decoded instructions that generate the watchdog timer clear signal WCLR during the period is counted, and if it is 16 or more, the carry signal CY is set to a logical value of "1°". When the data of the timer 201 becomes "'0001000", the counter 203 is cleared.

Since this embodiment uses only one timer, the circuit can be made smaller.

〔Effect of the invention〕

'As explained above, the present invention provides a watchdog
It is now possible to generate an interrupt not only when the instruction that generates the timer clear signal is not decoded, but also when the watchdog timer clear instruction continues to be decoded, making it possible to detect CPU abnormalities at an early stage. This makes it possible to build a secure system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and 311ffl is a block diagram of a conventional technique. 1.01, 102, 201, 301... Timer 103.203... Counter, 104, 204
...OR gate, 205...NOR gate, 206...A, ND gate, CLK...
...Clock signal, WCLR...Watchdog timer clear signal, OVF, 0VF1, 0VF
2-----・-over 7o- signal, CY...
Carry signal, WDTO... Watchdog
Timer output signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a first counting means that is cleared by a predetermined clear signal, counts a predetermined clock, and overflows when a predetermined time elapses; a time elapse detection means that detects the elapse of a predetermined period; and a predetermined time elapse detection means that is detected by the time elapse detection means. a second counting means for counting clear signals that clear the first counting means during a period;
counting means, and generates an abnormality detection signal based on the logical sum of an overflow of the first counting means and a detection that the second counting means has counted a predetermined number.