JP2814800B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a watchdog timer for detecting a microcomputer abnormality.

[0002]

2. Description of the Related Art Some conventional microcomputers have a built-in watchdog timer for coping with program runaway and system abnormalities.

[0003] The watchdog timer is provided with a counter for clearing the count value and is constituted by a counter which outputs overflow information of the count value. Executes the watchdog timer counter start instruction to start counting, and clears the watchdog timer count value in the program flow before the count value overflows (hereinafter referred to as the watchdog timer clear instruction). ) Is executed to prevent the count value of the watchdog timer from overflowing, thereby confirming that the program is operating normally.
If a program runaway or system error occurs and the watchdog timer clear instruction is not executed,
An overflow of the count value occurs, and a central processing unit (hereinafter referred to as a CPU) of the microcomputer detects an overflow of the count value of the watchdog timer,
By executing a processing routine for an abnormality or the like, the user can increase the reliability of the entire microcomputer system.

Further, the watchdog timer clear instruction may have a special code configuration so that the count value is not inadvertently cleared due to a program runaway. For example, RSTWDT # imm8 (1), # imm8
The watchdog timer clear instruction having the configuration of (2) is a 2-byte instruction, and when the operation codes of the third and fourth bytes are # imm8 (1) and # imm8 (2) are complements of each other, The watchdog timer count value is cleared. If the third and fourth byte operation codes are not complements due to a program runaway or the like, a software interrupt occurs, and the CPU executes a processing routine for the abnormality.

The microcomputer has a STOP state in which a system clock is stopped as a standby function for reducing power consumption. Executing the STOP instruction stops all clocks, stops the entire application system, and enters the STOP state. The watchdog timer that has entered the STOP state stops counting.

FIG. 5 is a block diagram showing a configuration example of a conventional microcomputer. The microcomputer shown in FIG. 5 includes a CPU 1 for controlling the entire system, an interrupt control circuit 2 for controlling an interrupt, a clock generation circuit 3 for generating a system clock 30, a standby function control circuit 5b for controlling a standby function, and a program. And a watchdog timer 6 for detecting an abnormality in.

[0007] The CPU 1 sends a STOP order 32 indicating execution of a STOP instruction to the standby control circuit 5b.
Output to The interrupt control circuit 2 receives the interrupt and
An interrupt generation signal 31 for notifying U1 that an interrupt has occurred is output. The clock generation circuit 3 outputs a system clock to each functional block. The standby function control circuit 5b outputs a STOP_A signal 37 for activating the STOP state to the clock generation circuit 3.

When the microcomputer enters the STOP state, the CPU 1 decodes the STOP instruction and
The order 32 is set to “1”. The standby control circuit 5b having received the STOP order 32 outputs the STOP_A signal 37.
Is “1”. The clock generation circuit 3 that has received the STOP_A signal 37 stops the system clock 30.
The watchdog timer 6 that performs the counting operation by inputting the system clock 30 stops counting.

In a normal use state, when the CPU 1 executes the watchdog timer clear instruction to set the watchdog timer clear signal 37 to "1", the count value of the watchdog timer 6 is cleared and the count is restarted. . If the instruction code cannot take a special code configuration due to a program runaway when the CPU 1 reads the watchdog timer clear instruction, a software interrupt occurs. With this software interrupt, the CPU 1 responds to a program error.

[0010]

In the above-mentioned conventional microcomputer, a watchdog timer clear instruction having a special program configuration is inserted into a program so that the count value of the watchdog timer does not overflow. The CPU can deal with runaway of the program. However, if the STOP instruction is executed due to the program runaway and the STOP state is entered before the watchdog timer clear instruction is executed, the watchdog timer stops counting, and the program is not operating normally. Cannot be detected by overflow of the count value of the watchdog timer. Also, using other means,
Nor can it detect program runaway.

The present invention has been made in view of such a problem, and a CPU detects a system abnormality before a STOP instruction which is not originally expected is executed due to a runaway of a program or the like, and It is an object of the present invention to provide a microcomputer capable of coping with runaway of a program.

[0012]

A microcomputer according to the present invention realizes a central processing unit, an interrupt control circuit for controlling an interrupt, a clock generation circuit for supplying a system clock to the entire system, and low power consumption. Control circuit, a microcomputer having a watchdog timer, and a storage circuit for storing that the STOP instruction is executed immediately after the instruction for clearing the count value of the watchdog timer, and the contents of the storage circuit and the standby state And a means for comparing the level with a signal for activating the program, and a means for entering a standby state when the result of the comparing means matches, and for requesting an interrupt processing when the result does not match.

[0013]

In the microcomputer according to the present invention, the standby control circuit 5a sets the STOP_A signal 37 which activates the STOP state by a STOP instruction to "1". When the watchdog timer clear instruction and the STOP instruction are executed successively, the output of the SR flip-flop 13 becomes "1". SR flip-flop 13 and STOP
If both _A signals 37 are “1”, STOP_B
The signal 38 is set to "1" to cause the clock generation circuit 3 to stop generating the system clock. SR flip-flop 1
When 3 is "0" and the STOP_A signal 37 is "1", the interrupt request signal 35a becomes "1". Further, the clock generation circuit 3 does not stop the system clock.

Therefore, even if a STOP instruction that is not expected is executed, the watchdog timer does not stop, and an abnormality in the system can be detected by overflow of the count value of the watchdog timer.

[0015]

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a microcomputer according to an embodiment of the present invention. The microcomputer shown in FIG. 1 has a CPU 1 for controlling the entire system.
An interrupt control circuit 2 for processing each interrupt; a clock generation circuit 3 for generating a system clock 30; and a STOP signal control circuit 4a for detecting that a watchdog timer clear instruction and a STOP instruction are continuously executed.
And a standby control circuit 5a for controlling a standby function
And

The CPU 1 sends to the STOP signal control circuit 4a a watchdog timer clear signal 37, an end signal 34 indicating the end of each execution instruction, and a STOP signal control circuit 4a.
It outputs a reset signal 33 for initializing the information a, a STOP order 32 indicating that the STOP command is to be executed to the standby control circuit 5a, and outputs the STOP order 32 to the standby control circuit 5a. The interrupt control circuit 2 outputs an interrupt generation signal 31 for requesting the CPU 1 to perform an interrupt process. The clock generation circuit 3
The system clock 30 is output to each function. STO
The P signal control circuit 4a controls the AND gate 24 (hereinafter referred to as an AND gate) 24 to control the STOP_A signal 37
An OP permission signal 36 is output. The AND gate 24 causes the clock generation circuit 3 to activate the STOP state.
_B signal 38, and the standby control circuit 5a
STOP_B to compare with STOP_A signal 37
The signal 38 is output.

The STOP signal control circuit 4a includes a watchdog timer 6, an SR flip-flop (hereinafter referred to as SRF / F) 11 for inputting a watchdog timer clear signal 37 output from the CPU 1, and an instruction for each instruction execution. AND gate 21 that inputs an end signal 34 indicating the end timing of the SRF / F11 and the output of the SRF / F11,
, The delay circuit 27 for delaying the signal of the SRF / F12, the end signal 34, the output of the delay circuit 27, and the input of the reset signal 33.
It comprises a DOR gate 22, an AND gate 23 for inputting the output of the SRF / F12 and the STOP order 32, and an SRF / F13 for inputting the output of the AND gate 23.

The STOP permission signal 36 which is the output of the SRF / F 13 is a STOP_ signal output from the standby control circuit 5a.
The signal is input to the AND gate 24 together with the A signal 37.

The standby control circuit 5 、
The function of setting the interrupt request signal 35a to "1" when the signal and the STOP_ # signal 38 do not match is added to the conventional standby control circuit 5b. When the STOP_ # signal 37 matches the STOP_ # signal 38, the standby control circuit 5a keeps the interrupt request signal 35a at "0".

FIGS. 2 and 3 show a watchdog timer clear instruction and ST when there is no program runaway.
FIG. 7 is a timing chart when an OP instruction is executed. FIG.
Is a condition for entering the STOP state when the STOP instruction is executed immediately after the watchdog timer clear instruction is executed. On the other hand, in FIG. 3, an instruction other than the STOP (for example, a NOP instruction) is executed immediately after the watchdog timer clear instruction is executed, and thereafter the STOP is executed.
This is a condition in which the STOP state cannot be entered when the instruction is executed.

In FIGS. 2 and 3, WDT denotes a watchdog timer clear instruction, and STOP denotes a STOP instruction. The execution cycle indicates the execution period of each instruction.

Referring to FIG. 1 and FIG.
The case where the data enters the STOP state will be described. CPU
1 is initialized by a reset signal 33 in advance, and SRF / F11,
The initial values of the outputs 12 and 13 are both "0".
When the watchdog timer clear signal 37 becomes "1", the SRF / F11 is set to "1". Next, the end signal 34 when the watchdog timer clear instruction is executed
Becomes "1", the output of the AND gate 21 becomes "1", and the SRF / F12 is set to "1". SRF / F12
Is delayed by the delay circuit 27 and input to the ANDOR gate 22. When the STOP order 32 becomes “1”, the output of the AND gate 23 becomes “1”.
It becomes "1", and sets the SRF / F13 to "1".
When the end signal 34 becomes “1” during execution of the TOP instruction,
The output of the ANDOR gate 22 becomes "1" and SRF /
F11 and SRF / F12 are reset to "0". STOP
When the _ $ signal 37 becomes "1", the STOP permission signal 36 which is the output of the SRF / F 13 is "1".
The output STOP_B signal 38 of the gate 24 becomes "1", and the clock generation circuit 3 stops generating the system clock 30.

On the other hand, the standby control circuit 5a
_Α signal 37 and STOP_B signal 38 are compared,
In this case, since they match, the STOP request interrupt signal 35a is kept at "0". Therefore, the microcomputer enters the STOP state. When the STOP state is released, the CPU 1 sends the reset signal 33 to the SRF / F 13
Is reset to “0”.

Next, a case where the microcomputer cannot enter the STOP state will be described with reference to FIGS. The CPU 1 initializes in advance with a reset signal 33,
The initial values of the outputs of F / Fs 11, 12, and 13 are all "0"
It is. Watchdog timer clear signal 37
When it becomes "1", the SRF / F11 is set to "1".
Next, when the end signal 34 after executing the watchdog timer clear instruction becomes “1”, the AND gate 21 becomes “1”.
And the SRF / F12 is set to "1". SRF / F1
The output “1” of 2 is delayed by the delay circuit 27 and input to the ANDOR gate 22. When the end signal 34 becomes "1" during execution of the NOP instruction, the output of the ANDOR gate 22 becomes "1", and the SRF / F11 and SRF
/ F12 is reset to "0". STOP order 32
Is "1", the output of the SRF / F12 is "0", so the output of the AND gate 23 is "0",
The STOP permission signal 36 output from the F / F 13 remains "0". Even if the STOP_Α signal 37 becomes “1”, the STOP_B signal 38 which is the output of the AND gate 24
Remains "0".

Accordingly, the clock generation circuit 3 continues to generate the system clock, and the microcomputer
Do not enter the state. On the other hand, the standby control circuit
Since the P_Α signal 37 and the STOP_B signal 38 do not match, the STOP request interrupt signal 35a is set to “1”.
And

Thereafter, the CPU 1 performs an interrupt process on the basis of the interrupt generation signal 31 from the interrupt control circuit 2 on the assumption that the STOP instruction has not been correctly executed.

Next, a second embodiment of the present invention will be described with reference to FIG.

In the first embodiment, the interrupt request signal 3
Although 5a is output from the standby control circuit 5a, in the second embodiment, the interrupt request signal 35b is output from the STOP signal control circuit 4b. The standby control circuit 5b of the second embodiment is the same as the conventional standby control circuit.

On the other hand, the STOP signal control circuit 4b
An inverter 26 for receiving the outputs of the SRF / F 14 and SRF / F 13 for inputting the OP order 32, and an AND gate 25 for receiving the output of the inverter 26 and the output of the SRF / F 14.
And an interrupt generation circuit 15 for inputting the output of the AND gate 25. The interrupt generation circuit 15 outputs the interrupt request signal 35b to the interrupt control circuit 2 with the same function and timing as the interrupt request signal 35a. Other functions are the same as those of the STOP signal control circuit 4a.

Since the timings of the SRF / Fs 11, 12, and 13 are the same as in the first embodiment, only the operation in which the STOP signal control circuit 4b outputs the interrupt request signal 35b will be described. Since the SRF / F 14 is reset to “0” by the reset signal 33 similarly to the SRF / Fs 11, 12, and 13, the initial output value is “0”.

Next, a case where the STOP state is entered will be described with reference to FIG. STOP when executing STOP instruction
When the order 32 becomes "1", the SRF / F 14 is set to "1". Since the STOP permission signal 36 output from the SRF / F 13 is "1", the output of the inverter 25 is "1".
The output of the AND gate 25 to which the output of the SRF / F 14 and the output of the inverter 26 are input becomes "0".
Interrupt generation circuit 15 receiving the output of AND gate 25
Since the STOP permission signal 36 is "1" and the STOP order 32 is "1", the interrupt request signal 35b
Remains "0". The STOP_ $ signal 38 is
Since it is 1 ", the microcomputer enters the STOP state.

Next, a case where the STOP state cannot be set will be described with reference to FIG. ST when executing STOP instruction
When the OP order becomes "1", SRF / F14 becomes SRF / F1.
It is set to "1" at the same timing as 3. SRF / F
Since the STOP permission signal 36, which is the output of 13, is "0", the output of the inverter 25 becomes "1" and the output of the AND gate 24 becomes "1". Interrupt generation circuit 15
Since the STOP permission signal 36 is "0" and the STOP order 32 is "1", the interrupt request signal 35b
Is set to "1". At this time, the STOP_Β signal 38 becomes “
Since it is 0 ", it cannot enter the STOP state.

As in the first embodiment, an interrupt request signal 35
When b becomes "1", the interrupt control circuit 2 sets the interrupt generation signal 31 to "1", and CPUI performs an interrupt process.

[0035]

According to the microcomputer of the present invention, the STOP state is entered only after the watchdog timer clear instruction and the STOP instruction are executed successively. Therefore, the CPU can detect a system abnormality before a STOP instruction that is not expected originally is erroneously executed due to a program runaway or the like. Further, an interrupt process for coping with an abnormality of the system can be performed. Thereby, a microcomputer with high system reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a timing chart when the microcomputer enters a STOP state.

FIG. 3 is a timing chart when the microcomputer cannot enter the STOP state.

FIG. 4 is a block diagram showing a microcomputer according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating an example of a conventional microcomputer.

[Explanation of symbols]

 1; CPU 2: interrupt control circuit 3: clock generation circuit 4: STOP signal control circuit 5a, 5b; standby control circuit 6; watchdog timer 11, 12, 13, 14; SR flip-flop 15; interrupt generation circuit 21, 23 , 24, 25; AND gate 22, ANDOR gate 26; inverter 27, delay circuit 30, system clock 31, interrupt generation signal 32, STOP order 33, reset signal 34, end signal 35a, 35b, interrupt request signal 36, STOP permission Signal 37; STOP_A signal 38; STOP_B signal

Claims (1)

(57) [Claims] 1. A central processing unit, an interrupt control circuit for controlling an interrupt, a clock generation circuit for supplying a system clock to the entire system, a standby control circuit for realizing low power consumption, and a watchdog timer. A memory circuit for storing that a STOP instruction has been executed immediately after an instruction for clearing a count value of a watchdog timer, and means for comparing the level of the content of the storage circuit with a signal for activating a standby state. And a means for requesting an interrupt process when the results of the comparing means match, and when the results of the comparing means do not match.