JP7276755B2 - Processing speed matching circuit and microprocessor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a processing speed matching circuit and a microprocessor, and more particularly to a processing speed matching circuit that maintains program compatibility even when the processing speed of a specific instruction is changed, and a microprocessor equipped with the processing speed matching circuit. .

Japanese Unexamined Patent Application Publication No. 2002-200300 is known as a document that deals with program compatibility. In Patent Document 1, the problem is software compatibility between two CPUs (Central Processing Units) having different execution timings. The logic circuit simulator disclosed in Japanese Patent Laid-Open No. 2003-200010 detects the timing of the delimitation of instruction execution from the execution results of two different simulations, and compares the state values of storage elements such as flip-flops at that point in time. We have confirmed that the two CPUs have software compatibility.

Here, processing in the microprocessor will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of a microprocessor 50 according to a comparative example, and also shows an externally connected storage device 60 together. As shown in FIG. 3, the microprocessor 50 includes an instruction decoder 52 , a wait circuit 54 and an arithmetic processing unit (ALU: Arithmetic Logic Unit) 56 .

Processing by microprocessor 50 is as follows. That is, the instruction decoder 52 outputs the instruction code <1> by designating the address of the storage device 60 where the program is stored (the signal indicated by <5> in FIG. 3, hereinafter <number> notation indicates the signal in the drawing). is called and decoded by the instruction decoder 52 . The decoded instruction code <1> is sent to the arithmetic processing unit 56 as the instruction <2>, is executed by the arithmetic processing unit 56, and the execution result is written in a predetermined storage device.

When the microprocessor 50 accesses the storage device 60, if the data output from the storage device 60 is slower than the processing time of the microprocessor 50, the wait signal <3> is sent from the storage device 60 to make the microprocessor 50 wait. is sent to the wait circuit 54 . The wait circuit 54, which has received the wait signal <3>, sends a wait control signal <4> to the instruction decoder 52 in order to wait the execution of the process for a predetermined time.

JP-A-10-187790

By the way, as is common to semiconductor devices in general, in the technical field of microprocessors in particular, new models are being developed on a daily basis for the purpose of improving processing capabilities. For example, a microprocessor originally developed as an 8-bit model may be upgraded to a 16-bit model with improved processing capability. In that case, instruction compatibility is often provided so that a program developed for an 8-bit microprocessor can be used as much as possible (so that programs can be inherited). At the same time, a microcomputer equipped with a 16-bit compatible microprocessor with improved processing capacity (hereinafter referred to as "16-bit microcomputer") was replaced with a microcomputer equipped with an 8-bit compatible microprocessor (hereinafter referred to as "8-bit microcomputer"). ) was developed as a high-end model.

However, if a user who adopted an 8-bit microcomputer before the development of a 16-bit microcomputer replaces it with a 16-bit microcomputer with improved processing capability, problems may arise in program inheritance. For example, in a program developed by a user with an 8-bit microcomputer, a certain program routine is constructed in anticipation of the instruction processing time of an 8-bit compatible microprocessor, and after the instruction processing time has elapsed, the next program routine is entered. This is the case when a routine that is In other words, the problem is that malfunctions occur due to shortening of the transition time from one program routine to the next due to the improved processing capability.

If the above problem occurs, even if the instructions of an 8-bit microcomputer and a 16-bit microcomputer are compatible, when a program developed with an 8-bit microcomputer is used with a 16-bit microcomputer, the program cannot be used without modification. is not possible, it becomes necessary to modify existing programs. As a result, it takes time to replace the microcomputer.

In this respect, Patent Document 1 does not address the issue of the instruction processing time itself.

The present invention has been made to solve the above-described problems, and suppresses the occurrence of program malfunction even when using a program containing instruction codes whose processing speed does not match the processing speed of an arithmetic processing unit. It is an object of the present invention to provide an improved processing speed matching circuit and microprocessor.

The processing speed matching circuit according to the present invention acquires an instruction code included in the program from a storage device storing a program for operating the arithmetic processing unit, and calculates the time required to process the instruction code and the arithmetic processing unit. and a detection unit that detects a specific instruction code that is predicted to cause a mismatch between the processing speed of the and a standby unit that waits for the start of execution of the specific instruction code.

A microprocessor according to the present invention includes an arithmetic processing unit that executes processing based on a program, and the processing speed matching circuit described above.

According to the present invention, there are provided a processing speed matching circuit and a microprocessor that suppress the occurrence of program malfunction even when using a program containing instruction codes whose processing speed does not match the processing speed of an arithmetic processing unit. It has the effect of being able to

1 is a block diagram showing an example of a configuration of a microprocessor according to a first embodiment; FIG. FIG. 11 is a block diagram showing an example of a configuration of a microprocessor according to a second embodiment; FIG. 3 is a block diagram showing the configuration of a microprocessor according to a comparative example; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description, the circuit configuration of a microprocessor that reads and executes instructions from an external storage device will be exemplified.

[First embodiment]
The configuration of microprocessor 10 according to the present embodiment will be described with reference to FIG. FIG. 1 also shows a storage device 30 attached to the microprocessor 10 and storing programs and the like used by the microprocessor 10 . Although the type of storage device 30 is not particularly limited, it is a non-volatile memory in this embodiment. As shown in FIG. 1, the microprocessor 10 includes a specific instruction detection circuit (processing capability) 12, an instruction decoder 14, a wait circuit 16, an arithmetic processing unit (ALU) 20, and an OR circuit 18. Although the type of microprocessor 10 is not particularly limited, it is a 16-bit microprocessor in this embodiment. Here, "16-bit compatible" means that the bit width of the arithmetic processing unit 20 is 16 bits. The specific command detection circuit (processing capability) 12 and the wait circuit 16 shown in FIG. 1 constitute a "processing speed matching circuit" according to the present invention.

The arithmetic processing unit 20 is a device that executes processing based on input commands and outputs execution results.

The instruction decoder 14 calls the instruction code <1> of the program stored in the storage device 30 by designating the address <8> of the storage device 30 and decodes it. The decoded instruction <7> is sent to the arithmetic processing unit 20 that executes the instruction <7>, is executed by the arithmetic processing unit 20, and the execution result is written in a storage device or the like (not shown). The decoded instruction <2> is also sent to the specific instruction detection circuit (processing capability) 12 at the same time.

The wait circuit 16 waits the processing by the microprocessor 10 when the data output from the external device is slower than the processing time of the microprocessor 10 when the microprocessor 10 accesses an external device such as the storage device 30. is the circuit of Waiting for processing by the microprocessor 10 is executed based on the wait signal <4> sent from the storage device 30 . The wait circuit 16 sends a wait control signal <6> to the instruction decoder 14 when waiting for processing.

A specific instruction detection circuit (processing capability) 12 detects a predetermined instruction from among the instructions <2> decoded by the instruction decoder 14, and waits for a detection signal <3> containing information indicating the detection. Send to 16. At this time, the detection signal <3> is logically summed with the weight signal <4> by the OR circuit 18, and the result is input to the weight circuit 16 as the weight input signal <5>. An enable signal <9> for selecting whether the specific command detection circuit (processing capability) 12 is operated or not (operating or non-operating) is input to the specific command detecting circuit (processing capability) 12 via an external terminal 32. It is Therefore, it is possible to stop the operation of the specific command detection circuit (processing capability) 12 by the enable signal <9> when necessary.

Here, a specific command detected by the specific command detection circuit (processing capability) 12 will be described.
A specific instruction according to the present embodiment refers to an instruction for which the processing speed of the arithmetic processing unit 20 and the processing speed do not match for some reason. There are no particular restrictions on the cause of the inconsistency in the processing speed with the arithmetic processing unit 20, but in the present embodiment, the response speed of the object controlled by the microprocessor 10 (controlled object) is slow, and in normal processing of the microprocessor 10 Refers to an instruction that may cause a malfunction. There are various possible causes for the slow response speed of the object to be controlled. In addition, it refers to an instruction with a slow relative response speed. In other words, the specific instruction is an instruction that is originally compatible with the old specification microprocessor, but is no longer compatible under predetermined operating conditions due to the improvement in the processing speed of the microprocessor 10 .

A specific example of occurrence of inconsistency in response speed as described above is when a program developed by a user with an 8-bit microcomputer is run on a high-end 16-bit microcomputer, and a certain program routine is 8-bit compatible. This is the case where the program is designed in anticipation of the instruction processing time of the microprocessor (hereinafter referred to as "specific instruction processing time"), and the program proceeds to the next program routine. In this case, it is assumed that the processing speed of the 16-bit microcomputer has increased, and the specific instruction processing time will also be shortened.

Then, it is conceivable that the next program routine may be started before the specific instruction processing time elapses, and in this case, malfunction may occur in the processing of the program.
An example of a command including such a specific command processing time is a data transfer command. In the case of a transfer instruction, if the processing speed is increased (for example, doubled) by upgrading the microprocessor from 8-bit support to 16-bit support, the next program routine will be shifted to before the transfer is completed. It is also assumed that it will be lost.

Therefore, in the present embodiment, the microprocessor 10 is intended to perform processing using instructions (specific instructions) with higher processing capabilities than the microprocessor before the version upgrade of the microprocessor 10 (hereinafter referred to as the "old microprocessor"). In order to match the processing speed of the microprocessor 10 for specific instructions with the processing speed of the old microprocessor. As a result, since the instruction execution timings of originally compatible instructions become the same, it is possible to replace the old microprocessor with the microprocessor 10 without changing the program developed for the old microprocessor. In addition, since the microprocessor 10 has an input section for an enable signal <9> to be input to the specific command detection circuit (processing capability) 12, the specific command is not used in the program of the microprocessor 10. When it is known, the operation of the specific command detection circuit (processing capability) 12 can be stopped and the original processing capability of the microprocessor 10 can be exhibited.

The operation of the microprocessor 10 will be described more specifically with reference to FIG. In the following, it is assumed that the enable signal <9> is active and the specific command detection circuit (processing capability) 12 is in an operating state. When the specific instruction detection circuit (processing capability) 12 receives the instruction <2> from the instruction decoder 14, it determines whether the received instruction <2> corresponds to the specific instruction. In the present embodiment, instructions corresponding to specific instructions are known in advance, and are stored, for example, in a storage unit (not shown). A specific command detection circuit (processing capability) 12 collates the received command <2> with specific commands stored in the storage unit, and if it determines that it corresponds to the specific command, issues a detection signal <3>.

The detection signal <3> is input to the wait circuit 16 as a wait input, and the wait circuit 16 that has received the wait input sends a wait control signal <6> to the instruction decoder 14 to wait the processing of the specific instruction for a predetermined time. . Specifically, the time corresponding to the difference between the processing time of the old microprocessor and the processing time (specific instruction processing time) of the microprocessor 10 with improved processing capability (hereinafter referred to as "waiting time") is the detection signal. Activate <3>. Wait time may be counted in the number of clocks used by microprocessor 10 . That is, the waiting time may be defined by the number of clocks.

The detection signal <3> is logically summed with the weight signal <4> by the OR circuit 18, and is input to the weight circuit 16 as the weight input signal <5>. The wait circuit 16 to which the wait input signal <5> is input sends a wait control signal <6> to the instruction decoder 14 to wait the execution of the specific instruction for a predetermined time. Therefore, execution of the specific instruction is waited for at least the wait time regardless of the state of the wait signal <4>.

As described in detail above, according to the microprocessor 10 according to the present embodiment, execution of a specific instruction is made to wait for a predetermined waiting time. It becomes possible to As a result, it becomes possible to replace the old microprocessor with the microprocessor 10 by using the program of the old microprocessor as it is without changing it. In addition, since the existing wait circuit 16 is used in this embodiment, there is an effect of reducing the circuit size.

[Second embodiment]
A microprocessor 10A according to the present embodiment will be described with reference to FIG. This embodiment is obtained by modifying the specific instruction detection circuit (processing capacity) 12 according to the above embodiment. Accordingly, components similar to those of the microprocessor 10 are denoted by the same reference numerals, and detailed description thereof is omitted. The specific instruction detection circuit (execution timing margin) 12A and the wait circuit 16 shown in FIG. 2 constitute a "processing speed matching circuit" according to the present invention.

As shown in FIG. 2, the microprocessor 10A replaces the specific instruction detection circuit (processing capability) 12 of the microprocessor 10 with a specific instruction detection circuit (execution timing margin) 12A. The specific instruction detection circuit (execution timing margin) 12A is a circuit that detects an instruction without a timing margin (specific instruction) among the instructions related to the microprocessor 10 . An instruction without a timing margin is an instruction whose execution timing is critical for some reason. For example, it is an instruction that has a large delay time because it is configured to pass through a delay circuit with a long delay time or an arithmetic processing unit, and has a low tolerance for deviation in execution timing.

If a program executed by a microprocessor contains a specific instruction without a timing margin as described above, the timing of the specific instruction becomes a bottleneck, and it may not be possible to increase the frequency of the clock that serves as a reference for the operation of the microprocessor. be. Therefore, in the microprocessor 10A according to the present embodiment, execution of such a specific instruction is made to wait for a predetermined time.

When the enable signal <9> is activated and the specific instruction detection circuit (execution timing margin) 12A is in an operating state, the specific instruction detection circuit (execution timing margin) 12A according to the present embodiment operates to Detects an instruction that does not exist as a specific instruction. Specific commands according to the present embodiment are also listed up in advance and stored in a storage unit (not shown). A specific instruction detection circuit (execution timing margin) 12A compares the instruction <2> received from the instruction decoder 14 with a predetermined specific instruction. Issue signal <3>. After that, execution of the specific instruction is waited for a predetermined number of clocks based on the procedure described in the above embodiment.

As described above, according to the microprocessor 10A according to the present embodiment, when an instruction without a timing margin is detected, the wait circuit 16 waits the execution of the instruction for a predetermined time. The bottleneck caused by increasing the frequency is eliminated, and the upper limit of the operating clock frequency can be set high. Further, since the microprocessor 10A has an input section for an enable signal <9> input to the specific instruction detection circuit (execution timing margin) 12A, it is possible to detect that the specific instruction is not used in the program of the microprocessor 10A. If it is known in advance, the operation of the specific instruction detection circuit (execution timing margin) 12A can be stopped and the original processing capability of the microprocessor 10A can be exhibited.

10 Microprocessor 12 Specific instruction detection circuit (processing capacity)
12A Specific instruction detection circuit (execution timing margin)
14 instruction decoder 16 wait circuit 18 OR circuit 20 arithmetic processing unit 30 storage device 32 external terminal 50 microprocessor 52 instruction decoder 54 wait circuit 56 arithmetic processing unit 60 storage device

Claims (5)

Based on the instruction code included in the program stored in the storage device storing the program for operating the arithmetic processing unit, there is a mismatch between the time required to process the instruction code and the processing speed of the arithmetic processing unit. a detection unit that detects a specific instruction code that is predicted to occur;
A standby signal from the storage device or a detection signal issued by the detection unit when the detection unit detects the specific instruction code is input, and the OR of the detection signal and the standby signal is calculated. a logical sum circuit that outputs the result;
a standby unit that waits the start of execution of the specific instruction code for a period of time corresponding to the mismatch based on the signal output from the OR circuit;
a decoding unit that decodes the instruction code and sends the decoded first command to the detection unit;
including
The waiting unit sends a waiting signal to the decoding unit for waiting the start of execution of the specific instruction code for the time corresponding to the mismatch,
The decoding unit sends out a second command to operate the arithmetic processing unit based on the standby signal,
The detection unit can be switched between operation and non-operation by a switching signal from the outside.
Processing speed matching circuit. The inconsistency is caused by the improvement of the operation speed of the arithmetic processing unit and the program being the same program as the program before the improvement of the operation speed,
2. The processing speed matching circuit according to claim 1, wherein the time corresponding to the mismatch is the difference in processing speed between before and after the operating speed of the arithmetic processing unit for the specific instruction code is increased. The inconsistency is caused by a small timing margin of the specific instruction code,
2. The processing speed matching circuit according to claim 1, wherein the time corresponding to said mismatch is a time predetermined for each of said specific instruction codes. an arithmetic processing unit that executes processing based on a program;
A processing speed matching circuit according to any one of claims 1 to 3 ;
including a microprocessor. further including a clock source that serves as a temporal reference for processing;
5. The microprocessor according to claim 4 , wherein the time corresponding to said mismatch is defined by the number of clocks of said clock source.

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