JP2022033968A - Processing speed matching circuit and microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing speed matching circuit and a microprocessor in which occurrence of malfunction of a program is suppressed even when the program including an instruction code of which processing speed is not consistent with processing speed of an arithmetic processing part is used.

SOLUTION: The present invention comprises a detection part 12 acquiring an instruction code<1>included in a program from a storage device 30 storing the program for operating an arithmetic processing part 20, and detecting a specific instruction code to be predicted that mismatch occurs between the time required for processing the instruction code<1>and the processing speed of the arithmetic processing part 20, and a waiting part 16 making execution start of the specific instruction code wait only for the time corresponding to the mismatch if the specific instruction code is detected in the detection part 12.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a processing speed matching circuit and a microprocessor, particularly a processing speed matching circuit that maintains program compatibility even when the processing speed of a specific instruction is changed, and a microprocessor provided with the processing speed matching circuit. ..

Conventionally, Patent Document 1 is known as a document having a problem of program compatibility. Patent Document 1 has a problem of software compatibility between two CPUs (Central Processing Units) having different execution timings. In the logic circuit simulator disclosed in Patent Document 1, the timing of instruction execution delimiter is detected from the execution results of two different simulations, and the state values of storage elements such as flip-flops at that time are compared. We have confirmed that one CPU has software compatibility.

Here, the processing in the microprocessor will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the microprocessor 50 according to the comparative example, and also illustrates the storage device 60 connected to the outside. As shown in FIG. 3, the microprocessor 50 includes an instruction decoder 52, a weight circuit 54, and an arithmetic processing unit (ALU) 56.

The processing by the microprocessor 50 is performed as follows. That is, the instruction decoder 52 specifies the address of the storage device 60 in which the program is stored (the signal indicated by <5> in FIG. 3, and the notation of <number> below indicates the signal in the figure), and the instruction decoder 52 indicates the instruction code <1>. Is called, and the instruction decoder 52 decodes it. The decoded instruction code <1> is sent to the arithmetic processing unit 56 as an instruction <2>, executed by the arithmetic processing unit 56, and the execution result is written in a predetermined storage device.

When the microprocessor 50 accesses the storage device 60, if the data output from the storage device 60 is slower than the processing time of the microprocessor 50, the weight signal <3> from the storage device 60 in order to make the microprocessor 50 stand by. Is sent to the weight circuit 54. The weight circuit 54 that has received the weight signal <3> sends a weight control signal <4> to the instruction decoder 52 in order to make the execution of the process wait (stand by) for a predetermined time.

Japanese Unexamined Patent Publication No. 10-187790

By the way, although it is common to semiconductor devices in general, especially in the technical field of microprocessors, new models are being developed every day for the purpose of improving processing capacity and the like. For example, a microprocessor originally developed as a model corresponding to 8 bits may be made a model corresponding to 16 bits having an upgraded version and improved processing capacity. In that case, the program developed for the microprocessor corresponding to 8 bits is often made instruction compatible so that it can be used as much as possible (so that the program can be inherited). At the same time, a microcomputer equipped with a 16-bit compatible microprocessor with improved processing capacity (hereinafter, "16-bit microcomputer") is replaced by a microcomputer equipped with an 8-bit compatible microprocessor (hereinafter, "8-bit microcomputer"). ) Will be developed as a high-end model.

However, if a user who adopted an 8-bit microcomputer before the development of a 16-bit microcomputer replaces it with a 16-bit microcomputer with improved processing capacity, a problem may occur in inheritance of the program. For example, in a program developed by a user with an 8-bit microcomputer, a certain program routine is assembled in anticipation of the instruction processing time of an 8-bit compatible microprocessor, and after the instruction processing time elapses, the program routine is further transferred to the next program routine. Routine was set up. That is, there is a problem that a malfunction occurs because the transition time from one program routine to the next program routine is shortened due to the improvement in processing capacity.

When the above problem occurs, even if the 8-bit microcomputer and the 16-bit microcomputer are instruction-compatible, when the program developed by the 8-bit microcomputer is used by the 16-bit microcomputer, the program should be used as it is without being changed. Therefore, it becomes necessary to modify the existing program. As a result, it takes time to replace the microcomputer.

In this respect, Patent Document 1 is not a document in which the processing time of an instruction itself is a problem.

The present invention has been made to solve the above-mentioned problems, and even when a program including an instruction code whose processing speed does not match the processing speed of the arithmetic processing unit is used, the occurrence of program malfunction is suppressed. It is an object of the present invention to provide a processed speed matching circuit and a microprocessor.

The processing speed matching circuit according to the present invention acquires an instruction code included in the program from a storage device in which a program for operating the arithmetic processing unit is stored, and the time required for processing the instruction code and the arithmetic processing unit. A detection unit that detects a specific instruction code that is predicted to cause an inconsistency with the processing speed of the above, and a detection unit that detects the specific instruction code, for the time corresponding to the inconsistency. It includes a standby unit that waits for the start of execution of a specific instruction code.

The microprocessor according to the present invention includes an arithmetic processing unit that executes processing based on a program, and the above-mentioned processing speed matching circuit.

According to the present invention, there is provided a processing speed matching circuit and a microprocessor in which the occurrence of program malfunction is suppressed even when a program including an instruction code whose processing speed does not match the processing speed of the arithmetic processing unit is used. It has the effect of being able to do it.

It is a block diagram which shows an example of the structure of the microprocessor which concerns on 1st Embodiment. It is a block diagram which shows an example of the structure of the microprocessor which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the microprocessor which concerns on a comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description, a circuit configuration of a microprocessor that reads and executes instructions from an external storage device will be illustrated and described.

[First Embodiment]
The configuration of the microprocessor 10 according to the present embodiment will be described with reference to FIG. 1. FIG. 1 also shows a storage device 30 attached to the microprocessor 10 and in which a program or the like used in the microprocessor 10 is stored. The type of the storage device 30 is not particularly limited, but in the present embodiment, it is a non-volatile memory. As shown in FIG. 1, the microprocessor 10 includes a specific instruction detection circuit (processing capacity) 12, an instruction decoder 14, a weight circuit 16, an arithmetic processing unit (ALU) 20, and an OR circuit 18. The type of the microprocessor 10 is not particularly limited, but in the present embodiment, it is a microprocessor compatible with 16 bits. The term "16-bit compatible" as used herein means that the bit width of the arithmetic processing unit 20 is 16 bits. The specific command detection circuit (processing capacity) 12 and the weight circuit 16 shown in FIG. 1 constitute a "processing speed matching circuit" according to the present invention.

The arithmetic processing unit 20 is a device that executes processing based on an input instruction and outputs an execution result.

The instruction decoder 14 calls and decodes the instruction code <1> of the program stored in the storage device 30 by designating the address <8> of the storage device 30. The decoded instruction <7> is sent to the arithmetic processing unit 20 that executes the instruction <7>, is executed by the arithmetic processing unit 20, and the execution result is written in a storage device (not shown) or the like. Further, the decoded instruction <2> is also sent to the specific instruction detection circuit (processing capacity) 12 at the same time.

The weight circuit 16 waits for processing by the microprocessor 10 when the data output from the external device is slower than the processing time of the microprocessor 10 when the microprocessor 10 accesses an external device such as the storage device 30. It is a circuit of. The standby for processing by the microprocessor 10 is executed based on the weight signal <4> sent from the storage device 30. The weight circuit 16 sends a weight control signal <6> to the instruction decoder 14 when the process is made to stand by.

The specific instruction detection circuit (processing capacity) 12 detects a predetermined instruction from the instructions <2> decoded by the instruction decoder 14, and waits for a detection signal <3> including the detected information. Send to 16. At this time, the detection signal <3> is ORed with the weight signal <4> by the OR circuit 18, and the result is input to the weight circuit 16 as the weight input signal <5>. An enable signal <9> for selecting whether to operate or not operate the specific command detection circuit (processing capacity) 12 (operation or non-operation) is input to the specific command detection circuit (processing capacity) 12 via the external terminal 32. Has been done. Therefore, if necessary, the operation of the specific command detection circuit (processing capacity) 12 can be stopped by the enable signal <9>.

Here, the specific instruction detected by the specific instruction detection circuit (processing capacity) 12 will be described.
The specific instruction according to the present embodiment means an instruction in which the processing speed and the processing speed of the arithmetic processing unit 20 do not match for some reason. There is no particular limitation on the cause of the inconsistency in the processing speed with the arithmetic processing unit 20, but in the present embodiment, the response speed of the target (controlled target) controlled by the microprocessor 10 is slow, and in the processing of the normal microprocessor 10. An instruction that may cause a malfunction. There are various possible causes for the slow response speed of the controlled object, but in this embodiment, the microprocessor 10 has been upgraded from the microprocessor of the old specification (for example, an 8-bit compatible microprocessor) to improve the processing capacity. In addition, it means an instruction whose relative response speed has become slower. That is, the specific instruction is an instruction that is originally compatible with the microprocessor of the old specification, but is an instruction that is no longer compatible under predetermined operating conditions due to the improvement in the processing speed of the microprocessor 10.

As a specific example of the occurrence of inconsistency in the response speed as described above, as described above, when a program developed by a user with an 8-bit microcomputer is operated by a 16-bit microcomputer which is a higher-end model, a certain program routine supports 8-bit. This is a case where the program is constructed in anticipation of the instruction processing time (hereinafter, "specific instruction processing time") of the microprocessor of the above, and further shifts to the next program routine. In this case, it is assumed that the specific instruction processing time is shortened due to the faster processing speed of the 16-bit microcomputer.

Then, it is assumed that the program moves to the next program routine before the specific instruction processing time elapses. In this case, a malfunction may occur in the program processing.
Examples of the instruction including such a specific instruction processing time include a data transfer instruction. In the case of a transfer instruction, if the processing speed becomes faster (for example, doubled) due to the upgrade of the microprocessor from 8-bit support to 16-bit support, the program shifts to the next program routine before the transfer is completed. It is also expected that it will end up.

Therefore, in the present embodiment, in the microprocessor 10, it is intended to process by an instruction (specific instruction) having a higher processing capacity than the microprocessor (hereinafter, "old microprocessor") before the version upgrade of the microprocessor 10. The processing speed of the microprocessor 10 for a specific instruction is matched with the processing speed of the old microprocessor. As a result, the instruction execution timings of the originally compatible instructions are also the same, so that the old microprocessor can be replaced with the microprocessor 10 without changing the program developed for the old microprocessor. Further, since the microprocessor 10 includes an input unit of the enable signal <9> input to the specific instruction detection circuit (processing capacity) 12, it is necessary in advance that the specific instruction is not used in the program of the microprocessor 10. If it is known, the operation of the specific instruction detection circuit (processing capacity) 12 can be stopped, and the original processing capacity of the microprocessor 10 can be exerted.

The operation of the microprocessor 10 will be described more specifically with reference to FIG. In the following, it is assumed that the enable signal <9> is activated and the specific command detection circuit (processing capacity) 12 is in the operating state. When the specific instruction detection circuit (processing capacity) 12 receives the instruction <2> from the instruction decoder 14, it determines whether or not the received instruction <2> corresponds to the specific instruction. In the present embodiment, the instruction corresponding to the specific instruction is known in advance, and is stored in, for example, a storage unit (not shown). The specific instruction detection circuit (processing capacity) 12 collates the received instruction <2> with the specific instruction stored in the storage unit, and issues a detection signal <3> when it is determined that the specific instruction corresponds to the specific instruction.

The detection signal <3> is input to the weight circuit 16 as a weight input, and the weight circuit 16 that receives the weight input sends the weight control signal <6> to the instruction decoder 14 to wait for the processing of the specific instruction for a predetermined time. .. Specifically, the detection signal is only the time corresponding to the difference time (hereinafter, "standby time") between the processing time of the old microprocessor and the processing time (specific instruction processing time) of the microprocessor 10 with improved processing capacity. Activate <3>. The standby time may be counted by the number of clocks used in the microprocessor 10. That is, the standby time may be specified by the number of clocks.

The detection signal <3> is ORed with the weight signal <4> in the OR circuit 18 and is input to the weight circuit 16 as a weight input signal <5>. The weight circuit 16 to which the weight input signal <5> is input sends a weight control signal <6> that makes the execution of the specific instruction wait for a predetermined time to the instruction decoder 14. Therefore, regardless of the state of the weight signal <4>, the execution of the specific instruction is waited for at least the waiting time.

As described in detail above, according to the microprocessor 10 according to the present embodiment, since the execution of a specific instruction is made to wait for a predetermined waiting time, the instruction compatibility with the old microprocessor including the timing of instruction execution is achieved. It becomes possible to do. As a result, the replacement of the old microprocessor with 10 can be performed by using the program of the old microprocessor as it is without changing the program. Further, since the existing weight circuit 16 is used in this embodiment, there is also an effect of reducing the circuit scale.

[Second Embodiment]
The microprocessor 10A according to the present embodiment will be described with reference to FIG. This embodiment is a modification of the specific command detection circuit (processing capacity) 12 according to the above embodiment. Therefore, the same components as those of the microprocessor 10 are designated by the same reference numerals, and detailed description thereof will be omitted. The specific command detection circuit (execution timing margin) 12A and the weight circuit 16 shown in FIG. 2 constitute the "processing speed matching circuit" according to the present invention.

As shown in FIG. 2, in the microprocessor 10A, the specific instruction detection circuit (processing capacity) 12 of the microprocessor 10 is replaced with the specific instruction detection circuit (execution timing margin) 12A. The specific instruction detection circuit (execution timing margin) 12A is a circuit that detects an instruction (specific instruction) having no timing margin among the instructions related to the microprocessor 10. An instruction without a timing margin is an instruction whose execution timing is critical for some reason. For example, it is an instruction that has a large delay time because it is configured to pass through a delay circuit having a large delay time or an arithmetic processing unit, and has a low tolerance for a deviation in execution timing.

If a specific instruction without a timing margin as described above exists in a program executed by a microprocessor, the timing of the specific instruction becomes a bottleneck, and it may not be possible to increase the frequency of the clock that is the reference for the operation of the microprocessor. be. Therefore, in the microprocessor 10A according to the present embodiment, the microprocessor 10A is made to wait for a predetermined time in the execution of such a specific instruction.

When the enable signal <9> is activated and the specific instruction detection circuit (execution timing margin) 12A is in the operating state, the specific instruction detection circuit (execution timing margin) 12A according to the present embodiment has the above timing margin. Detects non-existent instructions as specific instructions. Specific instructions according to this embodiment are also listed in advance and stored in a storage unit (not shown). The specific instruction detection circuit (execution timing margin) 12A compares the instruction <2> received from the instruction decoder 14 with a predetermined specific instruction, and when the specific instruction is detected, it detects only the time for the predetermined number of clocks. It emits a signal <3>. After that, based on the procedure described in the above embodiment, the execution of the specific instruction is waited for a predetermined number of clocks.

As described above, according to the microprocessor 10A according to the present embodiment, when an instruction having no timing margin is detected, the weight circuit 16 waits for the execution of the instruction for a predetermined time. The bottleneck when the frequency is increased is eliminated, and the upper limit of the operating clock frequency can be set high. Further, since the microprocessor 10A includes an input unit of the enable signal <9> input to the specific instruction detection circuit (execution timing margin) 12A, the specific instruction is not used in the program of the microprocessor 10A. If it is known in advance, the operation of the specific instruction detection circuit (execution timing margin) 12A can be stopped, and the original processing capacity of the microprocessor 10A can be exhibited.

10 Microprocessor 12 Specific instruction detection circuit (processing capacity)
12A Specific instruction detection circuit (execution timing margin)
14 instruction decoder 16 weight circuit 18 OR circuit 20 arithmetic processing unit 30 storage device 32 external terminal 50 microprocessor 52 instruction decoder 54 weight circuit 56 arithmetic processing unit 60 storage device

Claims (7)

There is an inconsistency between the time required to process the instruction code and the processing speed of the arithmetic processing unit based on the instruction code included in the program from the storage device in which the program for operating the arithmetic processing unit is stored. A detector that detects a specific instruction code that is expected to occur,
A standby signal from the storage device or a detection signal issued by the detection unit when the detection unit detects the specific command code is input, and the logical sum of the detection signal and the standby signal is calculated and calculated. The OR circuit that outputs the result and
A standby unit that waits for the start of execution of the specific instruction code for a time corresponding to the inconsistency based on the signal output from the OR circuit.
Processing speed matching circuit including. Further including a decoding unit that decodes the instruction code and sends the decoded instruction to the detection unit.
The processing speed matching circuit according to claim 1, wherein the standby unit sends a signal for waiting for the start of execution of the specific instruction code to the decoding unit for a time corresponding to the inconsistency. The inconsistency is caused by the improvement of the operating speed of the arithmetic processing unit and the fact that the program is the same program as the program before the improvement of the operating speed.
The processing speed matching circuit according to claim 1 or 2, wherein the time corresponding to the inconsistency is the difference in processing speed before and after the improvement of the operating speed of the arithmetic processing unit of the specific instruction code. The inconsistency is caused by a small timing margin of the specific instruction code.
The processing speed matching circuit according to claim 1 or 2, wherein the time corresponding to the inconsistency is a predetermined time for each specific instruction code. The processing speed matching circuit according to any one of claims 1 to 4, wherein the detection unit can be switched between operation and non-operation by a switching signal from the outside. An arithmetic processing unit that executes processing based on a program,
The processing speed matching circuit according to any one of claims 1 to 5.
Microprocessor including. It also includes a clock source that serves as a time reference for processing.
The microprocessor according to claim 6, wherein the time corresponding to the inconsistency is defined by the number of clocks of the clock source.

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