JP7069870B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing device having a built-in microprocessor such as an embedded device, and in particular, information processing capable of changing the priority of a plurality of interrupt handlers activated by an interrupt signal generated outside or inside the microprocessor. It is about the device.

Generally, in an embedded device having a built-in microprocessor (hereinafter referred to as "MPU"), when an interrupt signal is generated outside or inside the MPU, the developer of the software program of the embedded device (hereinafter, simply referred to as "developer"). The interrupt handler corresponding to each interrupt signal is executed with the priority set by.). This interrupt signal may occur when a certain event (event) occurs, but it may also occur periodically such as a timer interrupt. A plurality of interrupts may occur at the same time. In this case, the interrupt handler is executed in descending order of priority based on the priority preset for each interrupt signal by the developer.

Appropriately designing the interrupt signal to be used and the priority of interrupts is especially important for embedded devices that require real-time performance, but the current situation is that these designs rely largely on experience and intuition. In particular, in order to determine the priority when a plurality of interrupts occur at the same time, it is necessary to understand the entire function of the embedded device and the operation and specifications of the MPU, which is difficult.

Changing the priority while checking the behavior of the program by executing the software program on a trial basis is effective for reducing the difficulty of designing the priority, and for switching the priority of the interrupt handler from the past. Technology has been proposed. (See, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-127039

In the technique described in Patent Document 1, in order to prevent a task having a high priority from being waited for a long time, the MPU gives priority to the task when accessing the shared resource based on the access time zone for the shared resource preset by the developer. The degree is changed dynamically.

However, Patent Document 1 is a technique of changing the priority of a task based on the time zone when an event-like access to a shared resource specified by a user occurs, and the periodic interrupt cycle is as desired. It cannot be applied to the priority change to make it.

The present invention has been made in view of the above circumstances, and by dynamically changing the priority of a plurality of fixed-period interrupts based on the execution status of each interrupt handler, each interrupt priority is appropriately set. The purpose is to provide an information processing device that can be set to.

In order to achieve the above object, the information processing apparatus of the present invention is mainly characterized by the following points.
1. 1. The interrupt handler for which the interrupt priority is dynamically changed is determined in advance, and the information processing device determines the allowable conditions including the ratio of the allowable excess time of the original execution cycle and the allowable excess number of times from the original execution cycle in the interrupt handler. Set to.
2. 2. When the interrupt handler is executed, the conditional branch and execution process in the interrupt handler are detected, and the interrupt handler is executed under the condition that the execution time is maximized.
3. 3. During the execution of the program, the priority setting means configured by the program detects the existence of an interrupt handler that does not satisfy the allowable condition and raises the priority of the interrupt handler.
4. The priority setting means outputs an alarm in a format recognizable by the developer when there is an interrupt handler that does not satisfy the allowable condition even if the priority is set to the highest.

Specifically, the information processing device according to the present invention is an information processing device that sets the interrupt priority of an interrupt handler executed corresponding to each of a plurality of fixed-period interrupt signals.
A timer that measures the activation interval of each interrupt handler,
A means for preserving the allowable condition for the deviation between the activation interval and the original cycle,
For each interrupt handler, it is determined whether or not the permissible condition is deviated, and if it deviates, a priority setting means for raising the interrupt priority of the interrupt handler is used.
It is characterized by being equipped with.

Preferably, this permissible condition is determined by whether or not the difference between the preset original activation cycle of each interrupt handler and the value of the timer exceeds the threshold value, or the number of times the difference exceeds the threshold value. It is good to be determined based on this.

In the present invention, an interrupt handler that is not executed at a cycle according to the specification is detected, and the interrupt priority of the interrupt handler is changed so that the priority of all interrupt handlers is adjusted to be optimum.

More preferably, the interrupt priority for each interrupt handler is saved, all managed interrupt handlers are set to the lowest priority in the initial state (at the time of system reset), and the priority setting means is an interrupt. When the handler deviates from the permissible condition, it is preferable to raise the interrupt priority of the interrupt handler.

By doing so, the priority of the interrupt handler that deviates from the permissible condition is automatically increased, so that the interrupt priority of the entire system can be automatically adjusted. It should be noted that this adjustment may be performed at the time of system development, and the interrupt priority after adjustment may be fixedly set, or the adjustment may be performed at all times including during system operation.

Further, the information processing apparatus according to the present invention is
An instruction reading means that detects a conditional branch instruction in the program code for each interrupt handler and replaces the conditional branch instruction with a preset instruction other than a no-operation instruction or other conditional branch instructions.
After the interrupt handler is executed, the instruction replacement canceling means for returning the instruction replaced by the instruction reading means back to the original conditional branch instruction,
It is characterized by being equipped with.

In the present invention, if a conditional branch instruction such as an if statement or while statement exists in the program code (machine language) of the interrupt handler, it is not a conditional branch instruction such as NOP (no operation instruction). Replace with a predetermined instruction. By executing the interrupt handler in this state, it is possible to pass a critical path that affects the fixed cycle operation. It is preferable to perform such instruction replacement processing during system development.

In addition, if the interrupt priority of the interrupt handler rises to a predetermined priority and still deviates from the permissible conditions, an alarm is output, which may affect the fixed cycle operation of the entire system. It is possible to recognize a high interrupt handler in advance.

According to the present invention, it is possible to automatically set an appropriate interrupt priority of an interrupt handler that operates with a fixed-period interrupt, so that it is possible to reduce the difficulty of designing the interrupt priority.

It is a functional block diagram of the embedded device by 1st Embodiment of this invention. It is a data structure example of the time measurement result storage table of FIG. It is a flowchart which shows the processing procedure of the priority setting means of FIG. It is explanatory drawing of the specific example of the process of step S102 of FIG. It is a functional block diagram of the embedded device by the 2nd Embodiment of this invention. It is a data structure example of the time measurement result storage table of FIG. It is a flowchart which shows the processing procedure of the priority setting means of FIG. It is a flowchart which shows the processing procedure of the instruction reading means of FIG. It is a flowchart which shows the processing procedure of the instruction replacement canceling means of FIG. It is a data structure example of the conditional branch instruction table of FIG. It is explanatory drawing of the specific example of the instruction reading process of FIG. It is a data structure example of the reading place record table of FIG. It is another embodiment of FIG.

Hereinafter, the information processing apparatus of the present invention will be described with reference to the drawings, taking as an example an embedded device that requires real-time performance. The present invention is not limited to embedded devices, and can be applied to all information processing devices having an arithmetic processing function in which an interrupt handler is executed by a fixed-period interrupt.

(First Embodiment)
The embedded device 1 is generally an input unit that inputs a signal from an external device, an arithmetic processing unit that executes arithmetic processing based on the input signal, and has a memory for storing programs and data (hereinafter referred to as "CPU"). ), And an output unit that outputs the calculation result to an external device.

FIG. 1 is a functional configuration diagram of the CPU 2 of the embedded device 1. The CPU 2 includes an interrupt handler 26 that is activated at a predetermined cycle, a timer 21 that measures the activation interval of the interrupt handler for each interrupt handler, a priority setting means 23 that changes the priority of the interrupt handler, and an interrupt handler. Each time, a time measurement result storage table 24 for storing the start-up interval, the allowable condition regarding the deviation from the original cycle, and the like is provided. The priority setting means 23 and the interrupt handler 26 can be realized by a program.

In addition to this, the CPU 2 includes means 27 such as an application program and an operating system for realizing the functions of the embedded device 1, but since it is not directly related to the present invention, the description thereof will be omitted.

Hereinafter, as an example of the interrupt handler 26, the interrupt handler 26a that executes the control process with a fixed cycle cycle from the timer 21 and the control process with a fixed cycle cycle from the timer 21 are performed with a fixed cycle interrupt from the timer 21. This will be described using the interrupt handler 26b to be executed.

As shown in FIG. 2, the time measurement result storage table 24 has the latest execution start counter value for each of the interrupt handlers 26a and 26b for which the interrupt priority is dynamically changed, and the past n times (n> = 1). The cycle (unit is the counter value) of the natural number), the original cycle (the unit is the counter value), the number of times the cycle can be exceeded per last n executions, the cycle excess tolerance counter value, and the interrupt number are stored in association with each other. There is. Note that FIG. 2 shows an example of recording the actual value of the past three times (n = 3). The timer value is shown using the counter value. For example, in the case of 1 count in 0.1 ms, the latest cycle 510 has a time interval (startup interval) from the previous start to the current start of 51 ms (510 count x 0.1 ms / count = 51). It means that it is (milliseconds). In FIG. 2, each value of "latest execution start counter value", "latest cycle", "one cycle before", and "two previous cycles" changes with the execution of the program, and others. The item of is set in advance by the developer at the time of system construction and does not change with the execution of the program.

For example, for the interrupt handler 26a, the value "500" in the "original cycle" column indicates that the specified cycle is 50 milliseconds. The value "1" in the "Allowable number of cycle excesss per 3 executions" column allows up to 1 cycle excess in the last 3 executions. In this case, interrupt priority change processing. Is not performed, and it means that the interrupt priority change process is executed when the cycle is exceeded twice or more. Further, the value "0" of the "cycle excess permissible counter value" means that if the cycle exceeds even one count, it is determined that the cycle has been exceeded in that cycle. Further, the value "20" of the "cycle excess allowance counter value" of the interrupt handler 26b is determined that the cycle has not been exceeded until the cycle excess is within 20 counts of the original cycle, and when the cycle excess exceeds 20 counts, the cycle is exceeded. It means that it is determined that the cycle has been exceeded.

In the example of FIG. 2, three cycles are recorded, but the number of cycles to be saved may be appropriately determined by the developer according to the characteristics of the development program.

Next, the processing procedure of the priority setting means 23 will be described with reference to FIG. The priority setting means 23 is called from the interrupt handler 26 at the start of the interrupt handler 26, and executes the following processing. The initial value of the interrupt priority of each interrupt handler 26 can be arbitrarily set by the developer, but it is preferable to set it to the lowest level in the initial state.

(1) When the priority setting means 23 is called, it first reads the counter value of the timer 21 (step S101), and regarding the interrupt handler of the caller, the counter value and the cycle (startup) stored in the time measurement result storage table 24. The interval) is updated to the latest value (steps S102 to S104).
(2) Whether the number of cycles exceeding the cycle excess tolerance counter value by accessing the information regarding the caller's interrupt handler in the time measurement result storage table 24 exceeds the cycle excess tolerance counter count per three executions. It is determined whether or not (steps S105 and S106).
(3) As a result of the determination in steps S105 and S106, if the allowable number of times the cycle is exceeded is not exceeded, the priority setting process is terminated. On the other hand, if the number of times the cycle exceeds the allowable number is exceeded, it is determined whether or not it is possible to raise the interrupt priority of the caller's interrupt handler (steps S107 and S108). and,
(4) If it is possible to raise the priority as a result of the determination in steps S107 and S108, the priority of the interrupt corresponding to the interrupt handler is raised by one (step S109). On the other hand, if it is impossible to raise the priority, the user is notified by console output or the like (step S110).

The priority setting means 23 automatically adjusts the interrupt priorities of a plurality of interrupt handlers according to the above procedure.

Here, an example of a method for realizing the cycle update process (step S102) stored in the time measurement result storage table 24 of the priority setting means 23 will be described with reference to FIG.
(1) As shown in FIG. 4A, the part related to the cycle in the time measurement result storage table 24 is implemented as a circular list (cycle storage area 0 to 2) including a pointer to the latest cycle. For example, the periodic storage area 0 stores periodic data and the address of the periodic storage area 1 as the next periodic storage area. The same applies to other periodic storage areas. Now, in the state before the execution of step S102 in FIG. 3, as shown in FIG. 4A, it is assumed that the address pointed to by the pointer to the latest cycle is the address of the cycle storage area 0. That is, it is assumed that the cycle storage area 0 is used as the storage area of the latest cycle, the cycle storage area 1 is used as the storage area of the previous cycle, and the cycle storage area 2 is used as the storage area of the cycle two times before.
(2) As the process of step S102 in FIG. 3, as shown in FIG. 4 (b), the address pointed to by the pointer to the latest cycle is changed to the cycle storage area 2. As a result, the cycle storage area 0 used as the storage area of the latest cycle becomes the storage area of the previous cycle, and the cycle storage area 1 used as the storage area of the previous cycle becomes twice. It becomes the storage area of the previous cycle. By doing so, it is possible to efficiently update the periodic data for three times.

As described above, according to the present embodiment, the priority setting means sequentially raises the priority of interrupt handlers that cannot satisfy the allowable conditions set in the time measurement result storage table, so that the interrupt priority is appropriate for the entire system. Can be set automatically.

(Second embodiment)
Next, a second embodiment of the present invention will be described. FIG. 5 is a functional block diagram of the embedded device according to the second embodiment. The main difference from the first embodiment shown in FIG. 1 is the instruction reading means 28 that executes the instruction reading process so that the execution time of the interrupt handler becomes longer, and the instruction reading means 28 processing that cancels the reading process. The instruction replacement canceling means 29 to be executed, the table 30 for storing the conditional branch instruction, and the table 31 for recording the instruction replacement location have been added. Further, along with these additions, data items are added to the time measurement result storage table 24, and the processing procedure of the priority setting means 23 is changed.

FIG. 6 shows an example of the time measurement result storage table 24 according to the present embodiment. The difference from FIG. 2 is that the instruction replacement condition is added. The instruction reading condition is an execution condition of the instruction reading means 28, and is set in advance by the developer. By making it configurable by the developer, the instruction reading means 28 should not be executed for a process whose execution time does not change significantly, that is, a process whose execution time rarely becomes long. Is possible. As a result, it is possible to suppress the delay in the execution time due to the execution of the instruction replacement process.

FIG. 7 shows a processing procedure of the priority setting means 23 according to the present embodiment. The difference from FIG. 3 is that the processing procedure steps S201 to S203 are added immediately after the start of the priority setting means. Specifically, when the priority setting means 23 is activated, the command reading means 28 is called when the command reading conditions of the time measurement result storage table 24 are satisfied (steps S201 to S203). After that, the processes after step S101 are executed in the same manner as in FIG.

Next, a schematic procedure for processing the command reading means 28 will be described with reference to FIG. The instruction reading means 28 executes the following processing for each instruction of the interrupt handler that calls itself via the priority setting means 23.
(1) Whether or not the instruction is a conditional branch instruction is determined based on whether or not the instruction is included in the conditional branch instruction table 30 (step S302).
(2) If the instruction is included in the conditional branch instruction table 30, the conditional branch instruction is rewritten with another predetermined instruction (step S304). Specifically, among the processes that can be executed by the branch based on the instruction, the process that requires more execution time is rewritten so as to be executed unconditionally.
(3) The address of the replacement location, the command before the replacement, and the command after the replacement are recorded in the replacement location recording table 31. This record is used to restore the contents read by the command replacement canceling means 29.

The interrupt handler 26 calls the instruction replacement canceling means 29 at the end. As shown in FIG. 9, the called instruction replacement canceling means 29 accesses the replacement location recording table 31 and determines the interrupt handler based on the contents recorded in association with the interrupt handler of the caller of this process. The processing content of 26 is returned to before the instruction is replaced. As a result, the original processing of the interrupt handler 26 (processing before reading the instruction) is executed.

A specific example of the instruction replacement process and the conditional branch instruction table 30 is shown below.
As shown in FIG. 10, the conditional branch instruction table 30 used in the instruction reading means is a place where the conditional branch instruction and the branch processing by the branch instruction are completed based on the type of the instruction executed on the CPU 2. The instruction (branch processing end instruction) described in is recorded. These instructions are preset by the developer. The type of instruction to be registered is determined by the CPU used.

Next, an example of the command reading process according to step S304 of the command reading means 28 will be described with reference to FIG. Now, it is assumed that the instruction length of the CPU is fixed at 4 bytes and the time required for execution is the same for all instructions. Further, it is assumed that the contents shown in FIG. 10 are registered in the conditional branch instruction table 30.

In step S304, before the instruction is read, there is a conditional branch instruction "bge" at address 0x1230, and if the conditional branch instruction does not jump to address 0x1244, the processing is the branch processing end instruction "b" at address 0x1240. Because it ends with ", there are four instructions. On the other hand, the processing when jumping to the address 0x1244 is three instructions because it ends with the branch processing end instruction "bx" at the address 0x124C. Therefore, the conditional branch instruction at address 0x1230 is changed to the unprocessed instruction "nop" so that the processing when it does not jump to address 0x1244 (it takes longer than when it jumps to address 0x1244) is always executed. Replace.

The instruction replacement process is executed as described above.
FIG. 12 is an example of a replacement location recording table 31 used by the command replacement means 28 and the command replacement canceling means 29. This table stores the address of the replacement location, the command before the replacement, and the command after the replacement. A line (record) is added to the table 31 by the instruction reading means 28, and the record is read and deleted by the instruction reading canceling means 29.

(Other Examples)
The above assumes that it is possible to rewrite the instructions executed by the CPU. However, in the actual machine, the instruction may be stored in a memory that cannot be rewritten. This embodiment also makes it applicable in this case.

FIG. 13 shows a functional configuration in an embedded device for which an interrupt priority is determined. In this embodiment, instead of executing the software program in the embedded device, each means, table, etc. operating on the instruction set simulator 20 that simulates the software program on the personal computer 10 on which the instruction set simulator 20 operates are shown in the figure. It is the same as 5.

As described above, according to the present embodiment, in addition to the effect of the first embodiment, the interrupt priority can be appropriately set for the priority of the interrupt handler whose execution cycle is rarely long, and the design is difficult. It becomes possible to lower the degree.

The present invention is not limited to the above-described embodiment, and can be realized by various modifications without departing from the gist thereof. For example, in the above description, when the interrupt handler deviates from the allowable condition, the priority setting means increases the interrupt priority by 1, but the interrupt priority is increased by 2 or more according to the deviated amount. You can do it. In this way, the interrupt priority can be optimized faster.

1 Embedded device (information processing device)
2 CPU
10 Personal computer (information processing device)
20 Instruction set simulator 21 Timer 23 Priority setting means 24 Hours measurement result storage table 26 (26a, 26b, 26c) Interrupt handler 28 Instruction reading means 29 Instruction reading canceling means 30 Branch instruction table 31 Reading location recording table

Claims (6)

An information processing device that sets the interrupt priority of an interrupt handler that is executed in response to each of multiple fixed-period interrupt signals.
A timer that measures the activation interval of each interrupt handler,
A means for preserving the allowable condition for the deviation between the activation interval and the original cycle,
For each interrupt handler, it is determined whether or not the permissible condition is deviated, and if it deviates, a priority setting means for raising the interrupt priority of the interrupt handler is used.
An information processing device characterized by being equipped with. The allowable condition is determined by whether or not the difference between the preset original activation cycle of each interrupt handler and the value of the timer exceeds the threshold value, or is based on the number of times the difference exceeds the threshold value. The information processing apparatus according to claim 1, wherein the information processing apparatus is defined. Save the interrupt priority for each interrupt handler and save it.
Initially, all interrupt handlers are set to the lowest priority.
The information processing apparatus according to claim 1 or 2, wherein the priority setting means raises the interrupt priority of the interrupt handler when the interrupt handler deviates from the permissible condition. An instruction reading means that detects a conditional branch instruction in the program code for each interrupt handler and replaces the conditional branch instruction with a preset instruction other than a no-operation instruction or other conditional branch instructions.
After the interrupt handler is executed, the instruction replacement canceling means for returning the instruction replaced by the instruction reading means back to the original conditional branch instruction,
The information processing apparatus according to any one of claims 1 to 3, wherein the information processing apparatus is provided. It has a conditional branch instruction table that stores a list of conditional branch instructions.
The instruction reading means refers to the conditional branch instruction table, determines whether or not the corresponding conditional branch instruction exists in the program code of the interrupt handler, and if the conditional branch instruction exists, the conditional branch instruction is present. The conditional branch instruction and the address where the conditional branch instruction existed are recorded in the replacement location recording table.
The information processing apparatus according to claim 4, wherein the instruction replacement canceling means refers to the replacement location recording table and returns the instruction replaced by the instruction replacement means to the original conditional branch instruction. .. The information processing apparatus according to any one of claims 1 to 5, wherein if the interrupt priority of the interrupt handler rises to a predetermined predetermined priority and still deviates from the allowable condition, an alarm is output. ..

Images