JP2011186591A - Processor and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor and a control method therefor, capable of reducing power consumption. <P>SOLUTION: The processor includes an interruption period decision unit for calculating the period of an interruption request from each interruption generation circuit and deciding the periodicity thereof, a synchronization detection unit for detecting whether each interruption generation circuit is an interruption synchronization target circuit, that is, a target capable of synchronization with an interruption request source circuit generating the interruption request, a time difference detection unit for detecting a time difference of next interruption generation timing between the interruption request source circuit and the synchronization target circuit, and an interruption processing time adjustment unit for adjusting the next interruption generation timing so as to delay the interruption processing start time of the interruption request source circuit by the time difference of the next interruption generation timing when the time difference of the interruption timing is within a predetermined time. By this, interruption requests from a plurality of interruption generation circuits are adjusted. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a processor that performs interrupt control for a power switch system and a control method thereof.

  In recent years, the power consumption of the system has been increasing due to the improvement of CPU processing speed and the use of multiprocessors. As a countermeasure, the installation of power-saving technology such as power management using a power switch is indispensable for the system. . However, since it is necessary to start the CPU by turning on the power switch every time there is an interrupt request, a technique for reducing the number of activations has become necessary.

  Patent Document 1 discloses a power saving technique for reducing the number of CPU activations by processing a plurality of timer events at the same timing by adjusting the event generation timing for a timer event managed by a timer.

  FIG. 17 is a block diagram showing a timer management device described in Patent Document 1. In FIG. As shown in FIG. 17, timer queue elements 535, 555, 575, etc. of one (sub) system are connected in a queue form, and this queue is connected to each (sub) system by timer queue management tables 532, 552, 572, etc. Managed. The (sub) system is managed by timer management tables 530, 550, and 570 for each (sub) system, and each (sub) system is managed by the system queue management table 510. Examples of (sub) systems include a Code Division Multiple Access (CDMA) system, a digital mobile phone / personal digital cellular (PDC) system, or a PHS (Personal Handyphone System).

  The idle timer queue 520 is connected to timer queue elements whose processing has been completed after the timer has counted up, that is, timer queue elements that have been used up. If there is no empty timer queue element, a new timer event cannot be issued, so garbage collection is performed as appropriate.

  When a new timer queue element is connected to the timer queue 540 or the like, and there is a timer queue element 535 or the like in the timer queue 540 or the like, a differential timer value is calculated and the new timer queue element is connected to the timer queue. On the other hand, when there is no timer queue element, the timer value 210 is set as it is at the head of the timer queue 540 or the like, and a new timer queue element is connected as it is.

  Next, a timer management apparatus and method that can reduce the number of times the timer event times up will be described below with reference to FIGS. 18 (a) and 18 (b). FIGS. 18A and 18B are time charts showing the operation of the periodic timer event in the embodiment. As shown in FIG. 18A, for example, it is assumed that there is a periodic timer event 1 with a periodic activation time of 1 second and a periodic timer event 2 with a periodic activation time of 2 seconds. In this case, if time phase alignment is not achieved, that is, if timer event 1 and timer event 2 are asynchronous, timer event 1 occurs five times in total, T2, T3, T5, T6, and T8. 2 occurs 3 times in total, T1, T4 and T7, and 8 times in total.

  On the other hand, as shown in FIG. 18B, two timer events 1 and 2 are obtained at timings T12, T14, and T16 by matching the temporal phases at which the two periodic timer events 1 and 2 occur. The time can be increased at the same time. As a result, the number of occurrences of the timer event can be reduced from 8 times to 5 times. Hereinafter, a method of matching the temporal phases of two timer events will be described. As shown in FIG. 18B, when the periodic timer event 2 is activated (Tz), the timer event 2 is synchronized with the time phase of another periodic timer event 1 that is already running on the timer queue. Adjust the issue time and connect to the timer queue.

  When registering the timer event 2 (Tz), the difference Δt = T12−Tz between the time-up times T12 and Tz of the other periodic timer event 1 is calculated, and this Δt is set to the first (1 Set as timer value. That is, timer value = Δt, timer operation type = cycle, period activation time = period desired to be activated periodically, etc. As described above, the timer value of the timer event 2 is set to Δt instead of the original period start time (= 2) so as to synchronize with the generation period (= 1) of another periodic timer event 1 in this way. Once synchronization is achieved at T12, T14 and T16 are also synchronized thereafter. As a result, the number of timer interrupts generated by the hardware timer can be reduced. Therefore, since the power consumed when the CPU is activated by a timer interrupt or the like can be reduced, power saving can be greatly measured in the case of a battery-driven system such as a mobile phone.

  For example, an operation when a periodic timer event with a periodic activation time of 12 and a timer event with a period of 72 are added to a periodic timer event with a periodic activation time of 6 will be described. A timer event with a periodical activation time of 12 and an activation time of 72 is issued in accordance with the time phase of the periodical activation time of 6. Timer queue elements corresponding to both timer events are connected to the timer queue. In this case, since there is the greatest common divisor 6 in the cyclic activation times 6, 12, and 72, even if two timer events with the cyclic activation times 12 and 72 are added, the CPU is activated to process the timer event. The number of times played is not increased. With the greatest common divisor, there is no limit to the number of timer events that can be added except for conditions such as memory.

  Conversely, the same applies when a timer event with a periodical activation time of 6 is connected to an event with a periodical activation time of 72. When a timer event with a periodic activation time of 6 is connected to an event with a periodic activation time of 72, the greatest common divisor between 72 and 6 is 6, so that the timer event with a periodic activation time of 72 times out It is only necessary to issue an event with a periodical activation time of 6 and connect to the timer queue at the timing of giving the maximum n that the number obtained by subtracting 6 × n hours becomes 0. The reason for giving the maximum n is to make it the earliest timing.

  An example in the case where the cyclic start times are disjoint will be shown. Assume that a timer event with a periodical activation time of 3 is issued while a timer event with a periodical activation time of 5 is operating. At this time, an event having a periodic activation time of 5 and an event having a periodic activation time of 3 are relatively prime, that is, they are prime and not a common divisor. In this case, the timer event issuance timing is adjusted so that the occurrence of two timer events overlaps the time when the cyclic activation time is the least common multiple 15 (3 × 5) of 3 and 5. That's fine.

  As described above, according to the embodiment, since the number of times the hardware timer times up can be reduced by performing time phase alignment between periodic timer events, the CPU is started and consumed by a timer interrupt or the like. Electric power can be reduced.

JP 2000-259429 (FIGS. 5 and 12)

  However, when considering the power consumption of the entire system, the prior art has a problem in that the power saving effect is small because the number of CPU activations other than timer events cannot be reduced. The reason for this is that it is necessary to set the timer event generation cycle as an initial setting in advance, and it can be applied only to interrupt processing whose cycle is clear as a specification, such as a timer event, and the timing adjustment target is limited. This is because it is trapped.

  In addition, when matching the interrupt processing generation timing of multiple events, if the relationship between the multiples and divisors of the interrupt generation cycle is extracted and the relationship cannot be extracted, the timing is only when the cycle has the least common multiple relationship. Therefore, the timing for adjustment is limited.

  Therefore, in the prior art, when there is no relation between a multiple and a divisor in the interrupt generation period, the generation timing can be matched only with the least common multiple of the respective interrupt generation periods. For this reason, the number of IPs to be synchronized is small, the power supply voltage is restored many times, and the power saving effect is small.

  A processor according to the present invention is a processor that adjusts interrupt requests from a plurality of interrupt generation circuits, calculates an interrupt request period from each interrupt generation circuit, and determines an interrupt period determination unit; For each interrupt generation circuit, a synchronization detection unit that detects whether or not the interrupt synchronization target circuit is a target that can be synchronized with the interrupt request source circuit that generated the interrupt request, and the interrupt request source circuit and its synchronization An interrupt time difference detection unit that detects a time difference of next interrupt generation timing with the target circuit, and when the interrupt timing time difference is within a predetermined time, the interrupt processing start time of the interrupt request source circuit is Adjust the next interrupt generation timing by delaying the next interrupt generation timing time difference. Those having a interrupt processing time adjuster.

  The processor control method according to the present invention is a processor that adjusts interrupt requests from a plurality of interrupt generation circuits, calculates a cycle of interrupt requests from each interrupt generation circuit, determines its periodicity, For the generation circuit, it is detected whether or not it is an interrupt synchronization target circuit that is a target that can be synchronized with the interrupt request source circuit that generated the interrupt request, and between the interrupt request source circuit and the synchronization target circuit, When the time difference of the next interrupt generation timing is detected and the time difference of the interrupt timing is within a predetermined time, the interrupt processing start time of the interrupt request source circuit is delayed by the time difference of the next interrupt generation timing. Make adjustments.

  In the present invention, the periodicity of the interrupt request is determined, and among the periodic ones, an interrupt generation circuit that generates an interrupt within a predetermined range is extracted, and the interrupt timing is adjusted. Power consumption can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the processor which can reduce power consumption, and its control method can be provided.

1 is a block diagram showing an interrupt control system having a multiprocessor and a power switch mounted circuit according to an embodiment of the present invention. It is a schematic diagram which shows the CPU circuit part in embodiment of this invention. It is a flowchart figure which shows the process of the timing adjustment of the interruption process in embodiment of this invention. It is a flowchart figure which shows the example of the period calculation operation | movement in embodiment of this invention. It is a figure which shows the structural example of the data 120 for process start timing correction in embodiment of this invention. It is a figure which shows the structural example of the interruption process period data storage part 119 in embodiment of this invention. It is a flowchart figure which shows the example of the periodicity determination operation | movement in embodiment of this invention. It is a figure which shows the structural example of the interrupt interval data register 115 concerning embodiment of this invention. It is a time chart figure which shows the example of the synchronous object detection operation | movement in embodiment of this invention. Similarly, it is a time chart showing an example of a synchronization target detection operation in the embodiment of the present invention. It is a flowchart figure which shows the example of the time difference detection operation | movement of the interruption generation timing in embodiment of this invention. It is a figure explaining the next interruption generation | occurrence | production time difference in embodiment of this invention. Similarly, it is a figure explaining the next interruption generation | occurrence | production time difference in embodiment of this invention. Similarly, it is a figure explaining the next interruption generation | occurrence | production time difference in embodiment of this invention. It is a flowchart figure which shows the example of duplication determination operation | movement of the interruption generation timing in embodiment of this invention. It is a flowchart figure which shows the example of the maximum Wait time determination operation | movement in embodiment of this invention. (A) And (b) is a time chart figure which shows the Example of the interruption process wait instruction | indication of this invention. (A) And (b) is a time chart figure which shows the example of operation | movement in the conventional example and embodiment of this invention, respectively. 10 is a block diagram showing a timer management device described in Patent Document 1. FIG. (A) And (b) shows the operation | movement of the periodic timer event in embodiment with a time chart.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to an interrupt control system that performs interrupt control of a power switch system.

  In the present embodiment, in the interrupt control of the power switch system, a process of selecting a synchronization target IP for matching the interrupt generation timing within the CPU power recovery processing time and the interrupt request source interrupt processing time CPU power recovery processing time and interrupt request source interrupt processing time to determine the interrupt generation timing overlap to match the interrupt generation timing, CPU power recovery processing time and interrupt request A process for adjusting the interrupt processing start time for adjusting the interrupt generation timing within the original interrupt processing time is performed. Thereby, it is possible to obtain a power saving effect that is higher than that of the prior art.

  FIG. 1A is a block diagram showing an interrupt control system having a multiprocessor and a power switch mounting circuit according to the present embodiment. As shown in FIG. 1, an interrupt control system 100 according to the present embodiment includes IP (Intellectual Property) 101, 102, 103 as a plurality of interrupt generation circuits, a multiprocessor system 104, and an interrupt control device 121. Have.

  The multiprocessor system 104 includes an interrupt controller 105, power switch circuits 106 and 107, and CPU circuit units 108 and 109.

  In the multiprocessor system 104, the CPU circuit units 108 and 109 are connected to the power switch circuit units 106 and 107 connected to the power supply VDD, respectively, and the power switch circuit units 106 and 107 are connected to the interrupt controller 105. . The power switch circuit units 106 and 107 are controlled by the CPU circuit units 108 and 109 or the interrupt controller 105 depending on whether the CPU circuit units 108 and 109 are operating or idle. Each interrupt signal output from each IP 101, 102, 103 is connected to the interrupt controller 105 and also connected to each time difference detection circuit 112, 113, 114.

  The interrupt interval detection system 110 includes time difference detection circuits 112, 113, 114, interval data registers 115, 116, 117, and a timer circuit unit 111. Each time difference detection circuit 112, 113, 114 uses the connected timer circuit unit 111 to calculate the time interval at which an interrupt request from each IP 101, 102, 103 occurs, and the result is sent to each interval data register 115, 116, It outputs to 117. Each of the interval data registers 115, 116, 117 is composed of a FIFO (First-In First-Out) register, and the output is used by the CPU circuit units 108, 109 via a data bus.

  The memory area 118 includes an interrupt processing period data storage unit 119 and a processing start timing correction data storage unit 120. Data stored in these storage units is read out to the CPU circuit units 108 and 109 via the data bus and used for processing. Each of the IPs 101, 102, 103 issues an interrupt request to one of the CPU circuit units 108, 109 via the interrupt controller 105, and when an interrupt request is accepted, the CPU circuit units 108, 109 via the data bus. Controlled by either.

  FIG. 1B is a schematic diagram showing the CPU circuit unit 108 and the CPU circuit unit 109. As shown in FIG. 1B, the CPU circuit unit 108 and the CPU circuit unit 109 are processors that adjust interrupt requests from a plurality of IPs 101, 102, and 103, calculate the period of interrupt requests from each IP, and A function for determining periodicity (interrupt period determining unit) and a function for detecting whether each IP is a synchronization target IP that can be synchronized with the interrupt request source IP that generated the interrupt request (synchronization) Detection unit), a function for detecting a time difference of the next interrupt generation timing (interrupt time difference detection unit) between the interrupt request source IP and the synchronization target IP, and the interrupt timing time difference is within a predetermined time. If the next interrupt occurs, the interrupt processing start time of the interrupt request source IP is delayed by the next interrupt generation timing difference. Function of adjusting the timing and a (interrupt processing time adjuster). The interrupt control processing executed by the CPU circuit units 108 and 109 can be realized by causing the CPU circuit units 108 and 109 to execute computer programs. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another transmission medium.

  Next, the operation of the processing system according to this embodiment will be described. In the processing system according to the present embodiment, as an initial setting of the system operation, the multiprocessor system 104 includes a time required for turning on the power switch circuit units 106 and 107, a time required for interrupt processing of each IP 101, 102, and 103, and a process. The maximum time (maximum Wait time) during which the start can be delayed is preset in the interrupt processing period data storage unit 119 as interrupt processing period data.

  In the interrupt control system according to the present embodiment, when an interrupt request occurs in any of IPs 101, 102, and 103 (hereinafter, the IP that generated the interrupt request is referred to as an interrupt request source IP), the corresponding IP interrupt signal. Are connected to the respective time difference detection circuits 112, 113, 114 using the calculated time as the interrupt generation interval data. The interval data registers 115, 116, and 117 are sequentially held. In this embodiment, it is assumed that there are 10 interval registers each.

  Next, when receiving the interrupt request, the multiprocessor system 104 adjusts the processing start timing for the interrupt processing according to the following procedure. FIG. 2 is a flowchart showing timing adjustment processing for interrupt processing in the present embodiment. The interrupt processing timing adjustment method in this embodiment will be described with reference to FIG. Details of each step will be described later.

  First, one of the CPU circuit units 108 and 109 that has received an interrupt processing request by the interrupt controller 105 stores the interval data registers 115, 116, and 117 of each IP detected by the interrupt interval detection system 110 in step S201. Based on the above, the interrupt generation cycle of each IP 101, 102, 103 is calculated.

  In step S202, one of the CPU circuit units 108 and 109 determines whether or not there is periodicity with respect to the calculated interrupt generation cycle of each of the IPs 101, 102, and 103. If there is periodicity in interrupt generation of the interrupt request source IP, the process proceeds to the next step S203. Then, an IP that can synchronize the interrupt generation timing with the interrupt request source IP (hereinafter referred to as a synchronization target IP) is detected from the IPs 101, 102, and 103 other than the interrupt request source.

  If there is a synchronization target IP corresponding to the interrupt request source IP, the process proceeds to the next step S204, and any one of the CPU circuit units 108 and 109 performs the synchronization with respect to all the synchronization target IPs detected in step S203. The generation time difference of the next interrupt generation timing with the interrupt request source IP is calculated.

  Proceeding to the next step S205, one of the CPU circuit units 108 and 109 interrupts all the synchronization target IPs based on the time difference of the next interrupt generation timing calculated in step S204. It is determined whether the next interrupt occurrence timing overlaps with the request source IP. If there is a synchronization target IP that does not overlap the interrupt request source IP and the next interrupt generation timing, the process proceeds to the next step S206, and one of the CPU circuit units 108 and 109 determines the next interrupt calculated in step S204. It is determined whether the generation time difference between the generation timings is within a preset maximum wait time of the interrupt request source IP. If the next interrupt generation timing difference is within the maximum wait time of the interrupt request source IP, the process proceeds to the next step S207, and any one of the CPU circuit units 108 and 109 determines whether the interrupt request source IP interrupts. The next interrupt generation timing is adjusted by delaying the processing start time by the generation time difference of the next interrupt generation timing.

  Next, the detailed flow of each step will be described. In step S201, the CPU circuit units 108 and 109 calculate the period based on the interrupt generation interval data. Assume that the interrupt generation interval data registers 115, 116, and 117 hold, for example, 10 interrupt generation time interval data. Note that the number of data that can be held is variable depending on the number of mounted registers.

  FIG. 3 is a flowchart showing an example of the cycle calculation operation in the present embodiment. As shown in the flow of FIG. 3, the cycle is calculated as the average value of the interrupt generation interval data.

Maximum first data of each interval data registers 115, 116 and 117 for each IP101,102,103 the _I 1, 2-th data in the case where the _I 2, n-th data and _{I n,} as an initial value value Max and _{I 1,} the total value total and 0 (S20101). Comparing the second data _{I 2} and Max, the value of _{I 2} is adding the _{I 2} to Total value smaller than the Max value. If the value of I ₂ is equal to or greater than the Max value, the Max value is added to the Total value, and I ₂ is substituted as the Max value (S20102, S20103, S20104). CPU circuit unit 109 performs the processing up to _{I 10} is the last data of the number held by each interval data registers 115, 116, 117, and calculates the Total value of the interrupt occurrence time interval data (S20105). Next, the CPU circuit units 108 and 109 divide the calculated Total value by the value obtained by subtracting 1 which is the number of data of the Max value from the number of data n held in each of the interval data registers 115, 116 and 117 to generate an interrupt. The period T is calculated (S20106). The calculated cycle is held in the correction data storage unit 120 as process start timing correction data.

  FIG. 4 is a diagram illustrating a configuration example of the processing start timing correction data 120 in the present embodiment. As shown in FIG. 4, the process start timing correction data holds the period for each IP, the presence / absence of periodicity, the time until the occurrence of an interrupt, and information on the synchronization target IP. As updated. FIG. 5 is a diagram illustrating a configuration example of the interrupt processing period data storage unit 119. The interrupt processing period data storage unit 119 holds information on the interrupt processing period and the maximum waitable time.

  FIG. 6 is a flowchart showing an example of the periodicity determination operation in the present embodiment. As shown in the flow of FIG. 6, the periodicity determination in step S202 is performed by comparing the values stored in the correction data storage unit 120 with the values of the interval data registers 115, 116, and 117 by the CPU circuit units 108 and 109. This is done by confirming that the difference is within the allowable error range.

  First, the CPU circuit units 108 and 109 obtain the interrupt generation cycle of each of the IPs 101, 102, and 103 from the correction data storage unit 120 and the CPU power switch ON processing time from the interrupt processing period data storage unit 119, respectively. The switch ON processing time is set as an allowable error when determining periodicity.

Next, the first data interval data register 115 of the IP101 to _I 1, 2 th data was _I 2, n-th data and _{I n,} the data having a difference exceeding the allowable error and the interrupt generation period T of the IP101 The number of I is Nout, and Nout is set to 0 as an initial value (S20201). It is confirmed whether or not the difference between the _first data I1 of the interval data register 115 and the interrupt generation period T is within the allowable error, and if the difference is larger than the allowable error range, 1 is added to Nout (S20202, S20203). . CPU circuit unit 109 performs the processing up to _{I 10} is the last data of the interval data holding number, if the way in Nout becomes 2 or more, determined not to periodicity in the interrupt generation of the target IP Then, the determination process ends (S20204, S20207). Nout is the After the process of final data _{I 10} without being 2 or more, it is determined that there is periodicity, determining processing is ended (S20205, S20206). The determination result is held in the correction data storage unit 120 as process start timing correction data. The IPs 102 and 103 perform the same determination process.

FIG. 7 is a diagram illustrating a configuration example of the interrupt interval data register 115 according to the present embodiment. More specifically, 10 μs is set as the allowable error of IP101 from FIG. Next, since the difference between the _first data I ₁ = 100 μs (FIG. 7) of the interval data register 115 of IP 101 and the interrupt generation period 100 μs (FIG. 4) is within an allowable error, Nout is kept at 0, proceeds to process the next data I _2. Continuing the processing, I ₅ = 250 μs is set so that Nout is 1 because the difference from the interrupt generation period of 100 μs is an allowable error of 10 μs or more. Thus, if the processing is continued up to the 10th data, Nout = 1 is obtained for IP101, and therefore it is determined that there is periodicity (FIG. 4: Yes).

  The processing start timing correction data is updated as periodicity presence / absence data in the periodicity column as shown in FIG. In the example shown in FIG. 4, as the interrupt generation periodicity determination of IP_103, there are two or more data whose difference from the interrupt generation cycle 333 μs is the power switch ON processing time 10 μs or more shown in FIG. 109, it is determined that IP_103 has no periodicity (No).

  8A and 8B are time chart diagrams illustrating an example of the synchronization target detection operation in the present embodiment. The flow of FIGS. 8A and 8B shows an IP detection method that can be a synchronization target of interrupt generation timing for the interrupt request source IP in step S203. That is, the CPU circuit units 108 and 109 interrupt the interrupt request source IP within the time between the CPU power switch ON processing period and the interrupt processing period of the interrupt request source IP among the IPs other than the interrupt request source. Extract those in which the relationship between generation cycle and multiple or divisor is established.

First, when the interrupt request source IP was IP101, CPU circuit unit 109 determines to acquire the periodicity whether interrupt generation period _{T n} of the interrupt request source IP101 from the correction data storage unit 120 (S20301 ). If there is no periodicity, the detection of the synchronization target IP is terminated at that time. If there is periodicity, the CPU circuit units 108 and 109 obtain the interrupt processing period of the IP 101 and the CPU power switch ON processing time from the interrupt processing period data storage unit 119. Then, the CPU circuit units 108 and 109 substitute the value obtained by adding the power switch ON processing time of the CPU and the interrupt processing time of the interrupt request source IP as the initial value of the interrupt overlap possibility period Tw for the interrupt request source IP, and The detection of the IP to be activated is started (S20302). In the case of IP101, the initial value of Tw is 25 μs. At that time, the interrupts to be detected as synchronization targets when m = 1 are started in order from the interrupt with the smallest interrupt ID (S20303). Note that IP101 to IP103 are assigned interrupt IDs = 1 to 3, respectively.

The CPU circuit unit 108 or 109 that received the interrupt processing request compares the interrupt ID number of the interrupt request source IP with the interrupt ID number of the synchronization detection target IP and confirms that they are different IDs (S20304). If different, the detected synchronization target IP acquires periodicity whether interrupt generation period T _m of a (hereinafter, referred to. Synchronization detection target IP) from the correction data storage unit 120. In this case, if the synchronization detection target IP is IP102, it is determined from FIG. 4 that there is periodicity. If there is no periodicity, the synchronization detection target is shifted to the IP of the next interrupt ID number (S20305). If the CPU circuit units 108 and 109 have periodicity, the CPU circuit units 108 and 109 check the divisor relationship with respect to T _n and T _m .

CPU circuit unit 108 and 109, determines the _{T n} a remainder when divided by _{T m,} the _{T n} and _{T m} if the value obtained by subtracting from the _{T m} is less than or equal to _{T w} and divisor relationship holds and, in the case it was greater than _{T w} determined that about a few relationship is not satisfied (S20306). If divisor relationship is composed, add the interrupt processing time of the synchronization detection target IP to _{T w} (S20308), adds a synchronization detection target IP interrupt request source IP to be synchronized IP (S20309). The added synchronization target IP is held as the correction data storage unit 120. In step S20306, if the divisor relationship does not hold, CPU circuit unit 109 performs confirmation of a multiple relationship to _{T n} and _{T m.} The T _m is determined ploidy is established to _{T n} and _{T m} when the remainder when divided by _{T n} is equal to or less than Tw, determines that does not hold ploidy if greater than _{T w} (S20307 ). When the multiple relationship holds, the synchronization detection target IP is added to the synchronization target IP of the interrupt request source IP. The added synchronization target IP is held as the correction data storage unit 120 (S20309). In step S20307, if the multiple relationship does not hold, the synchronization detection target is shifted to the IP of the next interrupt ID number. These processes are performed for all interrupt IDs, and synchronization target IPs are detected (S20310, S20311).

  In the example shown in FIG. 4, IP_102 is detected as the synchronization target IP of IP_101. The CPU circuit units 108 and 109 confirm from the correction data storage unit 120 in FIG. 4 that the interrupt generation of the interrupt request source IP_101 has periodicity, and acquire the interrupt generation cycle 100 μs (Tn) of IP_101. Next, the CPU circuit units 108 and 109 set 25 μs, which is the sum of the interrupt processing period 15 μs of IP_101 acquired from the interrupt processing period data storage unit 119 of FIG. 5 and the CPU power switch ON processing period 10 μs, as the interrupt overlap possibility period Tw. To do. Then, the CPU circuit units 108 and 109 confirm from the correction data storage unit 120 in FIG. 4 that the generation of the interrupt of the synchronization target detection target IP_102 has periodicity, and set the IP_102 interrupt generation cycle of 210 μs (Tm). get. That is, here, the interrupt generation cycle Tn of the interrupt request source IP101 is 100 μs from FIG. 4, and the interrupt generation cycle Tm of the synchronization target IP (IP102) is 210 μs.

  Then, the CPU circuit units 108 and 109 check the divisor relation for the acquired interrupt request source IP_101 and the detection target IP_2 to be synchronized and the respective interrupt generation cycles. The remainder of dividing the IP_101 interrupt generation period of 100 μs by the IP_102 interrupt generation period of 210 μs is 100 μs, which is greater than the interrupt overlap possible period of 25 μs. Next, the CPU circuit units 108 and 109 confirm the multiple relationship. When the interrupt generation period 210 μs of IP_102 is divided by the interrupt generation period 100 μs of IP_101, the remainder is 10 μs, and the interrupt overlap possible period is 25 μs or less. to add.

FIG. 9 is a flowchart showing an example of the time difference detection operation of the interrupt generation timing. The processing of the interrupt generation timing time difference detection operation in step S204 will be described with reference to the flowchart of FIG. In this step, CPU circuit unit 109 detects the interrupt generation timing time difference _{T A} between the interrupt request source IP and its synchronization target IP.

  The time difference detection process of the interrupt generation timing is performed only for the synchronization request IP (hereinafter referred to as the interrupt generation timing time difference detection target) of the interrupt request source IP registered in the correction data storage unit 120. At that time, the CPU circuit units 108 and 109 set m = 1, then increment m (+1), and check the interrupt generation timing time difference detection target while checking the number of IP synchronization target IPs. Process in order from the smallest IP. (S20401, S20409, S204010)

First, the CPU circuit units 108 and 109 generate the interrupt generation period T _n of the interrupt request source IP, the interrupt generation period T _{m of} the interrupt generation timing time difference detection target IP, and the next interrupt generation time T _m2 ( 4) is acquired from the correction data storage unit 120. Next, _{T m} is determined whether _{T n} is less than (S20402), if _{T m} is less than _{T n,} the remainder C when obtained by dividing a value obtained by subtracting the _{T m2} from _{T n} with _{T m} T _m was subtracted from the value _T m -C = _{T a} to the next interrupt occurrence time difference (S20403, S20407) (see FIG. 10).

Then, if T _m is _{equal to} or greater than T _n , the CPU circuit units 108 and 109 determine whether T _m2 is smaller than T _n (S20404). If T _m2 is smaller than T _n , T _m2 is determined as T _m . T _m2 minus _{T n} from the value obtained by adding the value _{T m + T m2 -T n =} T a to the next interrupt occurrence time difference (S20405, S20408) (see FIG. 11). T _m2 is equal to or larger than _{T n,} a value obtained by subtracting _{T n} from _{T m2 T} m2 _-T n = T _A to the next interrupt occurrence time difference (S20406, S20408) (see FIG. 12).

  Then, the CPU circuit units 108 and 109 increase the value of m by +1 (S20408) and perform the above processing for all the synchronization target IPs, and the value of m becomes the same as the number of synchronization target IPs. Until next time, the next interrupt generation timing difference detection with each synchronization target IP is detected (S20407).

  FIG. 13 is a flowchart showing an example of the operation for determining the overlap of interrupt generation timing. The process for determining the duplication of the interrupt generation timing in step S205 will be described with reference to the flowchart of FIG.

  The duplication determination of the interrupt generation timing is performed only for the synchronization target IP of the interrupt request source IP registered in the correction data storage unit 120. At that time, the overlap determination target is processed in order from the IP with the small difference in the next interrupt request occurrence time detected in step S204.

First, the CPU circuit units 108 and 109 obtain the CPU power switch ON processing period and the interrupt processing time of the interrupt request source IP from the interrupt processing period data storage unit 119, and add the values to the interrupt duplication for the interrupt request source IP. It is set as an initial value of the period T _w. Further, 0 is set as an initial value of the maximum value T _max of the next interrupt request occurrence time difference. Further, the interrupt occurrence timing duplication determination target IP is set to IP_m, and the IP having the smallest difference in the next interrupt request occurrence time detected in step S204 is set (S20501).
Then the next interrupt request occurrence time difference _{T A} between the detected interrupt request source IP and IP_m is to compare the interrupt request source IP interrupt generation cycle _{T n} is less than in the step S204 (S20502). When T _A is _{equal to} or greater than T _n (S20502), the duplication determination target IP is changed to the next IP until the value of m becomes equal to the number of synchronization target IPs (S20506, S20507). If the next interrupt occurrence time difference _{T A} is larger than _{T n,} for example, as shown in FIG. 11, with respect IP2_ _POS2, between IP1_ _POS2, there is IP1_ _POS3, should achieve synchronization between the IP1_ _POS3 Therefore, such a pair is excluded from the synchronization target.

Next, when T _A is smaller than T _n , the CPU circuit units 108 and 109 compare whether T _A is longer than the interrupt duplication possible period T _w for the interrupt request source IP (S20503). If T _A seemed less _{T w,} acquires the interrupt processing time IP_m interrupt processing period data storage unit 119, in addition to _{T w} (S20505), the value of m is equal to the number of synchronization target IP The overlap determination target IP is changed to the next IP until it becomes (S20506, S20507). If T _A is larger than _{T w,} the following overlapping determination target IP to detect a synchronization target IP that next generation interrupt IP_m do not overlap (S20504), the value of m is the same as the number of synchronization target IP (S20506, S20507).

  These processes are performed on all the synchronization target IPs, and the next interrupt generation timing is determined to be overlapped with each synchronization target IP, and the synchronization target IPs that are not overlapped with the next interrupt generation timing are detected.

FIG. 14 is a flowchart showing an example of the maximum wait time determination operation. The maximum wait time determination at step 206 will be described with reference to the flowchart of FIG. First, the CPU circuit units 108 and 109 set the initial value of m to 1 with IP_m as the synchronization target IP detected at step 206 and not overlapping the next interrupt generation timing. Further, 0 is set as the initial value of the maximum value T _max of the next interrupt generation time difference between the synchronization target IP and the interrupt generation request source IP whose next interrupt generation timing does not overlap (S20601).

Next, the CPU circuit units 108 and 109 obtain from the interrupt processing period data storage unit 119 the maximum allowable time T _wait that can delay the processing with respect to the interrupt processing of the interrupt request source IP, and the interrupt request source IP and IP_m next interrupt request occurrence time difference _{T a} and performs a comparison or _{T wait} less _(S20602), is greater than _{T wait} changes the synchronization target IP that next interrupt generation timing does not overlap with the next IP (S20605, S20606). In the following cases _{T wait,} T _A makes a comparison of greater than T _max (S20603), the following cases T _max, the next interrupt generation timing to change the synchronization target IP that does not overlap the next IP (S20605 , S20606). T If _max greater than substitutes _{T A} to T _max (S20604).

These processes are performed on all synchronization target IPs whose next interrupt generation timings do not overlap, and the next interrupt generation time difference between the synchronization target IP and the interrupt generation request source IP whose next interrupt generation timings within T _wait do not overlap. The maximum value T _max is detected. Next, the CPU circuit units 108 and 109 compare whether or not the detected T _max is larger than the initial value 0 (S20607), and if it is larger, adjust the interrupt processing start time of the interrupt generation request source IP for T _max . Do. If it is less than or equal to 0, the next interrupt generation time difference within T _wait does not exist, so the time adjustment for interrupt processing start is not performed.

FIGS. 15A and 15B are time charts showing an embodiment of an interrupt processing wait instruction according to the present invention. In the example of FIG. 15 (a), IP_101 because larger interruption overlap period _{T w} of the next interrupt generation timing time difference _{T b} is plus the interrupt processing time and CPU power switch ON processing period IP_101 of IP_102, next interrupt occurs timing T _b is detected as the maximum value of the time difference between the synchronization target IP which do not overlap.

Since T _b which is the maximum value of the next interrupt occurrence time difference is equal to or less than T _wait, as described above, the start of interrupt processing of the interrupt request source IP is delayed by T _b in step 207 of FIG.

FIG. 15B shows the interrupt timings of the adjusted interrupt request source IP_101 and the synchronization target IP_102. In the example of FIG. 15 (b), the by delaying the interruption process starts in IP_101 _{T b} by the maximum value of the next interrupt request occurrence time difference, are combined for the next interrupt timing of IP_101 and IP_102.

  In this embodiment, considering the execution time of the CPU recovery process and the interrupt request source interrupt process when an interrupt request is generated, the interrupt generation timing is adjusted within the time when the above process is performed. Therefore, there is an effect that it is possible to obtain a power saving effect higher than that of the conventional technology. The reason for this is that, in the prior art, when there is no relation between a multiple and a divisor in the interrupt generation period as in IP_A and IP_B in FIG. 16A, the generation timing is matched only with the least common multiple of each interrupt generation period. This is because they cannot. Therefore, there are few IPs to be synchronized, and the power saving effect is also small.

  FIG. 16B is a time chart showing an example of the operation in the present embodiment. The IP_A and IP_B interrupt timings and the power supply voltage of the processor are shown. In the present embodiment, the interrupt interval detection system 110, the interrupt processing period data storage unit 119, and the processing start timing correction data storage unit 120 are provided, so that the CPU power recovery processing and interrupts that occur when an interrupt request is generated. In consideration of the execution time of the interrupt process of the request source, the interrupt generation timing is adjusted within the time when these processes are performed. As a result, as shown in FIG. 16B, the interrupt generation timing of (A) in the figure is delayed to (B) in the figure, thereby interrupting IP_A and IP_B in (B) and (C) in the figure. Overlapping occurrence timing. In this way, even when there is no relationship between multiples and divisors in each other's cycle, since timing adjustment is performed at any time, the number of IPs to be synchronized increases, and the number of times to restore the power supply voltage is small and the power saving effect is large. It is to become.

  In this embodiment, it is possible to obtain a power saving effect that is higher than that of the prior art. The reason for this is to adjust the interrupt generation timing within the time during which the above processing is performed in consideration of the execution time of the CPU return processing and the interrupt processing of the interrupt request source when the interrupt request is generated. .

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

100 Interrupt control system 101 IP
102 IP
103 IP
104 multiprocessor system 105 interrupt controller 106 power switch circuit 107 power switch circuit 108 CPU circuit section 109 CPU circuit section 110 interrupt interval detection system 111 timer circuit section 112 time difference detection circuit 113 time difference detection circuit 114 time difference detection circuit 115 interval data register 116 interval Data register 117 Interval data register 118 Memory area 119 Interrupt processing period data storage unit 120 Correction data storage unit 121 Interrupt control device

Claims (11)

A processor for coordinating interrupt requests from a plurality of interrupt generation circuits;
An interrupt cycle determination unit that calculates a cycle of an interrupt request from each interrupt generation circuit and determines its periodicity;
For each interrupt generation circuit, a synchronization detection unit that detects whether or not the interrupt synchronization target circuit is a target that can be synchronized with the interrupt request source circuit that generated the interrupt request,
Between the interrupt request source circuit and the synchronization target circuit, an interrupt time difference detection unit that detects a time difference of next interrupt generation timing,
An interrupt processing time adjusting unit that adjusts a next interrupt generation timing that delays an interrupt processing start time of the interrupt request source circuit by the next interrupt generation timing time difference when the interrupt timing time difference is within a predetermined time; Having a processor.   The processor according to claim 1, wherein the cycle determination unit holds a predetermined number of interrupt generation times of the respective interrupt generation circuits, and sets an average obtained by excluding the maximum value therefrom as an interrupt cycle.   The cycle determination unit holds a predetermined number of interrupt generation time intervals of each interrupt generation circuit, and determines that there is no periodicity when a difference from the interrupt cycle is a predetermined number or more and outside an allowable error range. The processor described.   The processor according to claim 3, wherein the allowable error range is a processing time required for power recovery of the CPU of the processor.   The synchronization detection unit has a relationship between the interrupt generation cycle of the interrupt request source IP and a multiple or a divisor within the interrupt generation cycle within the CPU power recovery processing time and the interrupt processing period of the interrupt request source circuit. The processor according to claim 1, wherein the processor is extracted. Interrupt generation cycle T _n of the interrupt request source circuit, interrupt generation cycle of the synchronization target candidate circuit for detecting whether or not to be synchronized, T _m , CPU power recovery processing time, and interrupt processing period of the interrupt request source circuit when the period was _{T w, T} n / _T remainder the remainder of _m minus the Tm, or the remainder of the _T m / _{T n} is a remainder obtained by subtracting from the _{T n,} if _{T w} smaller than the synchronization target The processor according to claim 1, wherein the candidate circuit is a circuit to be synchronized. Said interrupt time difference detection unit when the interrupt request source IP of the interrupt generation cycle T _n, the interrupt generation period of the detection target IP of the interrupt timing time difference T _m, and the next interrupt generation time was T _m2, T _m < if T _n, the next interrupt occurrence time difference of _T m -C = T _a, the processor of any one of claims 1 to 6. Said interrupt time difference detection unit when the interrupt request source IP of the interrupt generation cycle T _n, the interrupt generation period of the detection target IP of the interrupt timing time difference T _m, and the next interrupt generation time was T _m2, T _m> If T _n, <in the case of _{T n,} the _{T m + T m2 -T n =} T a and the next interrupt occurrence time difference, _{T m2> T m2} in the case of _{T n, T m2 -T n =} T a of the next The processor according to claim 7, wherein a difference in interrupt occurrence times is set. The interrupt processing time controller, when the interrupt processing time of the CPU power switch ON processing period and interrupt request source IP was T _w, the next interrupt occurrence time difference T _A is less than T _n, interrupts larger than T _w The processor according to claim 8, wherein the processor is detected as a synchronization target whose period does not overlap. The interrupt processing time controller, said among those next interrupt occurrence time difference T _A is within the allowable error range, it extracts the largest one, the maximum of the next interrupt only occurrence time difference T _A interrupt processing delay next interrupt generation The processor according to claim 1, wherein timing adjustment is performed. A processor for coordinating interrupt requests from a plurality of interrupt generation circuits;
Calculate the interrupt request period from each interrupt generation circuit and determine its periodicity,
For each interrupt generation circuit, detect whether or not it is an interrupt synchronization target circuit that can be synchronized with the interrupt request source circuit that generated the interrupt request,
Detecting the time difference of the next interrupt generation timing between the interrupt request source circuit and the synchronization target circuit;
A method for controlling a processor, wherein when the interrupt timing time difference is within a predetermined time, the next interrupt generation timing is adjusted to delay the interrupt processing start time of the interrupt request source circuit by the next interrupt generation timing time difference.

Images