JPS6286914A - Edge detecting circuit - Google Patents

Abstract

PURPOSE:To heighten effect of reduction of the scale of the circuit by constituting the circuit of an input side frequency dividing section, an exclusive OR output section that makes respective output from the first and second 1/2 frequency divider input and an output side frequency dividing section that 1/4 divides output of the exclusive OR output section and sends out a counting completion signal. CONSTITUTION:The edge detecting circuit 10 consists of an input side frequency dividing section 11, an exclusive OR output section 12 and an output side frequency dividing section 13, and receives clock pulse CK and a trigger signal TR in the input side, and sends out a counting completion signal CT when fixed number of edges (for instance five) is counted. The input side frequency dividing section 11 consists of the first 1/2 frequency divider 14 and the second 1/2 frequency divider 15 and the two consist of D-flip-flop. The exclusive OR output section 12 is provided with at least an EXOR gate, and takes exclusive logical sum of respective output of the first and second 1/2 frequency divider 14 and 15. The output side frequency dividing section 13 is made by cascading at least the first 1/2 frequency divider 17 and the second 1/2 frequency divider 18, and forms a 1/4 frequency divider as a whole.

Description

[Detailed Description of the Invention] [Summary] This circuit outputs a counting completion signal when a predetermined number of clock pulse edges are counted immediately after receiving a trigger signal.

The configuration consists of two edges driven respectively by the first rising edge and the first falling edge of the clock pulse.
It consists of a frequency divider, a part that performs an exclusive OR on each output of these two frequency dividers, and a part that adds a χ division to the exclusive OR output.

[Industrial application field]

The present invention relates to an edge detection circuit.

This edge detection circuit is used, for example, as a control circuit within a processor and is used to determine timing. Since processors generally operate based on clock pulses, various timings are often determined by the number of clock pulses.

The circuit of the present invention is effectively used as a means for determining this timing.

[Conventional technology]

FIG. 7 is a time chart for explaining the background to which the circuit of the present invention is applied. The processor operates based on the clock pulse CK, and consists of a repetitive pulse train as shown in column 1). The operation here includes, for example, a write command from the CPU, but generally speaking, a trigger signal TR is given from the CPU. This is shown in column 2). The general sequence is that this trigger signal TR comes and a signal corresponding to it is also generated. For example, if the trigger signal TR is a write command from the CPU, a write command signal (CT) is often sent to a peripheral register after a certain period of time has passed.

This write instruction signal (CT) is shown in the 3rd column, and is generated a certain period of time after the appearance of the trigger signal TR (after counting 5 consecutive rising edges and 5 falling edges of the clock pulse). . Note that the number of edges is arbitrarily determined in system design, but is usually about 3 to 7. After all, this write instruction signal (CT) can be generally expressed as a counting completion signal, and the circuit for this counting is the work/noji detection circuit.

The conventional edge detection circuit is a so-called synchronous counter,
A predetermined number of pairs of flip-flops each detecting the rise and fall of a clock pulse are connected in series. The predetermined number is the predetermined number of clock pulse edges to be counted from the time the trigger signal TR is received until the count completion signal CT is output.

[Problem that the invention seeks to solve]

In the conventional edge detection circuit, if the predetermined number of clock pulse edges is N, at least N pairs are required, and 2N flip-flops are required. Therefore, if the fixed number N is 5, 10 flip-flops and some associated logic circuits would be required, which would increase the circuit scale.

Means for Solving Problem C] FIG. 1 is a circuit diagram showing a first example of the simplest configuration of the circuit according to the present invention. In addition, the same reference number or symbol is attached and shown to the same component throughout all the figures. The edge detection circuit 10 of the first example includes an input side frequency dividing section 11, an exclusive OR output section 12, and an output side frequency dividing section 13, receives a clock pulse CK and a trigger signal TR on the input side, and receives a constant ( When IXI edges (5 in the first example) are counted, a counting completion signal CT is sent from the output side. Note that R5T is a reset signal, and each time the counting completion signal CT is sent, the edge detection circuit 10 is activated. Used to initialize the state of each part.

The input-side frequency divider 11 includes a first frequency divider 14 and a second frequency divider 15, both of which are constructed of D-flip-flops.

The exclusive OR output section 12 outputs at least EXOI? It is provided with a gate and calculates the exclusive OR of each output of the first and second frequency dividers 14 and 15.

The output side frequency divider 13 is made up of at least a first z frequency divider 17 and a second 2 frequency divider 18 connected in series, and the overall frequency is 1/2.
Forms a 4 frequency divider. Both are constructed from D-flip-flops. Then, the output of the second frequency divider 18 is used to form a target count completion signal CT.

[For production]

The operation of the edge detection circuit 10 shown in FIG. 1 is as follows. FIG. 2 is a diagram of signal waveforms appearing in the main part of the edge detection circuit 10, and the signal waveforms in columns 1) to 7) correspond to the signals appearing in 1 to 7 in FIG. First, the trigger signal TR
(column 2), the first frequency divider 14 and the second frequency divider 15 send out the outputs shown in the column 3) and column 4), respectively. In other words, it is driven by the rising and falling edges of the clock pulse in the first column, and generates an output divided by two. Here, the first frequency divider 14 receives the trigger signal T
The second 2 frequency divider 15 is driven at the first falling edge immediately after the trigger signal TR is generated, and the second 2 frequency divider 15 is driven at the first falling edge immediately after the trigger signal TR is generated, and the 2 frequency divider 15 is driven at the first falling edge immediately after the trigger signal TR is generated. Generate divided output. Whether the drive is rising or falling is determined by the presence or absence of the inverter 16.

The signal waveform of the 5th) 41JI is obtained by exclusive ORing these 2 frequency-divided outputs (3rd) and 4) columns). The benefits of using this exclusive OR output section 12 will become clear in the second example (FIG. 3) described later.

At the time when the exclusive OR output is obtained, the first edge of the clock pulse CK has passed, and 4 steps remain.

By counting the edges, the signal CT of the fifth edge is obtained. For this purpose, there is an output-side frequency divider 13 that functions as a 1/4 frequency divider, and the first frequency divider 17 obtains the signal in column 6), which is further divided into 1/4 The frequency is divided by the unit 18 and the total is 1.
When the frequency is divided by /4, the remaining four edges are detected in the 7th column, and the output of the second frequency divider 18, which falls at this point, forms the counting completion signal CT. Here, since the desired five-way detection circuit can be realized with four flip-flops and some logic gates, there is no need to use ten flip-flops as in the prior art.

〔Example〕

FIG. 3 is a circuit diagram showing a second example of the circuit according to the present invention, in which a counting completion signal CT is output at the sixth edge of the clock pulse. This edge detection circuit 2° is designed to be a 6-edge detection circuit that outputs a signal CT at the 6th edge of a clock pulse. 12 was slightly modified to form an exclusive OR output section 22. In other words, an EXNOR gate is used.

With only such changes, it is possible to change from a 5-edge detection type to a 6-edge detection type. This is the advantage of introducing the exclusive OR output section.

FIG. 4 is a signal waveform diagram appearing in a main part of the edge detection circuit 20, and corresponds to the signal waveform diagram in FIG.

The difference from FIG. 2 is columns 5) to 7), which are shifted to the right by one clock pulse as a whole. This is because the exclusive OR output section 22 is not an EXOR gate, but an EXNO gate.
This is because the signal waveform in column 5) of FIG. 2 was inverted because the R gate was used. As a result, the counting completion signal CT is obtained at the sixth edge of the clock pulse CK (after the appearance of the signal TR).

FIG. 5 is a circuit diagram showing a third example of the circuit according to the present invention, in which a counting completion signal CT is output at the seventh edge of the clock pulse. This edge detection circuit 3° is designed to be a 7-edge detection circuit that outputs a signal CT at the 7th edge of the clock pulse, so that the output-side frequency dividing section 13 is different from the 5-edge detection circuit 10 shown in FIG. The output side frequency dividing section 33 is simply changed slightly. In other words, an inverter 32 is added. With only such changes, it is possible to change from the 5-edge detection type to the phenol edge detection type. The function of this inverter is to shift the phase.

FIG. 6 is a signal waveform diagram appearing in the main part of the edge detection circuit 3o, and corresponds to the signal waveform diagram in FIG. 2.

The difference from FIG. 2 is that the sixth
) is inverted, and as a result, the counting completion signal CT is obtained at the seventh edge of the clock pulse CK (after the appearance of the signal TR).

〔Effect of the invention〕

As explained above, whether it is 5-edge detection, 6-edge detection, or phenol edge detection, basically the input-side frequency dividing section consisting of two flip-flops and the output-side frequency dividing section consisting of two flip-flops are exclusive. The number of flip-flops can always be four. Therefore, if 7-edge detection is realized using a conventional synchronous counter,
Considering that 14 (=2×7) flips and 70 flips are required, the effect of reducing the circuit scale according to the present invention is significant.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first example of the simplest configuration of a circuit according to the present invention. 2 is a signal waveform diagram appearing in a main part of the edge detection circuit 10, FIG. 3 is a circuit diagram showing a second example of the circuit according to the present invention, and FIG. 4 is a signal waveform diagram appearing in a main part of the edge detection circuit 20. 5 is a circuit diagram showing a third example of the circuit according to the present invention. FIG. 6 is a signal waveform diagram appearing in the main part of the edge detection circuit 30. FIG. 7 is a background to which the circuit of the present invention is applied. It is a time chart for explaining. 10, 20.30... Edge detection circuit, 11... Input side frequency dividing section, 12, 22... Exclusive OR output section, 13, 33...
・Output side frequency divider, 16, 32... Inverter, CK... Clock pulse, TR... Trigger signal, CT... Counting completion signal. FIG. 2 is a signal waveform diagram appearing in the main part of the edge detection circuit 10. CK... Clock pulse TFI... Trigger signal CT... Counting completion signal FIG. 3 is a circuit diagram showing a second example of the circuit according to the present invention. 22... Exclusive OR output unit Figure 4: Signal waveform diagram appearing in essential parts of the enono detection circuit 20. Figure 5: Circuit diagram showing a third example of the circuit according to the present invention. 33... Output side frequency dividing unit. 32... Signal waveform diagram appearing in the main part of the i/part effect detection circuit 30 in Fig. 6 A time chart for explaining the background to which the circuit of the present invention is applied Fig. 7 C...Clock/Prusse TR... One signal CT...J1b completion signal

Claims (1)

[Claims] 1. A clock pulse consisting of a repetitive pulse train and a trigger signal are input, and after receiving the trigger signal, a counting completion signal indicating that a predetermined number of edges of the clock pulse has been counted is generated. The output edge detection circuit is driven by the first rising edge and the first falling edge of the clock pulse immediately after receiving the trigger signal, and is out of phase with each other by 1/2 clock pulse. The clock pulse is 1/
an input side frequency divider (11) consisting of a first 1/2 frequency divider and a second 1/2 frequency divider that generates an output divided by 2; and the first and second 1/2 frequency dividers. an exclusive OR output section (12) that receives each output from the frequency generator as input, and an output side that divides the output of the exclusive OR output section (12) into 1/4 and sends out the counting completion signal. An edge detection circuit comprising a frequency dividing section (13).