JP2693885B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a program runaway detection circuit capable of detecting a runaway even if an infinite loop is entered at any place.

[0002]

2. Description of the Related Art Microprocessors or 1-chip microcomputers (hereinafter collectively referred to as "microcomputers") have been increasing in addressability with increasing program memory space or built-in program memory capacity. It is becoming possible to perform more complicated control such as time-division control by incorporating various peripheral functions.

Along with this, there are various fields of application from familiar consumer fields such as home appliances to information processing devices, communication devices, engine control of automobiles, etc. When an abnormal operation such as a runaway occurs, it is very important to detect it as soon as possible.

Conventionally, a watchdog timer has been known as a circuit for detecting a runaway such as when a program goes into an infinite loop due to some external factor or a special condition which is unexpected at first. This watchdog timer is an interval timer that generates a interrupt signal or a reset signal to the microcomputer by counting a predetermined reference clock and overflowing at regular time intervals, and can be cleared by a program.

That is, when a series of processes in program execution is not completed within a predetermined time, this state is regarded as a program execution abnormality and an internal reset signal is generated or an interrupt signal is generated. The structure of a conventional watchdog timer is shown in FIG.

In FIG. 3, an overflow timer 50 generated after counting a predetermined time by an interval timer (watchdog timer) 1 having a predetermined bit length that counts with a reference clock as an input becomes a reset signal or an interrupt signal, and is reset to a microcomputer. It takes an interrupt.

Also, the interval timer 1 can be cleared by a clear command during the counting operation. Therefore, as shown in the program flow 70 of FIG. 4, the program 60 is correct by appropriately arranging the clear instruction in advance in the program processing routine in a shorter cycle than the interval timer (watchdog timer) 1 overflows. When the processing routine is being executed, the interval timer 1
Is cleared and the overflow signal 50 is not generated,
If for some reason the program runs away, (1) in Fig. 4
When an infinite loop is entered like this, the clear instruction is not executed, so overflow can occur, and a reset or interrupt can occur to get out of the abnormal state. Since the actual program processing routine is more complicated than that shown in FIG. 4 and branches to an interrupt processing routine from a subroutine or a peripheral function in the middle, it is necessary to place a clear instruction in consideration of these branch processing times. It is omitted for simplicity because it leaves the main line.

[0008]

In the conventional watchdog timer 1 described above, as shown in (1) of FIG.
This is effective when entering an infinite loop that does not include a clear instruction, but since the watchdog timer 1 is cleared when entering an infinite loop in the program of the part that includes the clear instruction as in (2), There is a drawback that you cannot get out of the infinite loop despite the runaway condition.

An object of the present invention is to solve the above-mentioned drawbacks and to include a command itself for clearing a watchdog timer.
It is to provide a microcomputer capable of detecting this even when entering an infinite loop.

[0010]

The configuration of a runaway detection circuit incorporated in a microcomputer of the present invention is such that a predetermined reference clock is input and a reset signal or an interrupt signal is generated after a predetermined number of clocks have been counted and a counter value is issued by a clear instruction. Is cleared, two sets of capture registers that capture the contents of the program counter based on the capture signal, and the capture signal of the program counter are alternately output to the two sets of capture registers when the clear instruction is executed. And a comparator circuit for comparing the contents of the two sets of capture registers and generating a coincidence detection signal.

[0011]

1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

Referring to FIG. 1, in this embodiment, the interval timer 1 performs counting operation based on a predetermined reference clock, and overflows 23 when the predetermined count number is exceeded.
The interval timer with a predetermined bit length that generates the count value by the clear pulse generated when the interval timer clear instruction is executed.

Cleared to [0].

The toggle flip-flop 2 receives the clear pulse generated when the interval timer clear instruction is executed and outputs the capture signals 20 and 22 from the outputs Q and Q (inverted value).

The first capture register 4 has the Q output of the toggle flip-flop 2

It is a register that latches the contents of the program counter 3 when changing from [0] to [1], and the second capture register 5 outputs the Q (inverted value) of the toggle flip-flop 2.

It is a register that latches the contents of the program counter 3 when changing from [0] to [1].

In this embodiment, each of the program counter 3, the first capture register 4, and the second capture register 5 has a 16-bit length.

The comparison circuit 6 compares all the bits of the contents of the first capture register 4 and the contents of the second capture register 5 and generates a match detection pulse 21 when they match.

The OR gate 7 outputs a reset signal or an interrupt signal 24 of the microcomputer when the overflow 23 of the interval timer 1 occurs or the coincidence detection pulse 21 of the comparison circuit 6 occurs.

Further, the count value of the interval timer 1 is changed by the reset signal to the microcomputer.

Cleared to [0], the Q output of toggle flip-flop 2 is

The Q (inverted value) output is initialized to [1] at [0], and the first capture register 4 is reset at the time of reset.
Irrespective of the contents of the second capture register 5 and

[0] is output and the coincidence detection pulse 21 is not output.

Next, the execution of the program will be described with reference to FIG.

To simplify the explanation, it is assumed that a series of processes is repeated in the flow of program execution as shown by the arrow in FIG. At this time, a clear instruction for the interval timer 1 is placed at a time interval within the overflow time T of the interval timer 1 in FIG. For example, in the normal state as shown in FIG. 4, if the intervals A, B, C, and D are accessed in this order within the time T, an interval timer clear instruction is placed at each address.

The interval timer 1 is cleared by a reset input to the microcomputer. When the microcomputer executes the program in the normal sequence, when the clear instruction of the interval timer 1 at the address A is executed, the interval timer 1 is cleared and at the same time the Q output of the toggle flip-flop 2 is output.

Since the value changes from [0] to [1], the address A data, which is the content of the program counter 3, is captured in the first capture register 4.

On the other hand, the Q (inverted value) output of the toggle flip-flop 2 is from [1].

Due to the change to [0], the contents of the program counter 3 are not captured in the second capture register 5, so the comparison circuit 6 does not detect a match,

[0] Output remains.

Next, when address B is executed within the time interval T, the interval timer 1 is cleared and the Q (inverted value) output of the toggle flip-flop 2 is output.

Since the value changes from [0] to [1], the address B data, which is the content of the program counter 3, is latched in the second capture register 5, but the previous address A data is latched in the first capture register 4. Since the comparison circuit 6 does not detect the coincidence, the reset signal is not generated through the gate 7.

After that, when the address C → D is normally executed, the contents of the program counter are alternately latched in the first and second capture registers 5, so that the coincidence detection pulse 21 of the comparison circuit 6 is not generated. Then, after returning to the beginning of the program, the counter clear instruction at the address A is executed, and the above operation is repeated.

Next, a case where an infinite loop such as (1) shown in FIG. 4 is entered after the execution of addresses A and B will be described. In this case, since the clear command is not executed within the time T, the overflow 23 of the interval timer 1
As a result, a reset signal or interrupt signal 24 is generated via the OR gate 7 to detect an abnormality.

Further, (2) in FIG. 4 which is a drawback of the conventional example.
When entering the infinite loop like the above, the overflow 23 of the interval timer 1 does not occur, but the C address data is captured in the first capture register 4 at the first execution of the C address, and at the second execution of the C address. When the address C data is captured in the second capture register 5 and the comparison circuit 6 generates the coincidence detection pulse 21, a reset signal or an interrupt signal 24 is generated via the OR gate 7 and abnormality is detected.

FIG. 2 is a block diagram showing a microcomputer of the second embodiment of the present invention.

In FIG. 2, this embodiment is a second embodiment in which a counter 9 for counting the output of the coincidence detection pulse 21 of the comparison circuit 8 is added.

The counter 9 counts the coincidence detection pulse 21 from the comparison circuit 8 and, when an overflow 25 occurs, generates a reset signal or an interrupt signal 24 via the OR gate 7. Further, the content of the counter 9 is cleared by the signal indicating the disagreement from the comparison circuit 8.

Therefore, for example, the counter 9 is replaced by the comparison circuit 8
If a 4-bit binary counter that counts up each time the coincidence detection pulse 21 from is input, when the loop shown in (2) of FIG. 4 is entered, when the 16th coincidence detection pulse 21 is input. An overflow signal is generated, and a reset signal or interrupt signal 24 is generated via the OR gate 7.

That is, the first embodiment is actually suitable for the case where it is judged that the program is out of control at the time when the clear instruction of the same address is continuously executed, whereas the second embodiment is
The embodiment is suitable for the case where it is judged as abnormal when it is executed a plurality of times in succession. Furthermore, if the counter 9 is configured as a programmable counter so that the overflow 25 occurs at the time when a desired count value is counted, it is possible to design a program corresponding to more systems.

In each of the above embodiments, the program counter 3 is shown to have a 16-bit length, but it goes without saying that it is not limited to this. The reference clock of the interval timer 1 may also be selected from a plurality of types.

[0033]

As described above, the present invention is provided with two sets of capture registers for capturing the contents of the program counter when an instruction for clearing the interval timer (watchdog timer) is executed, and each set has a capture register for executing the clear instruction. By alternately capturing the contents of the program counter in the capture register of No. 2 and comparing the contents of two sets of capture registers to detect a match, it is possible to detect a program abnormal loop including the interval timer clear instruction itself. Compared with the conventional simple watchdog timer, it has the effect of being able to reliably detect program execution abnormalities.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a conventional watchdog timer.

FIG. 4 is a flowchart illustrating runaway detection by a conventional watchdog timer and each embodiment.

[Explanation of symbols]

 1 Interval Timer 2 Toggle Flip Flop 3 Program Counter 4 First Capture Register 5 Second Capture Register 6, 8 Comparison Circuit 7 OR Gate 9 Counter 20, 22 Capture Signal 21 Match Detection Pulse 23, 25 Overflow 24 Reset Signal or Interrupt Signal 50 Overflow signal 60 Program 70 Program flow

Claims (2)

(57) [Claims] 1. An interval timer that generates a reset signal or an interrupt signal after counting a predetermined number of clocks with a predetermined reference clock as an input and a counter value is cleared by a clear instruction, and captures the contents of a program counter based on a capture signal. 2 sets of capture registers, a means for alternately outputting the capture signal of the program counter to the 2 sets of capture registers when the clear instruction is executed, and a match detection signal for comparing the contents of the 2 sets of capture registers. A microcomputer characterized by being provided with a runaway detection circuit having a comparison circuit for generating 2. The microcomputer according to claim 1, wherein the means for alternately outputting is a toggle flip-flop to which a pulse generated when a clear instruction is executed is input.