JP2516711B2 - Watchdog timer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer device which generates a system reset signal when a microprocessor or the like runs out of control.

[0002]

2. Description of the Related Art In a microcomputer system, a CPU controls and processes according to a predetermined program. However, if the proper program cannot be executed due to some trouble, so-called CPU runaway occurs.

Therefore, a so-called watchdog timer device is used to determine such a runaway and automatically return the CPU.

FIG. 2 shows the configuration of a conventional watchdog timer device 10. In this conventional example,
The watchdog timer device 10 includes a binary counter 1
It is composed of two. A predetermined clock 100 is input to the binary counter 12, and the binary counter 12 counts the input clock 100, and when the count value reaches a predetermined system reset execution value. The system reset signal 102 is generated.

Such a system reset signal is shown in FIG.
Is input to a predetermined terminal of the CPU 11 as shown in FIG. On the other hand, the CPU 11 outputs a counter reset signal 104 to the binary counter 12 at a predetermined cycle with a certain time width in accordance with a predetermined reset routine incorporated in the software, whereby the binary counter 12 is reset. The binary counter 12 is reset almost regularly during normal CPU execution. Then, for example, when the CPU 11 runs out of control, such a counter reset signal 10
As 4 is not output periodically, as described above,
A system reset signal 102 is output from the binary counter 12 to the CPU 11, and as a result, the CPU 11
Will be reset and the system will generally return to its initial state.

[0006]

However, in the conventional watchdog timer device shown in FIG. 2, the counter reset signal 104 is output every certain period even if the CPU 11 is performing an abnormal operation. In this case, there is a problem that the watchdog timer device 10 cannot judge it. That is, when the counter reset signal 104 is output within a shorter period than the normal output interval, there is a problem that the runaway of the CPU 11 cannot be determined.

The present invention has been made in view of the above conventional problems, and an object thereof is to provide a watchdog timer capable of judging a system abnormality such that a counter reset signal occurs in a cycle shorter than usual. To provide a device.

[0008]

In order to achieve the above object, the present invention is an n-stage binary counter which counts a predetermined clock and is reset by a count reset signal input almost regularly. When the count value reaches a predetermined system reset execution value,
A binary counter that outputs a system reset signal from the n-th highest-order output terminal, and the binary counter
Predetermined among the remaining output terminals except the nth output terminal of
Commonly connected to m output terminals.
The value indicated by the m signals output from the counter is reset
Judgment value set to judge the abnormality that the interval becomes shorter
1st AND that outputs a signal within the determination period until the
Circuit, the signal within the judgment period is input, and
If the system reset signal is input,
And a second AND circuit that outputs a set signal .

[0009]

According to the above construction, the judgment means can judge whether the count reset interval is normal or not. Then, when the count reset interval becomes abnormal, a system reset signal can be generated by the abnormality determination circuit. Therefore, there is an advantage that it is possible to detect a system abnormality that could not be determined in the past. Also, in the present invention, a single binary counter
Can be made to function like two timers,
The configuration of the watchdog timer device can be simplified and
There is an advantage that the size can be reduced. Furthermore, the first Anne
The number of n output terminals connected to the circuit
Error that shortens the count reset interval by
The advantage that you can easily increase or decrease the judgment value for judging
There is also. In addition, according to the present invention, the second AND circuit is provided.
The count reset signal as it is
It has the advantage that it can be used as a set signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a watchdog timer device according to the present invention. The clock 100 is input to the binary counter 14 including 13 stages, such as a flip-flop, as in the conventional case. Then, this binary counter 14 has its clock 100
Is counted, and when it reaches a predetermined system reset execution value, that is, when it is counted up to 2 ¹² , the system reset signal 102 is output as in the conventional case.

A counter reset signal 104 is input to the binary counter 14 as in the conventional case.

In the figure, reference numeral 16 is a circuit for detecting a count reset interval abnormality. This circuit 16 is an AND circuit 18 having four input terminals in this embodiment, an output signal of the AND circuit 18 and the counter. The AND circuit 20 receives the reset signal 104, and the OR circuit 22 receives the output of the AND circuit and the output of the binary counter 14.

The AND circuit 18 has binary counters Q (bar) _{8 to} Q (bar) at its four input terminals, respectively.
₁₁ signals are being input. These are output from the Q (bar) terminal of the flip-flop that constitutes the binary counter 14.

Therefore, in the binary counter 14,
If the count value is 2 ⁸ or more, Q (bar) ₈ ~
"0" will be output from either terminal of Q (bar) ₁₁ . When this "0" is output, the output of the AND circuit 18 also becomes "0", and as a result, the AND circuit 2 receiving the counter reset signal 104 is input.
Gate 0 will close. Where AND circuit 1
The output of 8 corresponds to the signal within the determination period. You
That is, when the signal within the judgment period is 1, it is during reset
It is within the judgment period for judging the abnormality that the gap becomes shorter,
If the signal within the determination period is 0, it is outside the determination period.
It

On the contrary, when the count value of the binary counter 14 is less than 2 ⁸ , the AND circuit 18 outputs "1", and as a result, the AND gate 20 is opened. When the counter reset signal 104 is obtained in that state, the signal 104 is output to the OR circuit 22. That is, the system reset signal 102 is generated.

That is, this circuit 16 directly outputs the counter reset signal 104 to the system reset signal 10 when the counter reset signal 104 is obtained at a time other than the normal time which is predetermined for the count reset interval.
It is output as 2. Of course, AND circuit 1
By increasing or decreasing the number of output lines input to 8, the normal determination period for the interval of the counter reset signal can be changed .

According to the above watchdog timer device, even when the CPU performs a defective operation and a normal counter reset signal is not output, for example, such a defective operation is accurately determined and the CPU is reset. It becomes possible to execute such as. It should be noted that the configuration is also suitable for detecting the case where the counter reset signal 104 is continuously output.

[0019]

As described above, according to the present invention,
It is possible to judge a case where the counter reset interval is abnormal, and to judge a malfunction of the system, which could not be judged in the past. Therefore, it is possible to construct a highly reliable system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a watchdog timer device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional watchdog timer device.

[Explanation of symbols]

 14 binary counter 16 count reset interval abnormality determination circuit 100 clock 102 system reset signal 104 counter reset signal

Claims (1)

(57) [Claims] 1. An n-stage binary counter , which counts a predetermined clock and is reset by a count reset signal input almost regularly, the count value of which is a predetermined system reset execution. its when it reaches the value
From the n-th stage output terminals of the top-level and the binary counter for outputting a system reset signal, the remaining except for the n-th stage output terminals of said binary counter
Among the output terminals, it is commonly connected to the predetermined m output terminals,
Values indicated by m signals output from the m output terminals
However, it is necessary to judge the abnormality that the count reset interval becomes short
Signal within the judgment period until the judgment value set for
The first AND circuit for outputting and the signal within the determination period are input, and the count reset
System reset signal when a reset signal is input.
A second AND circuit for outputting a signal, and a watchdog timer device.