JPH04332056A - Microcomputer - Google Patents

Abstract

PURPOSE:To detect a program runaway state such as an infinite loop in a microcomputer. CONSTITUTION:The microcomputer is provided with an interval timer 4 for counting up clocks 106, and after counting the prescribed number of clocks, outputting an overflow signal 107 including a reset signal or an interruption signal and to be cleared at its counter value by a clear signal 105 and a clear signal generating circuit 1 for outputting the clear signal 105 when the 1st and 2nd clear instructions 101, 102 are alternately executed and inhibiting the generation of a clear signal when the same clear instruction is continuously executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to microcomputers.

0002

2. Description of the Related Art In microcomputers, including microprocessors and one-chip microcomputers, as the degree of integration increases year by year, the addressable program memory space or built-in program memory capacity increases, and various peripheral functions are built-in. It is becoming possible to perform increasingly complex control, such as time-sharing control. In addition, the field of application is wide-ranging, from familiar consumer fields such as home appliances to information processing equipment, communication equipment, and automobile engine controls.
If the microcomputer program that is the center of these controls malfunctions, such as going out of control,
It is becoming very important to detect this as early as possible.

Conventionally, a watchdog timer has been known as a circuit that detects when a program goes out of control, such as entering an infinite loop, due to some external factor or an unexpected special condition. The watchdog timer is an interval timer that counts a predetermined clock source and generates an interrupt or reset signal to the microcomputer by overflowing at regular intervals, and can be cleared by a program. That is, if a series of processes in program execution are not completed within a predetermined time, this circuit has a function of regarding this state as a program execution abnormality and generating an interrupt signal or an internal reset signal. FIG. 4 shows the configuration of a conventional watchdog timer.

In FIG. 4, the interval timer 5 is
The watchdog timer has a predetermined bit length and counts by inputting a clock 107. An overflow signal 109 is output as an interrupt signal or a reset signal, and interrupts or resets the microcomputer. Further, the interval timer 5 is cleared when a clear command 108 is input during the counting operation. Therefore, as shown in the program flowcharts of FIGS. 5(a) and (b), during the program processing routine,
Clear commands 301 and 30 are executed at a shorter period than the interval timer (watchdog timer) overflows.
By arranging 2, 303 and 304 appropriately, if the program is being executed with the correct processing routine, these clear instructions will clear the interval timer and no overflow will occur, but if for some reason the program If the process goes out of control and enters an infinite loop as shown in (2) in FIG. 5(b), an overflow occurs because the clear instruction is not executed, and an interrupt or reset occurs to escape from the abnormal state. The actual program processing routine is more complex than the processing routine example shown in Figure 5(b), and branches to subroutines and interrupt processing routines from peripheral functions, etc., so the processing time for these branches should also be taken into account. It is necessary to place a clear command, but this is omitted for the sake of simplicity as it departs from the main topic.

[0005]

[Problems to be Solved by the Invention] The anti-runaway function of the watchdog timer in the conventional microcomputer described above is such that when the watchdog timer enters an infinite loop that does not include a clear instruction, as shown in Figure 5(b), is valid, but
If a part of the program that includes a clear instruction enters an infinite loop, as shown in ■ in Figure 5(b), the watchdog timer will be cleared, so it will not be possible to escape from the infinite loop despite the runaway state. There is a drawback.

[0006]

[Means for Solving the Problems] A microcomputer of the present invention receives a predetermined clock source as input, generates a reset signal or an interrupt signal after counting a predetermined number of clocks, and provides an interval at which a counter value is cleared by a predetermined clear signal. Generates the clear signal when a timer and a predetermined first clear command and second clear command are executed alternately, and does not generate the clear signal even if the same clear command is executed continuously. and a clear signal generation circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the interval timer 4 is an interval timer with a predetermined bit length that performs a counting operation based on a predetermined clock 106 and generates an overflow signal 107 when the predetermined count number is exceeded. Latch 2 is set by a clear command (1) 101 input to the S terminal, and cleared by a clear command (2) 102 input to the R terminal to determine whether the state of latch 2 is set or cleared. An output signal 104 indicating this is output from the Q terminal. The pulse generating circuit 3 detects the rising and falling edges of the output signal 104 output from the Q terminal of the latch 2, and generates and outputs a clear signal 105 for the interval timer 4. And these latches 2
and pulse generation circuit 3, clear signal generation circuit 1
is formed.

Furthermore, in the case of a reset to start processing of the microcomputer, or when the interval timer 4 overflows and an interrupt occurs, the latch 2 is activated in response to the input of the reset signal/interrupt signal 103. Cleared and initialized.

Next, FIGS. 2(a) and (b) and FIG. 3(
Execution of the program will be explained based on a), (b), (c), and (d). To simplify the explanation,
It is assumed that a series of processes can be repeated in the flow of program execution as shown by the arrows in FIG. 2(a). At this time, Figure 1
Overflow time T of interval timer 4 at
A clear command (1) 201 and a clear command (2) 202 are placed at a time interval of less than or equal to the time interval. For example, as shown in FIG. 2(a), in a normal state, address A→address B→address C→address D→address A is accessed in this order within the time T at each interval. As shown in (b), clear instructions (1) 201 and 203 are placed at addresses A and C, and clear instructions (2) 202 and 20 are placed at addresses B and D.
Place 4. In response to a reset input to the microcomputer, a reset signal 103 is input to the latch 2 and initialized. Further, all the count values of interval 4 are cleared by the reset signal 103. When the microcomputer operates normally and executes the program in the normal sequence, first execute the clear instruction (1) 201 placed at address A, then the Q of latch 2 will be cleared.
The output signal 104 of the terminal is set to "1", and the rising edge of the output signal 104 is detected by the pulse generating circuit 3 to generate the clear signal 105, and the interval 4 is cleared. Next, a clear instruction (
2) By executing 202, the output signal 104 of latch 2 is cleared to "0", and the output signal 10 of latch 2 is cleared to "0".
The falling edge of interval 4 is detected by the pulse generating circuit 3, and a clear signal 105 for interval 4 is generated. Similarly, the above-described operation is repeated sequentially for address C, address D, address A, and so on.

Next, after executing the A address and B address, FIG.
The case where an infinite loop like ■ shown in b) is entered will be explained. After executing address A and address B, latch 2
The output signal 104 of is "0". In this state, if an infinite loop like ■ in Figure 2(b) is entered, no clear instruction will be executed even after time T has elapsed, so an interrupt or reset will occur due to the overflow of interval 4. , an abnormal operation is detected.

Next, using the timing diagrams shown in FIGS. 3(a), (b), (c), and (d), we will explain the case where an infinite loop like ■ in FIG. 2(b) is entered. do. If an abnormality occurs in program execution after executing a normal sequence of addresses A, B, and C, and the program enters an infinite loop containing address C, the conventional watchdog timer would The cleared command is executed and
No operational abnormality was detected.

In this embodiment, if a similar abnormality occurs in the execution of the program, FIGS. 3(a), (b), and (c)
) and (d), the output signal 104 of the latch 2 is set to "1" by the clear signal (1) generated by the clear instruction (1) 203 for address C that was executed immediately before. In an abnormal program sequence, the instruction at address C will be repeated many times in this state. That is, an instruction to set the output signal 104 of latch 2 to "1" is executed. However, latch 2 is already “
1”, the output signal of latch 2 is 10.
4 does not change, and the pulse generating circuit 3 does not generate the clear signal 105 for the interval timer 4, as shown in FIG. 3(d). Therefore, the interval time is, as shown in FIGS. 3(a) and (d),
Since it is not cleared within time T, an overflow occurs and an overflow signal 107 is output.
An operational abnormality is detected.

[0013]

[Effects of the Invention] As explained above, when clearing the interval timer (watchdog timer) of the present invention, the interval timer is not cleared unless the first clear command and the second clear command are executed alternately. In order to do this, a latch for storing the previous clear command and a pulse generation circuit that generates a clear signal when the contents of the latch change are added to the conventional watchdog timer. This has the effect that infinite program loops can be detected more reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing the flow of a program in this embodiment.

FIG. 3 is a timing chart of signals in this embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing the flow of a program in a conventional example.

[Explanation of symbols]

1 Clear signal generation circuit 2 Latch 3 Pulse generation circuit 4, 5 Interval timer

Claims (1)

[Claims] [Claim 1] With a predetermined clock source as input,
When an interval timer generates a reset signal or an interrupt signal after counting a predetermined number of clocks and the counter value is cleared by a predetermined clear signal, and a predetermined first clear instruction and second clear instruction are executed alternately. A microcomputer comprising: a clear signal generating circuit that generates the clear signal and does not generate the clear signal even if the same clear command is successively executed.