JP2984522B2 - Circuit verification system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit verification system, and more particularly to a circuit verification system for verifying whether or not a malfunction may occur due to the timing of a signal input to a predetermined circuit.

[0002]

2. Description of the Related Art A unit gate such as a flip-flop or a NAND gate, which has at least one input terminal and an output terminal, processes a signal input to these input terminals in a predetermined unit, and outputs the processed signal from an output terminal. A circuit that connects a plurality of circuits to each other, performs predetermined processing on a signal input from at least one external input terminal, and outputs a processing result from an external output terminal,
In a conventional circuit verification system for verifying whether or not a malfunction may occur, generally, each unit gate circuit of the circuit (hereinafter referred to as a circuit to be verified) is A signal test pattern is designed and created so that the operation of the circuit becomes critical, a delay simulation is performed using the test pattern, and then a timing simulation is further performed on the flip-flop.

In this example (first example), after a delay simulation is performed, a timing simulation is further performed on a flip-flop, which is troublesome twice and takes a long time for the timing simulation. And efficient circuit verification and circuit design could not be performed.

In order to solve this problem, a timing verification circuit capable of verifying the timing of a signal input to the flip-flop to be verified is provided in parallel with the flip-flop to be verified. There is an example in which the timing of a loop can be considered (for example,
17371).

FIG. 4 is a circuit diagram of a timing verification circuit of a circuit verification system for performing timing verification of a flip-flop simultaneously with a delay simulation and its peripheral circuits, and FIG. 5 is a timing chart of signals of various parts of the timing verification circuit.

[0006] The timing verification circuit 20 of this circuit verification system (second example) includes a flip-flop 1 to be verified.
A clock signal CK4 having a frequency four times the frequency of the clock signal CK1 input to the clock signal input terminal C
K, a set signal S, a reset signal R, and data D1 to the flip-flop 10a are input to a data input terminal D.
And flip-flops FF1, which are input corresponding to
FF2, FF3 and these flip-flops FF1, F
EX- which takes the exclusive OR (EX-OR) of the output Q of each of F2 and FF3 and the input signal to the data input terminal D
OR gates EOG1 to EOG3, a clock signal CK1, a clock signal CK2 having twice the frequency of the clock signal CK1, and EX-OR gates EOG1 to EOG, respectively.
A that inputs different ones of the three output signals
The configuration includes ND gates AG1 to AG3.

The rising timing t of the clock signal CK1
In contrast, when the data D1 rises at the timing of t2, the output Q of the flip-flop FF3 rises in synchronization with the rising of the clock signal CK4 at the timing of t3. An EX-OR gate EOG3 is generated by this signal and data D1.
Generates a pulse having a short pulse width. Further, the output of the EX-OR gate EOG3 and the clock signal CK
It can be verified that a spike-like pulse is generated at the external output terminal at the output terminal of the three-input AND gate AG3 by 1 and CK2, and that spike noise due to critical operation timing is generated. Further, when the data D1 rises at the timing of t4, no spike-like pulse is generated from the output terminal of the AND gate AG3, which indicates that there is no problem in timing.

[0008]

In the first example, the above-described conventional circuit verification system is configured to perform a delay simulation using a test pattern and then perform a timing simulation on a flip-flop. There is a problem that it takes time and time to perform the timing simulation, which makes it difficult to perform efficient circuit verification and circuit design. In the second example, a timing verification circuit is provided in parallel with the flip-flop to be verified. Since the timing of the lever flip-flop is verified at the same time as the delay simulation using the test pattern, the efficiency of circuit verification and circuit design is considerably improved, but the delay simulation using the test pattern still remains. Pattern design, delay It takes a long time to run, such as the simulation, circuit verification, there is a problem that the completion of the circuit design is delayed.

An object of the present invention is to design a test pattern,
An object of the present invention is to provide a circuit verification system capable of performing circuit verification and circuit design in a short time without the necessity of preparation.

[0010]

A circuit verification system according to the present invention has at least one input terminal and at least one output terminal, performs predetermined unit processing on a signal input to the input terminal, and outputs the processed signal from the output terminal. Verification for connecting a plurality of unit gate circuits to each other, performing predetermined processing on a signal input from at least one external input terminal, and outputting a processing result from the external output terminal, in a predetermined form, a verification target circuit Target circuit input means, clock signal identification means for identifying what clock signal is used for the circuit to be verified, and clock signals for all input signals and generated signals of the circuit to be verified. A synchronization check means for checking which of the signals is synchronized, and an external input from a predetermined input terminal of a predetermined unit gate circuit of the circuit to be verified. A signal path deriving unit that traces a signal path in the direction of the force terminal and derives all signal paths, and stores data of a spike occurrence possibility circuit that is recognized in advance as a possibility of spike noise under predetermined conditions. The storage means for performing the above-mentioned operation, referring to the data of the spike occurrence possibility circuit of the storage means and the result of the check by the synchronization check means for the signal path of the input terminal of the predetermined unit gate circuit of the circuit to be verified. Has a determining means for determining whether or not a spike noise occurrence possibility circuit exists, and an output means for outputting a determination result by the determining means.

Further, the determination means refers to the data stored in the storage means, and the circuit and the terminal which have reached the signal path to the predetermined input terminal of the predetermined unit gate circuit are external input terminals, and the external input terminal is If the input terminal of the unit gate circuit of this signal path is not for inputting a set signal or reset signal, and the input terminal of the unit gate circuit is not for a clock signal input and the input terminal is an intermediate unit gate circuit, a clock signal is supplied to this unit gate circuit. When there is an input and this clock signal and other data inputs and signal inputs are synchronized with the same clock signal, there is no clock signal input to the intermediate unit gate circuit, and two or more of the input signals become the same clock signal. When synchronized and one of these input signals is not a clock signal, the clock signal input to said intermediate unit gate circuit. If two or more of the input signals are not synchronous signals of the same clock signal and the input terminals of the unit gate circuit in this signal path are not for set signal input and reset signal input, spike noise may occur in these circuits and terminals. The circuit is configured to be determined.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a circuit to be verified includes, for example, names of unit gate circuits, input terminals and output terminals of each unit gate circuit, names of input signals, names of output signals, connection relationships between unit gate circuits, and the like. And a clock signal for identifying which clock signal is used in the circuit to be verified from the data of the circuit to be verified input by the circuit input unit 1 to be verified. Identification means 2; synchronization checking means 3 for checking which input signal of the circuit to be verified and all the signals generated in the circuit are synchronized with the clock signal; A signal path is traced back from a predetermined input terminal (for example, a clock signal input, a set signal reset signal) of a predetermined unit gate circuit to an external input terminal. And a signal path deriving unit for deriving a signal path of the above, and data of a spike noise generation possibility circuit which is recognized in advance that spike noise may be generated when input signals, clock signals, synchronization relations, etc. are under predetermined conditions. These signals are referred to by referring to the data of the spike noise generation possibility circuit of the storage unit 5 and the check result of the synchronization check unit 3 with respect to the signal path of the predetermined input terminal of the unit gate circuit of the circuit to be verified. A spike generating circuit presence / absence determining unit 6 for determining whether or not a spike noise generation possibility circuit exists in the path; and a determination result output unit 7 for outputting a determination result by the spike generating circuit presence / absence determining unit 6. Configuration.

As a spike noise generation possibility circuit,
A circuit that has reached the signal path to a predetermined input terminal of a predetermined unit gate circuit, the terminal is an external input terminal, and this external input terminal is not for inputting a clock signal, and the input terminal of the unit gate circuit is for inputting a set signal. A circuit not for reset signal input, a unit gate circuit in the middle, a clock signal input to this unit gate circuit, and the clock signal and other data inputs and signal inputs are synchronized with the same clock signal, an intermediate circuit Has no clock signal input to its unit gate circuit, two or more of the input signals are synchronized with the same clock signal, and one of these input signals
One is not a clock signal, the intermediate unit gate circuit does not have a clock signal input, two or more of the input signals are not synchronous signals of the same clock signal, and the input terminal of the first unit gate circuit in this signal path is for a set signal input , And a circuit not for reset signal input.

Next, the operation of this embodiment will be described.

First, after inputting various data of the circuit to be verified, what clock signal is used for the circuit to be verified is identified, and the input signal and the intermediate generated signal are synchronized with any of the clocks. Investigate whether it is. On the other hand, a signal path is traced from a predetermined input terminal of a predetermined unit gate circuit of the circuit to be verified toward an external input terminal, and all signal paths are derived. The circuit path verification is performed on the derived signal path by the spike generation circuit presence / absence determination means 6 based on the result of the check by the synchronization check means 3 and the data of the spike noise generation possibility circuit in the storage unit 5.

FIG. 2 is a flowchart for explaining a circuit verification procedure by the presence / absence determination means 6 of the spike generation circuit.

First, if the circuit and terminal that arrived along the signal path are external input terminals and the input signal is a clock signal, it is determined that the circuit is normal (S1, S2). This is to determine the case where the clock signal is directly input to the terminal to be verified. If the input terminal is an external input terminal and the input signal is not a clock signal, and the terminal to be verified is for a set signal input or a reset signal input, the circuit is determined to be a normal circuit; (S1 to S
3). This is to determine the case where a signal not synchronized with the clock signal is directly input to the terminal to be verified.

Instead of an external input terminal (unit gate circuit),
If the unit gate circuit has a clock terminal and the signals at the data terminal and the clock terminal are not the same clock synchronization signal, it is determined that the circuit is normal (S5, S6). If the signals at the data terminal and the clock terminal are the same clock synchronization signal, the circuit is determined to be a spike noise generation possibility circuit (S5, S6). That is, when the signals at the data terminal and the clock terminal are in-phase, spike noise is generated at the output and the spike noise is input to the verification target terminal.

If there is no clock terminal in the unit gate circuit, and if all the input terminals are the same signal, the signal path goes back to the circuit one stage before (S5, S7, S11), and step S1 is performed.
And the same procedure is repeated. When all input terminals are not the same signal, two or more of the input signals are two or more of the same clock synchronizing signal. If one of them is a clock signal, a normal circuit (S7, S8, S9) is generated. Judge as a possibility circuit. This is because when a signal synchronized with the clock signal is input to the combinational circuit,
It is determined whether a spike noise is generated in the output and the spike noise is input to the verification target terminal.

If two or more of the input signals are not the same clock synchronizing signal and the terminals to be verified are for set signal input and reset signal input, the signal path goes back to the unit gate circuit of the previous stage (S8, S10), the same procedure is repeated from step S1. If 2.8, which is a set / reset terminal as a verification terminal, is NO, the circuit is determined to be a spike occurrence possibility circuit. This determines when a signal that is not clock synchronized is input to the clock terminal.

FIGS. 3 (a) and 3 (b) are a specific circuit diagram of a circuit to be verified and a timing chart of signals of respective parts thereof, which are verified by this embodiment.

The clock terminal CK of the flip-flop 10 to be verified is set as a verification start point. First, the buffer circuit 11 arriving back along the signal path is not an external input terminal, but has no clock terminal at the input terminal and all input terminals have the same signal. move on. The two-input AND gate 12 is not an external input terminal, the input terminal has no clock terminal, all input terminals are not the same signal, and two of the input signals A and B are the same clock synchronization signal, and they are not clock signals. Therefore, the circuit is determined to be a spike noise generation possibility circuit.

When the input signals A and B change from "0" to "1" and "1" to "0" in synchronization with the same clock, respectively,
The output C of the AND gate 12 generates a spike-like pulse. This spike-like pulse appears at the output of the buffer circuit 11, and the clock terminal C of the flip-flop 10
K, the value of the data terminal D cannot be held correctly, and the output value (OUT) becomes undefined.

In this embodiment, since delay simulation and timing simulation are not performed, there is no need to design or create a test pattern, and it is possible to quickly feed back circuit design by circuit verification. The design period can be shortened.

[0027]

As described above, according to the present invention, whether or not a spike noise generation possibility circuit exists in each signal path of a circuit to be verified is preset and stored with various data of the circuit to be verified. With the configuration in which the determination is made based on the data of the spike noise generation possibility circuit thus performed, the delay simulation and the timing simulation using the test pattern as in the conventional example are not required, and the design and creation of the test pattern are not required. In addition, since the feedback of the circuit verification can be promptly made to the circuit design, there is an effect that the circuit verification and the circuit design can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an operation flowchart of a spike generation circuit presence / absence determination means for explaining the operation of the embodiment shown in FIG. 1;

3 is a specific circuit diagram of a circuit to be verified by the embodiment shown in FIG. 1 and a timing diagram of signals of respective parts thereof;

FIG. 4 is a circuit diagram of a timing verification circuit of a conventional circuit verification system and peripheral circuits thereof.

FIG. 5 is a timing chart of the timing verification circuit shown in FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 verification target circuit input unit 2 clock signal identification unit 3 synchronization check unit 4 signal path derivation unit 5 storage unit 6 presence / absence determination unit of spike generation circuit 7 determination result output unit 10, 10a flip-flop to be verified 11 buffer circuit 12 AND gate 20 Timing verification circuit

Claims (2)

(57) [Claims] 1. A plurality of unit gate circuits each having at least one input terminal and an output terminal, performing predetermined unit processing on a signal input to the input terminal, and outputting from the output terminal, connecting at least one Verification target circuit input means for performing a predetermined process on a signal input from the external input terminal and inputting a verification target circuit that outputs the processing result from the external output terminal in a predetermined form, and the verification target circuit. Clock signal identification means for identifying what clock signal is used, and synchronization for investigating to which of the clock signals these signals are synchronized with respect to all input signals and generated signals of the circuit to be verified. Investigating means, and all signals along a signal path from a predetermined input terminal of a predetermined unit gate circuit of the circuit to be verified toward an external input terminal. Signal path deriving means for deriving a path, storage means for storing data of a spike occurrence possibility circuit recognized in advance that there is a possibility that spike noise may occur under predetermined conditions, and a predetermined condition of the circuit to be verified. Referring to the data of the spike occurrence possibility circuit of the storage means and the check result by the synchronization check means for the signal path of the input terminal of the unit gate circuit, whether or not the spike noise occurrence possibility circuit exists in these signal paths A circuit verification system comprising: a determination unit that determines the state of the circuit; and an output unit that outputs a result of the determination by the determination unit. 2. A circuit in which a determination means refers to data stored in a storage means and traces a signal path to a predetermined input terminal of a predetermined unit gate circuit and a terminal is an external input terminal, and the external input terminal is If the input terminal of the unit gate circuit of this signal path is not for inputting a set signal or reset signal, and the input terminal of the unit gate circuit is not for a clock signal input and the input terminal is an intermediate unit gate circuit, a clock signal is supplied to this unit gate circuit. When there is an input and this clock signal and other data inputs and signal inputs are synchronized with the same clock signal, there is no clock signal input to the intermediate unit gate circuit, and two or more of the input signals become the same clock signal. When synchronized and one of these input signals is not a clock signal, there is no clock signal input to the intermediate unit gate circuit. If two or more of the input signals are not synchronous signals of the same clock signal and the input terminals of the unit gate circuit on this signal path are not for set signal input or reset signal input, these circuits and terminals may be spike noise generating circuits. The circuit verification system according to claim 1, wherein the circuit verification system is configured to judge.