JP4186559B2 - Scan flip-flop - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a scan flip-flop, and more particularly to a scan flip-flop used in scan design for facilitating LSI testing.
[0002]
[Prior art]
Conventionally, a plurality of flip-flops in a semiconductor integrated circuit such as an LSI are connected like a shift register (this is called a “scan chain” or “scan path”), and a test signal is input from an external terminal to generate a logic circuit A technique is known that can facilitate the test by reading out the operation result of (1) through this scan path (see, for example, Patent Document 1 and Patent Document 2).
[0003]
FIG. 15 shows a circuit configuration of the semiconductor integrated circuit 20 when the scan chain is not configured. The semiconductor integrated circuit 20 includes flip-flops FF1-1 to FF1-n (n is a natural number), logic circuits 10-1 to 10- (n-1), and a buffer BUF12.
[0004]
A clock signal having a predetermined frequency is input from the buffer BUF12 to the clock terminals CK of the flip-flops FF1-1 to FF1-n. Data is input to the D terminal of the flip-flop FF1-1, and the Q terminal of the flip-flop FF1-1 is connected to the data input terminal D of the subsequent flip-flop FF1-2 via the logic circuit 10-1. Similarly, the data output terminal Q of the flip-flop FF1-2 is connected to the data input terminal D of the subsequent flip-flop FF1-3 via the logic circuit 10-2. The flip-flop FF1-1 outputs the data input to the data input terminal D to the data output terminal Q in synchronization with the rising edge of the clock signal input to the clock terminal CK. The same applies to flip-flops after the flip-flop FF1-2.
[0005]
At the time of manufacturing test of a semiconductor integrated circuit such as an LSI, it is necessary to inspect all elements constituting the semiconductor integrated circuit. However, in the configuration shown in FIG. 15, arbitrary data is set in an arbitrary flip-flop. Have difficulty.
[0006]
Therefore, the flip-flops FF1-1 to FF1-n are replaced with flip-flops FF3-1 to FF3-n as shown in FIG. 16 to form a scan chain, that is, a shift register, and arbitrary data is set in any flip-flop. It is common to test by taking out or taking outside.
[0007]
The flip-flops FF3-1 to FF3-n are provided with a scan input terminal SI and a scan enable terminal SE in addition to the data input terminal D, the data output terminal Q, and the clock terminal CK. Arbitrary scan data is input to the scan input terminal SI. A scan enable signal for selecting data to be output to the data output terminal Q is input to the scan enable terminal SE. For example, when the scan enable signal is enabled (for example, high level), as shown in FIG. 17, the scan data input to the scan input terminal SI is synchronized with the rising edge of the clock signal input to the clock terminal CK. Output to data output terminal Q. Thus, the data output terminal Q of each flip-flop is connected to the scan input terminal SI of the subsequent flip-flop, and arbitrary data can be set.
[0008]
On the other hand, when the scan enable signal is not enabled, as shown in FIG. 17, the data input to the data input terminal D is applied to the data output terminal Q in synchronization with the rising edge of the clock signal input to the clock terminal CK. Output. The scan enable signal is at a low level or a high level as necessary during a scan test, and is fixed at a low level during normal operation.
[0009]
However, in the configuration shown in FIG. 16, a malfunction may occur if a skew, that is, a delay due to a time difference occurs in the clock signal supplied from the buffer BUF 12 to each flip-flop. That is, as shown in FIG. 18, for example, when there is a skew between the clock signal input to the flip-flop FF3-2 and the clock signal input to the flip-flop FF3-3, the flip-flop FF3-2 Since the clock signal input to the flip-flop FF3-3 rises after the data is output from the data output terminal Q, the data is not shifted, and the data is output from the flip-flop FF3-3 in the same cycle as the flip-flop FF3-2. It will cause an abnormal operation.
[0010]
Therefore, as shown in FIG. 19, a delay circuit DLY4 having a delay value longer than the delay time due to skew between the data output terminal Q of the flip-flop FF3-2 and the scan input terminal SI of the flip-flop FF3-3. The timing was improved by inserting. As a result, as shown in FIG. 20, the data output from the data output terminal Q of the flip-flop FF3-2 is delayed by a delay circuit DLY4 for a time longer than the delay time due to the skew, and the scan input terminal of the flip-flop FF3-3. Since it is input to SI, it is possible to prevent data from being output from the flip-flop FF3-3 in the same cycle as the flip-flop FF3-2.
[0011]
FIG. 21 shows a semiconductor integrated circuit 30 that can form a scan chain and includes a plurality of clock circuits. The semiconductor integrated circuit 30 shown in FIG. 21 includes buffers BUF12 and BUF14 that output clock signals having different frequencies, and a clock selection circuit MUX16. Here, it is assumed that the frequency of the clock signal output from the buffer BUF14 is higher than the frequency of the clock signal output from the buffer BUF12.
[0012]
The clock selection circuit MUX16 has a B terminal, an A terminal, and an S terminal. The B terminal has a clock signal from the buffer BUF12, the A terminal has a clock signal from the buffer BUF14, and the S terminal has a clock signal. Each selection signal is input. For example, a low level is input to the S terminal during a normal operation, and a high level is input during a scan test.
[0013]
The clock selection circuit MUX16 selects the clock signal from the buffer BUF14 input to the A terminal and selects the flip-flops FF3-3 to FF3-when the clock selection signal input to the S terminal is at a low level, that is, during normal operation. output to n. On the other hand, when the clock selection signal input to the S terminal is at a high level, that is, during a scan test, the clock signal from the buffer BUF12 input to the B terminal is selected and output to the flip-flops FF3-3 to FF3-n. .
[0014]
That is, during normal operation, as shown in FIG. 22, for example, the flip-flop FF3-2 operates with a clock having a frequency different from that of the flip-flop FF3-3. On the other hand, at the time of a scan test, each operates with a clock having the same frequency.
[0015]
For this reason, as shown in FIG. 22, for example, the data output from the flip-flop FF3-2 operated by the clock signal from the buffer BUF12 is held in the next-stage flip-flop FF3-3 for a plurality of cycles. Therefore, the problem caused by the skew in the buffers BUF12 and BUF19 does not occur, and the data output from the flip-flop FF3-2 is transferred to the flip-flop FF3-3 regardless of the presence or absence of skew. Such a relationship is called a multi-cycle path.
[0016]
However, at the time of the scan test, as shown in FIG. 23, since any flip-flop operates with the clock from the buffer BUF12, as described above, the data taken in by the flip-flop FF3-2 due to the clock skew occurs. In the same cycle, the next stage flip-flop FF3-3 takes in an abnormal operation.
[0017]
For this reason, in order to correct a skew that does not cause a problem during normal operation, a design for improving timing is required.
[0018]
Therefore, when performing a scan test design, as shown in FIG. 24, first, a circuit design for a normal LSI function is performed (step 200), and then a scan design such as insertion of a scan flip-flop is performed ( In step 202), the final circuit is determined by performing a design for improving the timing such as inserting a delay circuit in order to prevent the abnormal operation due to the skew as described above (step 204).
[0019]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-177060.
[Patent Document 2]
JP-A-11-125662.
[0020]
[Problems to be solved by the invention]
However, since the design for improving the timing is not necessary for the normal operation of the LSI, the design man-hour for improving the timing is actually an extra man-hour.
[0021]
The present invention has been made in view of the above-described facts, and an object of the present invention is to provide a scan flip-flop capable of reducing the design man-hour for LSI development.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is mounted on a semiconductor integrated circuit including at least a clock generation circuit and a logic circuit, and is a path for performing a normal operation connected in series with the logic circuit interposed therebetween. A scan flip-flop that enables a scan test by forming a scan chain by connecting directly without going through the logic circuit separately, and includes a data input terminal, a scan data input terminal, a scan enable terminal, and a clock terminal And a data output terminal, and in synchronization with a clock signal from the clock generation circuit input to the clock terminal, the data input terminal according to a scan enable signal input to the scan enable terminal Input data or scan input to the scan data input terminal Flip-flops that selectively output data to the data output terminal, and at least the scan data input to the scan data input terminal, when the plurality of flip-flops are connected in series to form a scan chain, Delay means for delaying a predetermined time longer than the delay time of the clock signal so as to be transferred to the flip-flop, The semiconductor integrated circuit includes a plurality of clock generation circuits that generate clocks having different frequencies, and the flip-flop is operated by a clock signal output from any one of the plurality of clock generation circuits during the scan test. And the delay means is provided on the data output terminal side. It is characterized by that.
[0023]
A plurality of scan flip-flops are mounted on a semiconductor integrated circuit including a clock generation circuit and a logic circuit, and are connected in series without using a logic circuit to constitute a scan chain and enable a scan test. Here, the serial connection without using the logic circuit means that the data output terminal of the scan flip-flop is connected so as to be connected to the scan data input terminal of the subsequent scan flip-flop without using the logic circuit.
[0024]
The scan flip-flop includes a flip-flop and a delay unit.
[0025]
The flip-flop includes at least a data input terminal, a scan data input terminal, a scan enable terminal, a clock terminal, and a data output terminal. For example, a flip-flop receives a clock signal from a clock generation circuit input to the clock terminal. In synchronization with the rising edge, data input to the data input terminal or scan data input to the scan data input terminal is selectively output to the data output terminal in accordance with the scan enable signal input to the scan enable terminal.
[0026]
The delay means is configured so that at least scan data input to the scan data input terminal is sequentially transferred to a subsequent flip-flop when a plurality of flip-flops are connected in series to form a scan chain. The delay is delayed for a predetermined time longer than the delay time of the clock signal so that the clock does not capture the same data in the same cycle.
[0027]
Since such a delay means is built in, it is not necessary to design for timing improvement after the scan design. Thereby, the design man-hour of the semiconductor integrated circuit can be reduced.
[0030]
By the way, a semiconductor integrated circuit may include a plurality of clock generation circuits that generate clocks having different frequencies. For example, when data is transferred from a flip-flop that operates with a low-frequency clock to a flip-flop with a high frequency, the data is held for multiple cycles, so there is no problem due to clock delay. This is a problem because it needs to be tested.
[0031]
Therefore, in front The semiconductor integrated circuit includes a plurality of clock generation circuits that generate clocks having different frequencies, and the flip-flop is operated by a clock signal output from any one of the plurality of clock generation circuits during the scan test. The delay means may be provided on the data output terminal side.
[0032]
Thus, by providing the delay means on the data output terminal side, the data output from the data output terminal is delayed by the delay means and output to the subsequent flip-flop. Therefore, it is possible to prevent a plurality of flip-flops from capturing the same data in the same cycle.
[0033]
Claims 2 As described above, the semiconductor integrated circuit includes a plurality of clock generation circuits that generate clocks having different frequencies, and is output from any one of the plurality of clock generation circuits during the scan test. The flip-flop operates in response to a clock signal, the delay means is provided on the data output terminal side, and delay data from the delay means or output data from the data output terminal is selectively output according to a selection signal It is good also as a structure further provided with the selection means to select and the selection signal input means for inputting the said selection signal.
[0034]
In this case, for example, the selection means can select and output the delay data during the scan test, and can select and output the data from the data output terminal as it is during the normal operation. This prevents the data output from the data output terminal from being delayed by the delay means and output to the subsequent flip-flop during the scan test, thereby preventing multiple flip-flops from capturing the same data in the same cycle. In normal operation, the data from the data output terminal is output as it is without being delayed, so that it is possible to prevent the data from being delayed unnecessarily.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. Note that the same reference numerals are given to the same parts as those described in the prior art, and detailed description thereof is omitted.
[0036]
FIG. 1 shows a semiconductor integrated circuit 40 according to this embodiment. As shown in FIG. 1, the semiconductor integrated circuit 40 includes flip-flops FF5-1 to FF5-n (n is a natural number), logic circuits 10-1 to 10- (n-1), and a buffer BUF12.
[0037]
The flip-flops FF5-1 to FF5-n are provided with a data input terminal D, a data output terminal Q, a clock terminal CK, a scan input terminal SI, a scan enable terminal SE, and a scan output terminal SO.
[0038]
Data used for normal operation of the semiconductor integrated circuit 40 is input to the data input terminal D. The data input terminal D of the flip-flop FF5-1 is connected to, for example, an external input terminal, and the data input terminals D of the flip-flops FF5-2 to FF5-n are respectively connected to the preceding logic circuits 10-1 to 10- (n− Connected to the output terminal of 1).
[0039]
From the data output terminal Q, data input to the data input terminal D or the scan input terminal SI is selectively output. The data output terminals Q of the flip-flops FF5-1 to FF5- (n-1) are respectively connected to the input terminals of the logic circuits 10-1 to 10-n in the subsequent stage, and the data output terminals Q of the flip-flops FF5-n are For example, it is connected to an external output terminal.
[0040]
A clock signal having a predetermined frequency is input from the buffer BUF12 to the clock terminal CK.
Arbitrary scan test scan data is input to the scan input terminal SI. The scan input terminal SI of the flip-flop FF5-1 is connected to, for example, an external input terminal for inputting scan data, and the scan input terminals SI of the flip-flops FF5-2 to FF5-n are respectively connected to the preceding flip-flops FF5-1 to FF5-1. It is connected to the scan output terminal SO of FF5- (n-1).
[0041]
A scan enable signal for selecting data to be output to the data output terminal Q is input to the scan enable terminal SE. For example, when the scan enable signal is enabled (for example, high level), the scan data input to the scan input terminal SI is output from the data output terminal Q in synchronization with the rising edge of the clock signal input to the clock terminal CK. The Although details will be described later, data obtained by delaying data output from the data output terminal Q by a predetermined time is output from the scan output terminal SO.
[0042]
On the other hand, when the scan enable signal is not enabled (when the level is low), the data input to the data input terminal D is output to the data output terminal Q in synchronization with the rising edge of the clock signal input to the clock terminal CK. Is done. Further, data obtained by delaying data output from the data output terminal Q by a predetermined time is output from the scan output terminal SO.
[0043]
The scan enable signal is at a low level or a high level as necessary during a scan test, and is fixed at a low level during normal operation.
[0044]
Thus, the data output terminal Q of the preceding flip-flop is connected to the data input terminal D of the succeeding flip-flop across the logic circuit, and the preceding scan output terminal SO is connected to the succeeding scan input terminal SI. Since the data input to the data input terminal D or the scan input terminal SI is selectively output from the data output terminal Q and the scan output terminal SO to the subsequent flip-flop, arbitrary data is set in the logic circuit. And a scan test can be performed.
[0045]
FIG. 2 shows the internal configuration of the flip-flop FF5-2. The flip-flops FF5-1 and FF5-3 to FF5-n have the same configuration.
[0046]
As shown in FIG. 2, the flip-flop FF5-2 includes a flip-flop FF42 and a delay circuit DLY8.
[0047]
The flip-flops FF5-1 to FF5-n correspond to the scan flip-flop of the present invention, the flip-flop FF42 corresponds to the flip-flop of the present invention, the delay circuit DLY8 corresponds to the delay means of the present invention, and the buffer BUF12. Corresponds to the clock generation circuit of the present invention, the data input terminal D corresponds to the data input terminal of the present invention, the data output terminal Q corresponds to the data output terminal of the present invention, and the scan enable terminal SE corresponds to the scan input terminal of the present invention. The clock terminal CK corresponds to the clock terminal of the present invention, the scan input terminal SI corresponds to the scan data input terminal of the present invention, and the scan output terminal SO corresponds to the delayed data output terminal of the present invention. To do.
[0048]
The flip-flop FF42 has the same configuration as the above-described FF3-1 in FIG. That is, in addition to the data input terminal D, the data output terminal Q, and the clock terminal CK, a scan input terminal SI and a scan enable terminal SE are provided, and a scan is performed according to a scan enable signal input to the scan enable terminal SE. The scan data input to the input terminal SI or the data input to the data input terminal D is selectively output to the data output terminal Q.
[0049]
The data output terminal Q of the flip-flop FF42 branches in two directions, one is connected to the data output terminal Q of the flip-flop FF5-1 and the other is connected to the input side of the delay circuit DLY8. The output side of the delay circuit DLY8 is connected to the scan output terminal SO of the flip-flop FF5-1.
[0050]
The delay circuit DLY8 delays the data output from the data output terminal Q of the flip-flop FF42 for a predetermined time and outputs the delayed data to the scan output terminal SO.
[0051]
This predetermined time is set to a time longer than the skew of the clock signal, that is, the delay time of the clock signal generated between the flip-flops.
[0052]
Next, operations of the flip-flops FF5-2 and FF5-3 will be described with reference to a timing chart shown in FIG.
[0053]
When a high level is input to the scan enable terminal SE of the flip-flop FF5-2 at the time of the scan test, as shown in FIG. 3, the scan is performed in synchronization with the rising edge of the clock signal input to the clock terminal CK. The data input to the input terminal SI is delayed by a predetermined time longer than the delay time of the clock signal by the delay circuit DLY8 and output from the scan output terminal SO.
[0054]
As a result, as shown in FIG. 3, there is a skew between the clock signal input to the clock terminal CK of the flip-flop FF5-2 and the clock signal input to the clock terminal CK of the flip-flop FF5-3. Even in this case, since the data input to the scan input terminal SI of the flip-flop FF5-3 is input with a delay longer than the delay time of the clock signal, the flip-flop FF5-2 and the flip-flop FF5-3 are in the same cycle. Can prevent data from being imported.
[0055]
As described above, the flip-flops FF5-1 to FF5-n incorporate the delay circuit DLY8 for delaying the output data. For this reason, when designing the semiconductor integrated circuit 40, as shown in FIG. 4, it is only necessary to first design a circuit (step 100) and then perform a scan design (step 102). Therefore, it is not necessary to design for timing improvement after scan design as in the prior art, and the number of man-hours for designing a semiconductor integrated circuit can be reduced.
[0056]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment, and detailed description is abbreviate | omitted.
[0057]
FIG. 5 shows a semiconductor integrated circuit 50 according to this embodiment. The semiconductor integrated circuit 50 is different from the semiconductor integrated circuit 40 shown in FIG. 1 in that the flip-flops FF7-1 to FF7-n are not provided with the scan output terminal SO, and the data output terminal Q is the logic circuit of the subsequent stage. In addition to being connected to the input side, it is also connected to the scan input terminal SI of the subsequent flip-flop. Other configurations are the same as those of the semiconductor integrated circuit 40 shown in FIG.
[0058]
FIG. 6 shows the internal configuration of the flip-flop FF7-3. The flip-flops FF7-1, FF7-2, and FF7-4 to FF7-n have the same configuration.
[0059]
The flip-flop FF7-3 includes a flip-flop FF42 and a delay circuit DLY8. The output side of the delay circuit DLY8 is connected to the scan input terminal SI of the flip-flop FF42.
[0060]
Therefore, as shown in FIG. 7, the data input to the scan input terminal SI of the flip-flop FF7-3 is delayed by a predetermined time longer than the delay time of the clock signal by the delay circuit DLY8, and the scan input terminal of the flip-flop FF42. Input to SI. The flip-flop FF42 outputs the data input to the scan input terminal SI to the data output terminal Q in synchronization with the rising edge of the clock signal CK.
[0061]
Thereby, it is possible to prevent the flip-flop FF7-2 and the flip-flop FF7-3 from capturing data in the same cycle.
[0062]
As described above, since the flip-flops FF7-1 to FF7-n incorporate the delay circuit DLY8 for delaying output data, when designing the semiconductor integrated circuit 50, design for improving timing is required. There is no need to perform this, and the number of design steps for the semiconductor integrated circuit can be reduced.
[0063]
(Third embodiment)
Next, a third embodiment of the present invention will be described. The same parts as those of the circuit described in the prior art are denoted by the same reference numerals, and detailed description thereof is omitted.
[0064]
FIG. 8 shows a semiconductor integrated circuit 60 according to this embodiment. Since the semiconductor integrated circuit 60 is different from the semiconductor integrated circuit 30 shown in FIG. 21 only in the configuration of the flip-flops FF11-1 to FF11-n, description of other configurations is omitted.
[0065]
FIG. 9 shows the internal configuration of the flip-flop FF11-2. The flip-flops FF11-1 and FF11-3 to FF11-n have the same configuration.
[0066]
As shown in FIG. 9, the flip-flop FF11-2 includes a flip-flop FF42 and a delay circuit DLY8. The input side of the delay circuit DLY8 is connected to the data output terminal Q of the flip-flop FF42, and the delay circuit DLY8 The output side is connected to the data output terminal Q of the flip-flop FF11-2. As a result, the data output from the data output terminal Q of the flip-flop FF42 is delayed for a time longer than the delay time of the clock signal, and the input side of the subsequent logic circuit and the scan input terminal SI of the subsequent flip-flop FF3-3. Is output.
[0067]
Next, operations of the flip-flops FF11-2 and FF11-3 will be described with reference to a timing chart shown in FIG.
[0068]
At the time of the scan test, a high level is input as a clock selection signal to the S terminal of the clock selection circuit MUX16. Thus, the clock selection circuit MUX16 selects the clock signal from the buffer BUF12 input to the B terminal and flip-flop Output to FF11-3 to FF3-n.
[0069]
Therefore, as shown in FIG. 10, both the flip-flop FF11-2 and the flip-flop FF11-3 are operated by the clock signal from the buffer BUF12.
[0070]
In the scan test, when a low level is input to the scan enable terminal SE of the flip-flop FF11-2, as shown in FIG. 10, in synchronization with the rising edge of the clock signal input to the clock terminal CK. The data input to the data input terminal D is delayed by a predetermined time longer than the delay time of the clock signal by the delay circuit DLY8 and output from the data output terminal Q.
[0071]
As a result, as shown in FIG. 10, there is a skew between the clock signal input to the clock terminal CK of the flip-flop FF11-2 and the clock signal input to the clock terminal CK of the flip-flop FF11-3. Even in this case, the flip-flop FF11-2 and the flip-flop FF11-3 can be prevented from capturing data in the same cycle.
[0072]
As described above, the flip-flops FF11-1 to FF11-n incorporate the delay circuit DLY8 for delaying the output data. Therefore, when designing the semiconductor integrated circuit 60, it is not necessary to design for timing improvement after the scan design, and the design man-hour for the semiconductor integrated circuit can be reduced.
[0073]
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same part as 3rd Embodiment, and detailed description is abbreviate | omitted.
[0074]
FIG. 11 shows a semiconductor integrated circuit 70 according to this embodiment. Since the semiconductor integrated circuit 70 is different from the semiconductor integrated circuit 60 shown in FIG. 8 only in the configuration of the flip-flops FF12-1 to FF12-n, the description of the other configuration is omitted.
[0075]
FIG. 12 shows the internal configuration of the flip-flop FF12-2. The flip-flops FF12-1 and FF12-3 to FF12-n have the same configuration.
[0076]
As shown in FIG. 12, the flip-flop FF12-2 includes a flip-flop FF42, a delay circuit DLY8, and an output selection circuit MUX44. In addition to the data input terminal D, the scan input terminal SI, the scan enable terminal SE, the clock terminal CK, and the data output terminal Q, the flip-flop FF12-2 includes an output selection signal input terminal SH for inputting the output selection signal SH. ing.
[0077]
The output selection circuit MUX44 corresponds to the selection means of the present invention, and the output selection signal input terminal SH corresponds to the selection signal input means of the present invention.
[0078]
The output selection circuit MUX44 has a B terminal, an A terminal, and an S terminal, the B terminal is connected to the data output terminal Q of the flip-flop FF42, and the A terminal is connected to the output side of the delay circuit DLY8. ing. The input side of the delay circuit DLY8 is connected to the data output terminal Q of the flip-flop FF42.
[0079]
The output selection circuit MUX 44 selectively outputs the data input to the B terminal or the A terminal to the data output terminal Q of the flip-flop FF12-2 according to the output selection signal SH input to the S terminal. For example, the output selection signal SH is a signal that is at a low level during normal operation and at a high level during a scan test. The output selection circuit MUX 44 selects the data input to the B terminal and outputs it to the data output terminal Q of the flip-flop FF12-2 for output selection when the output selection signal SH is at a low level, that is, during normal operation. When the signal SH is at a high level, that is, during a scan test, the data input to the A terminal is selected and output to the data output terminal Q of the flip-flop FF12-2.
[0080]
Accordingly, during normal operation, the data output from the data output terminal Q of the flip-flop FF42 is output as it is to the data output terminal Q of the flip-flop FF12-2, and during the scan test, it is output from the data output terminal Q of the flip-flop FF42. The delayed data is delayed by the delay circuit DLY8 for a time longer than the delay time of the clock signal and output to the data output terminal Q of the flip-flop FF12-2.
[0081]
Next, the operation during the scan test of the flip-flops FF12-2 and FF12-3 will be described with reference to the timing chart shown in FIG.
[0082]
During the scan test, a high level is input as a clock selection signal to the S terminal of the clock selection circuit MUX16. Thereby, the clock selection circuit MUX16 selects the clock signal from the buffer BUF12 input to the B terminal and outputs it to the flip-flops FF12-3 to FF12-n.
[0083]
For this reason, as shown in FIG. 13, both the flip-flop FF12-2 and the flip-flop FF12-3 are operated by the clock signal from the buffer BUF12.
[0084]
In the scan test, when a low level is input to the scan enable terminal SE of the flip-flop FF12-2 and a high level is input to the output selection signal input terminal SH, as shown in FIG. In synchronization with the rising edge of the clock signal input to CK, the data input to the data input terminal D is delayed by a predetermined time longer than the delay time of the clock signal by the delay circuit DLY8 and output from the data output terminal Q. .
[0085]
As a result, as shown in FIG. 13, a skew is generated between the clock signal input to the clock terminal CK of the flip-flop FF12-2 and the clock signal input to the clock terminal CK of the flip-flop FF12-3. Even in this case, the flip-flop FF12-2 and the flip-flop FF12-3 can be prevented from taking in data in the same cycle.
[0086]
Next, operations during normal operation of the flip-flops FF12-2 and FF12-3 will be described with reference to a timing chart shown in FIG.
[0087]
During normal operation, a low level is input as a clock selection signal to the S terminal of the clock selection circuit MUX16. Thereby, the clock selection circuit MUX16 selects the clock signal from the buffer BUF14 input to the A terminal and outputs it to the flip-flops FF12-3 to FF12-n.
[0088]
Therefore, as shown in FIG. 14, the flip-flop FF12-2 and the flip-flop FF12-3 operate with clock signals having different frequencies.
[0089]
In a normal operation, when a low level is input to the scan enable terminal SE of the flip-flop FF12-2 and a low level is input to the output selection signal input terminal SH, the output selection circuit MUX44 is connected to the B terminal. The input data, that is, the data output from the data output terminal Q of the flip-flop FF42 is selected and output to the data output terminal Q of the flip-flop FF12-2. As a result, the data can be output without delay as shown in FIG.
[0090]
As described above, the flip-flops FF12-1 to FF12-n incorporate the delay circuit DLY8 and the output selection circuit MUX44 for delaying the output data. Therefore, when designing the semiconductor integrated circuit 70, it is not necessary to design for timing improvement after the scan design, and the design man-hour for the semiconductor integrated circuit can be reduced.
[0091]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the design man-hours for LSI development.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment.
FIG. 2 is a circuit diagram of a flip-flop according to the first embodiment.
FIG. 3 is a timing chart showing operation timings of the semiconductor integrated circuit according to the first embodiment.
FIG. 4 is a flowchart showing a design flow of the semiconductor integrated circuit according to the first embodiment.
FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment.
FIG. 6 is a circuit diagram of a flip-flop according to a second embodiment.
FIG. 7 is a timing chart showing operation timings of the semiconductor integrated circuit according to the second embodiment.
FIG. 8 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment.
FIG. 9 is a circuit diagram of a flip-flop according to a third embodiment.
FIG. 10 is a timing chart showing operation timings of the semiconductor integrated circuit according to the third embodiment.
FIG. 11 is a circuit diagram of a semiconductor integrated circuit according to a fourth embodiment.
FIG. 12 is a circuit diagram of a flip-flop according to a fourth embodiment.
FIG. 13 is a timing chart showing operation timings during a scan test of the semiconductor integrated circuit according to the fourth embodiment.
FIG. 14 is a timing chart showing operation timings during normal operation of the semiconductor integrated circuit according to the fourth embodiment.
FIG. 15 is a circuit diagram of a semiconductor integrated circuit according to a conventional example.
FIG. 16 is a circuit diagram of a semiconductor integrated circuit according to a conventional example.
FIG. 17 is a timing chart showing operation timings of a semiconductor integrated circuit according to a conventional example.
FIG. 18 is a timing chart showing operation timing of a semiconductor integrated circuit according to a conventional example.
FIG. 19 is a circuit diagram of a semiconductor integrated circuit according to a conventional example.
FIG. 20 is a timing chart showing the operation timing of a semiconductor integrated circuit according to a conventional example.
FIG. 21 is a circuit diagram of a semiconductor integrated circuit according to a conventional example.
FIG. 22 is a timing chart showing operation timings in a normal operation of a semiconductor integrated circuit according to a conventional example.
FIG. 23 is a timing chart showing operation timings during a scan test of a semiconductor integrated circuit according to a conventional example.
FIG. 24 is a flowchart showing a design flow of a semiconductor integrated circuit according to a conventional example.
[Explanation of symbols]
10 logic circuits
20, 30, 40, 50, 60, 70 Semiconductor integrated circuit
BUF12, BUF14 buffer
DLY4, DLY8 delay circuit
FF1, FF3, FF5, FF7, FF11, FF12 flip-flop
FF42 flip-flop
MUX16 clock selection circuit
MUX44 output selection circuit
D Data input terminal
Q Data output terminal
CK clock pin
SE scan enable pin
SH Output selection signal input terminal
SI scan input terminal
SO Scan output terminal

Claims (2)

A plurality of semiconductor integrated circuits including at least a clock generation circuit and a logic circuit are mounted, and a scan chain can be formed by directly connecting without passing through the logic circuit separately from a path for performing a normal operation with the logic circuit sandwiched in series. A scan flip-flop that is configured to enable scan testing,
A data input terminal, a scan data input terminal, a scan enable terminal, a clock terminal, and a data output terminal are provided at least, and in synchronization with a clock signal from the clock generation circuit input to the clock terminal, A flip-flop that selectively outputs data input to the data input terminal or scan data input to the scan data input terminal to the data output terminal in response to a scan enable signal input to the scan enable terminal;
From the delay time of the clock signal, at least the scan data input to the scan data input terminal is sequentially transferred to the subsequent flip-flop when a plurality of flip-flops are connected in series to form a scan chain. A delay means for delaying a predetermined time that is too long,
Built-in,
The semiconductor integrated circuit includes a plurality of clock generation circuits that generate clocks having different frequencies, and the flip-flop is operated by a clock signal output from any one of the plurality of clock generation circuits during the scan test. Works and
A scan flip-flop , wherein the delay means is provided on the data output terminal side . A plurality of semiconductor integrated circuits including at least a clock generation circuit and a logic circuit are mounted, and a scan chain can be formed by directly connecting without passing through the logic circuit separately from a path for performing a normal operation with the logic circuit sandwiched in series. A scan flip-flop that is configured to enable scan testing,
A data input terminal, a scan data input terminal, a scan enable terminal, a clock terminal, and a data output terminal are provided at least, and in synchronization with a clock signal from the clock generation circuit input to the clock terminal, A flip-flop that selectively outputs data input to the data input terminal or scan data input to the scan data input terminal to the data output terminal in response to a scan enable signal input to the scan enable terminal;
From the delay time of the clock signal, at least the scan data input to the scan data input terminal is sequentially transferred to the subsequent flip-flop when a plurality of flip-flops are connected in series to form a scan chain. A delay means for delaying a predetermined time that is too long,
Built-in,
The semiconductor integrated circuit includes a plurality of clock generation circuits that generate clocks having different frequencies, and the flip-flop is operated by a clock signal output from any one of the plurality of clock generation circuits during the scan test. Works and
The delay means is provided on the data output terminal side, and selectively outputs delay data from the delay means or output data from the data output terminal according to a selection signal; and inputs the selection signal And a selection signal input means for performing the scan flip-flop.

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