JP2000266818A - Scan test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a clock skew in a scan test without giving an influence on the performance of a clock in an ordinary operation by a method wherein a delay element is inserted into a test clock before the selector of the clock. SOLUTION: A signal test clock which is distributed so as to be used in a scan test is delayed in every clock buffer tree. A selector 10 which selects a clock used in an ordinary operation and a clock for the scan test is installed. The selector is installed in every clock buffer tree. Before the selector of every clock buffer tree, the test clock is delayed by every delay element. Every delay amount of every delay element is calculated by calculating every delay amount by the test clock of every clock buffer tree. As a result, a clock skew in a scan path can be seduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan test clock circuit for reducing clock skew in a scan test using an LSI or ASIC.

[0002]

2. Description of the Related Art A scan circuit is one of methods for facilitating test of LSIs, ASICs and the like. The scan circuit is a circuit used for testing a sequential circuit and a combinational circuit between the sequential circuits. In a scan-designed sequential circuit, flip-flops are connected in a chain and operated as a shift register. Thus, the circuit can read out the data set in each flip-flop in series, and can inspect the elements and wiring for defects.

By the way, LSIs and ASICs usually have a plurality of clocks having different frequencies in a circuit. Among these, there are LSIs and ASICs that do not have a clock terminal dedicated to scan test. These LSIs and ASICs select one of a plurality of clocks and use it as a scan test clock. In this case, this clock or terminal is used in combination with the function of the original clock and the scan test clock. In this case, the frequency can be changed.

With respect to clock systems other than the selected clock, scan test clocks are distributed for scan test. Then, the selector provided at the root of the clock buffer tree selects which of the normal clock and the scan test clock is used.

FIG. 2 shows an example of a prior art circuit having two clocks having different frequencies. FF21, FF22, FF2
Reference numeral 3 denotes a flip-flop with a scan function, which has a data input, a data output, a scan input, and a clock terminal. FF21, FF22, FF23, and FF24 form a shift register, and form a scan path. SEL1
Reference numeral 0 denotes a selector for selecting a clock between a normal time and a test time. Delay 40 is a delay element having a delay large enough to eliminate a hold time violation occurring in the scan path from FF23 to FF22.

The delay element Delay 40 delays the data line of the shift register. The arrows in the figure indicate data lines constituting the scan path. Although not shown, between FF21 and FF22 and between FF23 and FF
Data lines constituting a scan path also exist between the lines 24.

At the time of normal operation, TMO is applied to the selector SEL10.
By setting DE = 0, FF21 / FF22 becomes CLK1, FF23 /
The FF 24 operates with CLK2. FIG. 3 shows the state of CLK. CLK1 and CLK2 have different frequencies and phases. Each operates at its own frequency.

During the scan test, the selector SEL10
Is set to TMODE = 1. As a result, the clock is switched to the selector SEL1
CLK1 is selected by 0. Therefore, all the flip-flops basically perform the scan operation in synchronization with CLK1, that is, with CLK1 except for the delay. At this time, the frequency of the test clock input to FF21, FF22, FF23, and FF24 is naturally the same as the frequency of CLK1.

However, during normal operation, the clock CLK1
The specifications such as the number of flip-flops at the last stage connected to CLK2, the required skew value, and AC specifications are different.
Therefore, the number of stages of the clock buffer differs between the clock buffer tree of CLK1 and the clock buffer tree of CLK2. For this reason, the delay of the clock buffer tree of CLK1 at the time of the test and the delay of the clock buffer tree when CLK1 is input to the place where it operates with CLK2 during normal operation are naturally different. FIG. 4 shows an example of the clock in this state.

In FIG. 4, a delay is caused by each buffer from the input of CLK1, and the CLK1 system, C
The LK1-2 system is shown. CL of the time chart of FIG.
The K1 system is FF21, FF2 for scan test shown in FIG.
2 is a clock for operating the second clock. The CLK1-2 system is a CLK for operating the scan test FFs 23 and 24. The CLK1-2 system means that CLK1 is input to a circuit that operates with CLK2 during normal times. Here, it is assumed to be a CLK1-2 system portion shown in FIG.

At the time of such a test, the scan path is
It crosses over different clock systems like between FF23 and FF22. In such a scan path, a shortage of data hold time may occur. That is, because the clock system changes from the CLK1-2 system to the CLK1 system, the FF 22 latches with clocks that are not at the same timing due to a difference in delay.

FIG. 5 shows a time chart in this state.
The CLK1 system is a circuit that operates with the clock CLK1 in a normal state, and is a delayed version of the clock CLK1, and is a clock of the FF21 and the FF22.
The data determination time of the ScanData FF2 input after the rise of the CLK1 system is short, and the hold time cannot be secured. In the CLK1-2 system, CLK1 is selected by SEL10 and normally passes through a buffer through which CLK2 passes.
Are the clocks of FF23 and FF24.

At present, when a shortage of the hold time occurs in a scan path spanning clocks of different frequencies, a countermeasure is taken by inserting a delay element into a data line. FIG. 6 shows a time chart in this state. The data determination time of ScanData FF2 input is delayed because it passes through a delay element. Therefore, even after the rise of the CLK1 system, the data determination time of ScanData FF2 is sufficient. As a result, a hold time can be secured for the timing relationship between the CLK1 system and the ScanData FF2 input.

FIG. 8 shows an example of a circuit configuration when there are four different clocks. FF21, FF22, FF23, FF
24, FF25, FF26, FF27, and FF28 constitute a shift register and constitute a scan path. SEL1
0, SEL11 and SEL12 are clock selection selectors. Buffer 30, 31, 32, 33, 34, 35, 3
6, 37, 38, 39, 60, 61, 62 and 63 are clock buffers.

In this example, delay elements are inserted where the clock system changes between shift registers in the scan path. Delay 41 on the scan path between CLK1 and CLK2, and Dela on the scan path between CLK2 and CLK3.
y42, Delay 43 is inserted in the scan path between CLK3 and CLK4. The principle of operation is the stacking in the case of FIG.

[0016]

At present, a designer inserts a delay element for hold time countermeasures individually into a scan path in question. Therefore, as the number of scan paths having a short hold time increases, the number of delay elements irrelevant to the original logic increases.
This increases power consumption and area. In addition, the path where the hold time is insufficient and the magnitude of the delay required for the countermeasure vary depending on the layout result. For this reason,
At present, elements are manually inserted while viewing the delay simulation results after layout. This is one cause of an increase in the design period.

[0017]

[MEANS FOR SOLVING THE PROBLEMS] Two or more clocks
An electronic circuit having a buffer tree. During a scan test, the clocks of two or more types of clock buffer trees are converted into a single test clock by each selector of two or more types of clock buffer trees. In the scan test circuit, the delay elements for each of two or more types of clock buffer trees are added to the test clock at a stage preceding each selector, and the test clocks are delayed by respective delay amounts to perform the scan.・
A scan test circuit for performing path timing adjustment.

Each delay amount of each delay element is compared with each test clock delay when each of the two or more types of clock buffer trees is operated with a test clock to establish a scan path timing. Test circuit which is each delay amount calculated for each.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described. FIG. 1 shows a circuit configuration of an embodiment of the present invention. FIG. 3 shows a clock buffer tree and a flip-flop for a scan test. FF21, FF22, FF23, and FF24 are flip-flops with a scan function and have a data input, a data output, a scan input, and a clock terminal.

FF21 to FF24 constitute a shift register, and constitute a scan path. Arrows indicate a scan path and a data line. The scan path has a shift register composed of flip-flops that hold scan data acquired during a scan test. The scan path is a data read path at the time of a scan test.

Although not shown, FF21 and FF22, FF23
There is also a data line between the FFs 24, which constitutes a shift register and forms a scan path. In addition, each CLK
A buffer is inserted in the system. The number and configuration of the buffers differ for each CLK system as described in the prior art.

A buffer is provided to drive the clock. Buffers 30, 31, 32, 3
CLK1 passes during normal operation. Buffer 3
CLK2 passes through 5, 36 and 37 during normal operation. As shown in FIG. 1, the input clocks of the FF21 and FF22 are set to the CLK1 system as in the prior art. The input clocks of FF23 and FF24 are CLK1-2.

SEL 10 is a selector, which selects a clock during normal operation and during a scan test. Delay50
Is a delay element having the magnitude of the delay difference between the CLK1 system and the CLK1-2 system. That is, the circuit configuration of the present invention delays the test clock, not the data, by the delay element.
The delay element is selected for the clock. The delay amount of the Delay 50 is obtained by calculating the delay amount in the clock buffer tree of the CLK1 system and the CLK1-2 system and taking the difference.

Next, the operation of the present invention will be described. During normal operation, by setting the selector SEL10 to TMODE = 0, the FF21
The clock buffer tree of / FF22 contains CLK1 and FF22.
CLK2 is supplied to the clock buffer tree of the 23 / FF24. CLK1 and CLK2 have different frequencies. With these clocks, each circuit (not shown) operates normally. At this time, since no scan test is performed,
The shift registers FF21 to FF24 do not operate.

During the scan test, the selector SEL10
By setting TMODE = 1 to CLK as the test clock
1 is selected. Therefore, all flip-flops, FF
21 to FF24 perform a scan operation basically in synchronization with CLK1. At this time, the frequency of the test clock input to FF21 to FF24 is the same.

As shown in FIG. 1, FF21 and FF22 are CLK
1 operates with the CLK1 system delayed. In FF23 and FF24, the selected CLK1 is a delay element Delay50 and a selector SEL1.
0, and operates by the CLK1-2 system delayed by the buffers 35, 36 and the like.

FIG. 7 shows a time chart at the time of the scan test of the present invention. Here, the delay of the clock buffer tree based on CLK1 at the time of the scan test due to the delay element Delay50 inserted before the selector SEL10 is substantially equal between the CLK1 system and the CLK1-2 system. That is, CL
The K1 system and the CLK1-2 system have the same frequency and almost the same phase. This is because the Delay2 of the delay element delays the CLK2 system by the calculated delay amount.

The FF23 and FF24 operate according to the CLK1-2 system and output scan data. As a result, Scan
Since the output of Data FF3 will be delayed, the input of ScanData FF2 will also be delayed. Therefore, when the FF 22 operates in the CLK1 system, the ScanData FF2 after the rise of the CLK1 system
There is sufficient time to determine the input data.

As a result, a sufficient hold time can be secured as a timing relationship. As a result, the scan data from the FF 23 can be reliably latched, so that the scan test can be accurately performed. This allows
Clock skew has been reduced.

A second embodiment will be described below. In the first embodiment, a circuit having two types of clocks has been described. However, a similar circuit configuration for three or more types of clocks can be used to reduce clock skew during a scan test.

Here, the case of four types of clocks will be described as an example. FIG. 9 is a circuit configuration example in the case of four types of clocks. The configuration is such that the delay elements Delay 51 and Delay 5 each having an individual delay amount are added to the test clock CLK 1 for each clock.
2, Delay 53, each selector SEL10, SEL11, SEL12
Put in front of.

Each delay amount of each delay element is based on a calculation based on a delay when a test clock is applied. FF21,
FF22, FF23, FF24, FF25, FF26, FF27, FF
Reference numeral 28 denotes a shift register, which is a scan path.

Normally, the buffers through which CLK2 passes are buffers 35, 36, 37, 68 and 69. Normally CL
Buffers through which K3 passes are buffers 38, 39, 60, and 6
4,65. Buffers through which CLK4 normally passes are buffers 61, 62, 63, 66, and 67.

The operation is that the operation of the first embodiment is repeated between each clock at the time of the scan test. Delay element De
lay53, selector SEL12, buffers 61, 66, 62
Thus, scan data is output from the FF 27 with the delayed test clock.

In the FF 26, the test clock is a delay element De.
lay52, selector SEL11, buffers 38, 64, 39
The scan data from the FF 27 is held by the test clock delayed by the above. This is the same principle as in the first embodiment even if the delay amount is different. This is repeated between FF25 and FF24. The same applies between FF23 and FF22.

[0036]

According to the present invention, a delay element for adjusting a delay difference between clocks during a scan test is provided by a clock buffer.
Insert at the root of the tree. In other words, the test clock is inserted into the delay element before the clock selector. As a result, the clock skew during the scan test can be reduced without affecting the clock performance during the normal operation.

Further, by using such a circuit, the delay element individually inserted into the scan path extending between different clock systems in which the hold time violation has occurred becomes unnecessary. Therefore, simplification of design,
Power consumption and area can be reduced.

[Brief description of the drawings]

FIG. 1 is a scan test clock circuit realized by the present invention.

FIG. 2 is a clock circuit for scan test realized by the prior art.

FIG. 3 is a time chart of a normal clock.

FIG. 4 is a timing chart of a clock during a scan test.
G

FIG. 5 is a time chart when no measures are taken in a scan test.

FIG. 6 is a time chart at the time of countermeasures by a conventional technique in a scan test.

FIG. 7 is a time chart for a countermeasure according to the present invention in a scan test.

FIG. 8 shows a conventional scan test clock circuit having four different clocks.

FIG. 9 shows a scan test clock circuit according to the present invention when four different clocks are provided.

[Explanation of symbols]

10, 11, 12 SEL (selector) 11, 22, 23, 24, 25, 26, 27, 28 F
F (flip-flop) 12, 31, 32, 33, 34, 35, 36, 37, 3
8, 39, 60, 61, 62, 63, 64, 65, 6
6, 67 Buffer, 41, 42, 43, 50, 51, 52, 53 Delay
(Delay element)

Claims (2)

[Claims] An electronic circuit having two or more types of clock buffer trees, wherein at the time of a scan test, each of the two or more types of clock buffer trees is selected by each selector of the two or more types of clock buffer trees. In a scan test circuit for switching a clock of a buffer tree to a single test clock, a delay element for each of the two or more types of clock buffer trees is inserted into the test clock at a stage preceding each of the selectors. A scan test circuit for adjusting the timing of a scan path by delaying the test clock by a delay amount. 2. The delay amount of each of the delay elements is compared with each test clock delay when each of the two or more clock buffer trees operates with the test clock, and the scan is performed. 2. The scan test circuit according to claim 1, wherein each of the delay amounts is calculated to establish a path timing.