CN203117968U - SPI (Serial Peripheral Interface) communication interface - Google Patents
SPI (Serial Peripheral Interface) communication interface Download PDFInfo
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- CN203117968U CN203117968U CN 201220735758 CN201220735758U CN203117968U CN 203117968 U CN203117968 U CN 203117968U CN 201220735758 CN201220735758 CN 201220735758 CN 201220735758 U CN201220735758 U CN 201220735758U CN 203117968 U CN203117968 U CN 203117968U
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Abstract
The utility model belongs to the technical field of distributed control systems and relates to an SPI (Serial Peripheral Interface) communication interface, which aims to solve the technical problems of unreliability, dislocation and the like of data collected by a slave due to the fact that the current data acquisition or the data area assignment can be interrupted when a communication instruction is passively received by the slave. The SPI communication interface comprises an SPI communication host, at least one slave, an MISO (Master Input/Slave Output) line, an MOSI (Master Output/Slave Input) line, an SCK (Serial Clock) line and a CS (Chip Select) line. The SPI communication interface is characterized in that each slave is provided with a Ready line which is connected with the host and used for guaranteeing data integrity of SPI communication. By utilizing the SPI communication interface, two communication methods are provided to guarantee the data integrity of the SPI communication. According to the SPI communication interface, the Ready line is additionally arranged between the SPI communication host and the slave, so that the influence that the current operation is interrupted when the communication instruction is passively received by the slave in the SPI communication is eliminated, and the data integrity of the SPI communication is guaranteed.
Description
Technical field
The utility model belongs to the DCS(scattered control system) technical field, be specifically related to a kind of chip SPI communication interface between fastener inside and the fastener that is applied to.
Background technology
Scattered control system (DCS) is widely used in industry-by-industries such as electric power, metallurgy, petrochemical complex.Along with the development of DCS, the situation of single module double mcu even multiple single chip microcomputer is more and more, or single module has a plurality of programmable chips.The SPI communications protocol is flexible, degree of controllability is high, and a lot of cpu chip SPI communication of tenaculum DMA, makes the SPI communication become more simple and convenient, and the time that takies CPU still less, so the communication mode of SPI agreement is all adopted in the communication of a lot of chip chambers.
The both sides of SPI communication are divided into main frame and one or more from equipment, generally use 4 lines: the effective slave of serial time clock line (SCK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and low level is selected line CS.
During general SPI communication, the status that main frame has the initiative and dominates, slave can only passively be accepted.But the chip as slave generally also needs to carry out other orders and task, and the communication command of accepting main frame passively inevitably will interrupt and influence the task of current execution, if especially both sides' Content of communciation is the data of bringing in constant renewal in, slave is accepted the SPI communication command passively and may be interrupted current data acquisition or interrupt the data field assignment, problems such as the unreliable and data dislocation of the data that cause slave to collect, even might cause very serious fault.
Summary of the invention
The technical problems to be solved in the utility model provides a kind of SPI communication interface, the current task of avoiding being in the SPI communication programmable chip of slave status is interrupted, also avoid the data of communication transmission that problems such as dislocation take place, improved the operation efficiency of transfer efficiency and processor.
For achieving the above object, the technical scheme that adopts is: a kind of SPI communication interface, main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of comprising the SPI communication, it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
Good effect of the present utility model is: by set up a Ready line between the main frame of SPI communication and every slave, make slave have initiative to communication, eliminated the influence that is interrupted current operation when slave is passive in the existing SPI communication accepts communication instruction.Simultaneously because the existence of CS line, the main frame of SPI communication is not lost the control to communication yet, main frame and slave can not interrupt other tasks of oneself because of the passive communication command of accepting, thereby the quality of SPI communication is significantly improved, guarantee the data integrity of SPI communication, also improved the work efficiency of the CPU of the main frame of SPI communication and slave.
Description of drawings
Fig. 1 is the hardware principle block diagram of existing SPI communication;
Fig. 2 is the hardware principle block diagram of SPI communication of the present utility model;
Fig. 3 is the byte sequential chart of the SPI means of communication of the present utility model;
Sequential chart when Fig. 4 is first kind of means of communication multibyte communication of the present utility model;
Sequential chart when Fig. 5 is second kind of means of communication multibyte communication of the present utility model;
The process flow diagram of slave when Fig. 6 is first kind of means of communication multibyte communication of the present utility model;
The process flow diagram of main frame when Fig. 7 is first kind of means of communication multibyte communication of the present utility model;
The process flow diagram of slave when Fig. 8 is second kind of means of communication multibyte communication of the present utility model;
The process flow diagram of main frame when Fig. 9 is second kind of means of communication multibyte communication of the present utility model.
Embodiment
A kind of SPI communication interface comprises main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of SPI communication, and it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
Use above-mentioned SPI communication interface, first kind of means of communication of guaranteeing data integrity is characterized in that, may further comprise the steps:
(1) the slave data acquisition finishes and data is put into SPI transmission buff district, when being ready for the SPI communication, drags down the Ready line;
(2) main frame detects certain slave Ready line when low, drags down the CS line of this slave correspondence;
(3) main frame and this slave carry out the SPI communication;
(4) communication finishes, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
Use above-mentioned SPI communication interface, second kind of means of communication of guaranteeing data integrity is characterized in that, may further comprise the steps:
(1) the slave data acquisition finishes and data is put into SPI transmission buff district, when being ready for the SPI communication, drags down the Ready line;
(2) main frame detects certain slave Ready line when low, drags down the CS line of this slave correspondence;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) whether the judgment data transmission finishes, and end of transmission then goes to step (7), does not finish then to go to step (5);
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
Fig. 1 is the hardware principle block diagram of existing SPI communication, Fig. 2 is the hardware principle block diagram of SPI communication of the present utility model, comparison diagram 1 and Fig. 2 are as seen, SPI communication of the present utility model has been Duoed a Ready line than existing SPI communication at hardware, the signal of this line is exported by slave, be input to main frame, be that slave is to the control line of whole SPI communication, this line makes main frame in whole SPI communication initiative arranged, therefore, the SPI communication command that no longer sent by main frame such as the task of the current execution of slave such as data collection interrupts.
Fig. 3 is the byte sequential chart of the SPI means of communication of the present utility model, by in the sequential chart as can be seen, only the CS line just can drag down after the Ready line drags down, and all be that CLK just can be effective under the low situation at Ready and CS line only, thereby data just can be effective, the existence of Ready line and CS line just, just make main frame and the slave both sides of SPI communication that ownership has been arranged, main frame and slave can not interrupt other tasks of oneself because of the passive communication command of accepting, thereby can guarantee data and other data integrities and the true and accurate of SPI communication.
Sequential chart when the sequential chart that the utility model has two kinds of communication mode: Fig. 4 when being first kind of means of communication multibyte communications of the present utility model, Fig. 5 are second kind of means of communication multibyte communications of the present utility model.The something in common of two kinds of communication modes is that slave has the Ready control line, all communication is had control; Difference is that first kind of pattern Ready line only overturns once, and beginning drags down before the communication, and communication finishes and draws high, and is applicable to the demanding situation of communication speed, and main frame, slave can be with rapid data transmission means such as DMA; And second kind of pattern overturn once at each byte end of transmission Ready line, in this case, main frame needed to judge the level of Ready line before each the byte transmission except first byte, thereby more can guarantee the correctness of communication, but the defective of this pattern is, main frame all needs to judge the state of Ready line at every turn because each slave all will overturn the Ready line, thereby has reduced the communication speed of SPI, and can not use the high speed means of communication such as DMA.So can select to use first kind of pattern according to actual conditions in use still is second kind of pattern.
The process flow diagram of main frame when the process flow diagram of slave when Fig. 6 is first kind of means of communication multibyte communication of the present utility model, Fig. 7 are first kind of means of communication multibyte communications of the present utility model.As shown in the figure, when the slave DSR, drag down the Ready line; Main frame detects certain slave Ready line when low, drags down the CS line of this slave correspondence; Main frame and this slave carry out the SPI communication; Communication finishes, and main frame is drawn high the CS line, and slave is drawn high the Ready line.
The process flow diagram of main frame when the process flow diagram of slave when Fig. 8 is second kind of means of communication multibyte communication of the present utility model, Fig. 9 are second kind of means of communication multibyte communications of the present utility model.As shown in the figure:
(1) the slave data acquisition finishes and data is put into SPI transmission buff district, when being ready for the SPI communication, drags down the Ready line;
(2) main frame detects certain slave Ready line when low, drags down the CS line of this slave correspondence;
(3) this slave and main frame begin the SPI communication, transmit a byte;
(4) whether the judgment data transmission finishes, and end of transmission then goes to step (7), does not finish then to go to step (5);
(5) slave is put into the SPI data register with next byte, and the level of the Ready line that overturns;
(6) main frame judges according to the byte number that transmits whether Ready line level is correct, correctly then goes to step (3), the incorrect step (7) that then goes to;
(7) main frame is drawn high the CS line, and slave is drawn high the Ready line, and communication finishes.
By the process flow diagram of above-mentioned two kinds of communication modes as can be seen, before each communication begins, all to operate the Ready line, this is that slave can select when to begin communication, and main frame is because the existence of CS line, do not lose the control to communication yet, like this slave can data acquisition or other tasks finish control Ready line notice main frame afterwards can communication, finish and control the CS line afterwards and begin communication and main frame also can be chosen in other tasks, the control that all has of main frame and slave makes the communication controllability that becomes very strong like this, other operations of main frame and slave can not interrupted, guaranteed the data integrity that is designed into of other operations.
Experimental verification:
Test for performance of the present utility model, compare with existing SPI communication modes, both hardware circuits are identical, all adopting main frame is that LPC2136, two slaves are STM32F103, main frame carries out multiple communication simultaneously, slave carries out the meter of pulsed quantity simultaneously to be measured frequently, and measurement range is 1-10000Hz.
Experimental results show that, when adopting traditional SPI means of communication, slave is because the passive communication command of accepting, when pulsed frequency is higher or pulsed frequency lower the time, the operation meeting frequently of the meter of slave is interrupted by the SPI communication, thereby causes result of calculation to follow the signal source of input inconsistent.When adopting the SPI means of communication of the present utility model, slave is chosen in to calculate and drags down the Ready line after finishing and begin communication, and through observing for a long time, the result of calculation of slave is consistent with the signal of input, and in measurement range, error is ± 1Hz.
By experimental result as can be known, the utility model can be guaranteed the correctness of other operations of SPI communication two party, can guarantee that the SPI communication two party carries out the complete of the data that relate to when other calculate.
Claims (1)
1. SPI communication interface, main frame and at least one slave, MISO line, MOSI line, SCK line and CS line of comprising the SPI communication, it is characterized in that: every described slave has a Ready line to be connected with described main frame, is used for guaranteeing the data integrity of SPI communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220735758 CN203117968U (en) | 2012-12-28 | 2012-12-28 | SPI (Serial Peripheral Interface) communication interface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220735758 CN203117968U (en) | 2012-12-28 | 2012-12-28 | SPI (Serial Peripheral Interface) communication interface |
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| CN203117968U true CN203117968U (en) | 2013-08-07 |
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| CN 201220735758 Expired - Fee Related CN203117968U (en) | 2012-12-28 | 2012-12-28 | SPI (Serial Peripheral Interface) communication interface |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077144A (en) * | 2012-12-28 | 2013-05-01 | 上海自动化仪表股份有限公司 | Serial peripheral interface (SPI) communication interface for ensuring data integrity, and communication method thereof |
| CN103744814A (en) * | 2014-01-06 | 2014-04-23 | 深圳市芯海科技有限公司 | High speed communication method by two lines |
| CN107819659A (en) * | 2017-10-24 | 2018-03-20 | 七玄驹智能科技（上海）有限公司 | A kind of intelligent level UNICOM communication network based on SPI |
-
2012
- 2012-12-28 CN CN 201220735758 patent/CN203117968U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077144A (en) * | 2012-12-28 | 2013-05-01 | 上海自动化仪表股份有限公司 | Serial peripheral interface (SPI) communication interface for ensuring data integrity, and communication method thereof |
| CN103744814A (en) * | 2014-01-06 | 2014-04-23 | 深圳市芯海科技有限公司 | High speed communication method by two lines |
| CN103744814B (en) * | 2014-01-06 | 2017-01-11 | 深圳市芯海科技有限公司 | High speed communication method by two lines |
| CN107819659A (en) * | 2017-10-24 | 2018-03-20 | 七玄驹智能科技（上海）有限公司 | A kind of intelligent level UNICOM communication network based on SPI |
| CN107819659B (en) * | 2017-10-24 | 2020-09-29 | 七玄驹智能科技（上海）有限公司 | Intelligent cascade communication network based on SPI |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160328 Address after: Zhabei District Shanghai City 200072 West Guangzhong Road No. 191 Building No. 7 Patentee after: Shanghai instrument and meter for automation company limited Address before: 200233, No. 41 Rainbow Road, Shanghai, Xuhui District Patentee before: Shanghai Automatic Industrument and Meter Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130807 Termination date: 20181228 |