CN104142876A - Function verification method and verification environmental platform for USB (universal serial bus) equipment controller modules - Google Patents
Function verification method and verification environmental platform for USB (universal serial bus) equipment controller modules Download PDFInfo
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Abstract
The invention discloses a function verification method for USB (universal serial bus) equipment controller modules. The function verification method is based on UVM (universal verification methodology), reference models which are built in a verification environmental platform are verified by the aid of a verification IP (intellectual property) of an AHB (advanced high-performance bus) and a verification IP of a USB host, and function verification is implemented on the USB equipment controller modules. The invention further discloses the verification environmental platform for implementing the verification method. The verification environmental platform is based on the UVM by the aid of systemverilog language and comprises an AHB universal verification assembly, a USB universal verification assembly, a virtual sequencer, a scoring table and a USB configuration file. The function verification method and the verification environmental platform have the advantages that module-level functions of USB equipment controllers can be quickly verified by the aid of the function verification method and the verification environmental platform, and accordingly the verification efficiency can be improved.
Description
Technical field
The present invention relates to integrated circuit (IC) design SOC(system level chip) functional verification field, particularly relate to a kind of USB(USB (universal serial bus)) the module level function checking method of device controller module.The invention still further relates to the verification environment platform adopting in a kind of described verification method.
Background technology
General verification methodology (UVM Universal Verification Methodology) is to lead by U.S. Mentor(is bright), Cadence(clang rises electronics technology) and Synopsys(Synopsys) company common release based on the system-level hardware description language of system verilog() verification methodology of new generation of language.The party's science of law is for verifying that slip-stick artist provides abundant class base resource and reusable method; Support the emulator of multiple manufacturers; Increasingly automated.
Checking IP(Intellectual Property intellecture property) be EDA(electric design automation) manufacturer is for some standard interfaces are as AHB(Advanced High-performance Bus system bus), APB(peripheral bus), the bus behavior model of the exploitation such as USB.In the functional verification of integrated circuit modules level, by using various checking IP can reach the object of building rapidly verification environment platform, accelerate project process.The system bus AHB generic validation assembly (UVC) of Cadence company exploitation is the ahb bus checking IP based on UVM.The general-purpose serial bus USB host verification IP of Denali company exploitation is a verification model based on USB2.0 agreement, contains the protocol layer of USB and the related communication of Physical layer.This general-purpose serial bus USB host verification IP is applicable to various checking language, and is applicable to VMM(verification methodology handbook), the verification environment platform of UVM.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of USB device controller module function verification method, can realize fast module level function checking, improves verification efficiency; For this reason, the present invention also will provide the verification environment platform adopting in a kind of described verification method.
For solving the problems of the technologies described above, USB device controller module function verification method of the present invention, to adopt following technical scheme to realize: adopt UVM, use system bus ahb bus checking IP and general-purpose serial bus USB host verification IP to build the reference model in verification environment platform, USB device controller module is implemented to functional verification.
The verification environment platform adopting in described verification method, adopts system verilog language, completes based on UVM; Comprise:
AHB generic validation assembly, is ahb bus agreement end (hereinafter to be referred as " AHB end ") verification environment submodule, for completing ahb bus operation;
USB generic validation assembly is usb host end verification environment submodule, for simulating the work of usb host;
Virtual sequence device, is virtual generator, does not connect what driver of taking in described AHB generic validation assembly and USB generic validation assembly, controls the generation order of the activation sequence unit of AHB end and usb host end on both upper stratas;
Scoring plug, is responsible for the data that the described AHB generic validation assembly of collection and USB generic validation assembly produce, and automatically compares, to judge that whether transmission is correct;
USB configuration file, is in charge of whole verification environment platform, the configuration information of synchronous AHB end and usb host end.
The present invention adopts verification methodology UVM of new generation, use the ahb bus checking IP of Cadence company and the usb host checking IP of Denali company to build the reference model in verification environment platform, utilize checking IP high efficient and reliable, be convenient to integrated feature, abundant multiplexing checking IP functional module, give full play to UVM activation sequence unit generation mechanism flexibly, fast construction verification environment platform, to USB device controller module carry out module level comprehensively, functional verification fast, complete efficiently, easily functional verification work, and verify abundant, complete; Can significantly improve verification efficiency, be a kind of advanced person's function verification method.
Brief description of the drawings
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is USB device controller module verification environment platform structure schematic diagram;
Fig. 2 is the activation sequence unit extensions schematic diagram in AHB generic validation assembly;
Fig. 3 is the activation sequence unit extensions schematic diagram in USB generic validation assembly.
Embodiment
According to technical solution provided by the invention, choose by reference to the accompanying drawings embodiment the enforcement of summary of the invention done to following specific descriptions:
Described USB device controller module function verification method, adopt UVM, use the ahb bus checking IP of Cadence company and the general-purpose serial bus USB host verification IP of Denali company to build the reference model in verification platform, USB device controller module is implemented to functional verification.
Described ahb bus checking IP, as the main equipment reference model on the ahb bus of USB device controller module, is used for configuring the internal register of USB device controller module.
Described general-purpose serial bus USB host verification IP is as usb host model, to USB device controller module reset, bus enumeration and initiation transmission.
Described enforcement functional verification refers to, on the one hand, verifies that by ahb bus IP produces register read-write activation sequence unit; On the other hand, verify that by usb host IP produces the activation sequence unit of the random USB issued transaction level that can retrain, in the virtual sequence that these two kinds of activation sequence unit produce at virtual sequence device, reach synchronously by the flow process control of agreement, jointly trigger verification environment working platform.Described verification environment platform automatization judgement response results, robotization statistical function coverage rate.
The described register read-write activation sequence unit that AHB end produces is to expand on the basis of ahb bus checking IP basis sequence units, has expanded reading task and writing task.The serial device of AHB end is also to expand on the basis of the former serial device of system bus ahb bus checking intellecture property IP, has added the virtual interrupt interface for flow process control.AHB end is by interrupt latency and read or write task, implements internal register configuration and the communication process control of USB device controller module.
The activation sequence unit of the described USB issued transaction level that usb host end produces is to expand on the issued transaction level sequence units basis of usb host checking IP, on the basis of described issued transaction level sequence units, add multiple tasks, be used for sending IN(input) issued transaction task, OUT(output) issued transaction task, PING(output inquiry at a high speed) issued transaction task, SETUP(set up) issued transaction task (comprise device address is set, equipment configuration is set) etc.The activation sequence unit of USB issued transaction level can generate at random, also can call individual task and realize; Complex incentive sequence units as the transmission of usb bus enumeration process, data etc. can be accomplished by above-mentioned task combination, provide powerful activation sequence unit combination mechanism based on UVM, the activation sequence unit of the described USB issued transaction level of usb host end can cover usb protocol transmission completely.
Verification environment platform 1 shown in Figure 1, to adopt in described verification method, adopts systemverilog language, completes based on UVM.It comprises: AHB generic validation assembly 2, USB generic validation assembly 3, virtual sequence device 6, scoring plug 5 and USB configuration file 8.
Described AHB generic validation assembly 2 is ahb bus agreement end verification environment submodules, for completing ahb bus operation.It comprises the each assembly in ahb bus agreement, as main equipment 9(as described in main equipment reference model), from equipment 10, moderator 11, code translator 12.After these assemblies are communicated with, the running of jointly simulating ahb bus system.Virtual sequence device 6, by main equipment 9 assembly transmitter register read-write activation sequence unit, is realized the reception and registration of AHB end register read-write activation sequence unit.
Described USB generic validation assembly 3, it is usb host end verification environment submodule, usb host model 17(wherein comprises usb host and monitor) be usb host checking IP, be used for simulating the work of usb host, as initiated transmission, answering equipment, reset, hang up and wake up etc.
Described in each, AHB generic validation assembly 2 and USB generic validation assembly 3 are encapsulated mouldings, configurable and reusable.Each described AHB generic validation assembly 2 and USB generic validation assembly 3 inside, comprise one or more agencies (Agent) module.In the embodiment shown in fig. 1 at the main equipment 9 of AHB generic validation assembly 2, from equipment 10, moderator 11 and code translator 12, be respectively equipped with a proxy module; In USB generic validation assembly 3, be provided with a proxy module.Each proxy module is made up of serial device 13, driver 14 and watch-dog 15.Described serial device 13 is senior excitation generators, according to the demand of below driver 14, controls activation sequence unit and produces.Described driver 14 is entities of an active, and abstract data sequence unit is changed into logical signal, is driven on ahb bus interface.Described watch-dog 15 is passive entities, is responsible for collecting interface signal, refinement event, to do coverage rate analysis, protocol testing and data comparison.
Described virtual sequence device 6 is virtual generators, does not connect any driver in described AHB generic validation assembly 2 and USB generic validation assembly 3, controls the generation order of the activation sequence unit of AHB end and USB end on both upper stratas.
Described scoring plug 5, the data that the described AHB generic validation assembly 2 of responsible collection and USB generic validation assembly 3 produce also compare automatically, to judge that whether transmission is correct.For the transmission of the OUT direction of usb host end, AHB holds the data that the data received (be AHB receive bag 19) in Fig. 1 and usb host end send (be USB send bag 21) in Fig. 1 will be in collected scoring plug 5 relatively; For the transmission of the IN direction of usb host end, data that usb host end is received (be USB receive bag 20) in Fig. 1 can and AHB hold the data sent (be AHB send bag 18) in Fig. 1 in collected scoring plug 5, to compare.Described data are by the port transmission of transmitting stage model (TLM) the mechanism definition of UVM.
Described USB configuration file is in charge of whole verification environment platform, the configuration information of synchronous AHB end and USB end.These configuration informations comprise the initial configuration of USB device controller module internal register and the relevant configuration information of usb host.As maximum packet length, transport-type and transmission speed etc.
In the present invention, need checking to as if USB device controller module 4(DUT), USB device controller module 4 one end are connected with AHB generic validation assembly 2 by ahb bus interface, and the other end is connected with the usb host model 17 in USB generic validation assembly 3 by usb bus.Ahb bus checking IP configures the associated inner register of USB device controller module 4 by ahb bus, make USB device controller module 4 connect usb host, after usb host checking IP confirms that usb bus connects, initiates reset signal; USB device controller module 4 is as the go forward side by side reset operation of line correlation register of reset answer; Usb host checking IP resets and starts to carry out bus enumeration after flow process finishes confirmation both sides, treats the laggard row data communication of bus enumeration success; USB device controller module 4 is made and being replied, and transmits the data in its internal register under the operation of ahb bus checking IP.Communication data between usb host and USB device controller module 4 is collected in scoring plug 5 and automatically compares in transmitting procedure.The monitor of each verification environment submodule is responsible for monitoring ahb bus and usb host behavior, if interface signal is not inconsistent with agreement, reports an error.
Shown in Fig. 1, described verification environment platform 1 is the verification platform of a layering: the activation sequence unit applying at top layer definition AHB end and usb host end.This activation sequence unit exists with the nested activation sequence unit form of complexity, describes the overall process of current test.For example, comprise that AHB end initialization register sequence units, usb host send reset signal sequence units, usb host and address sequence unit, usb host are set configuration sequence unit, AHB end are set reply address and sequence units, AHB end are set reply that configuration arranges sequence units, usb host sends data sequence unit and AHB end receiving data sequence unit etc.These activation sequence unit are distributed in the actual sequence device 13 in AHB generic validation assembly 2 and USB generic validation assembly 3 by virtual sequence device 6.On the one hand, the sequence name that the serial device 13 of main equipment 9 assemblies in AHB generic validation assembly 2 obtains transmitting from described virtual sequence device 6, produce the activation sequence unit of corresponding AHB read-write register; The driver 14 of main equipment 9 assemblies obtains these activation sequence unit and is driven on ahb bus from serial device 13, completes read-write operation; The monitor 15 of the main equipment 9 assemblies signalizing activity of monitoring ahb bus in real time.On the other hand, the sequence name that the serial device 13 in USB generic validation assembly 3 obtains transmitting from described virtual sequence device 6, produce corresponding USB issued transaction sequence units; Driver 14 in USB generic validation assembly 3 obtains USB issued transaction sequence units from its serial device 13, and is transmitted to usb host checking IP; Usb host checking IP resolves this USB issued transaction sequence units, and changes into USB interface signal, is driven on usb bus; The watch-dog that usb host checking IP carries is responsible for detecting usb bus activity and does protocol testing.
Configuration module described in Fig. 1 in proxy module 16 is responsible for the mode of operation of the each assembly of configuration (comprise described AHB generic validation assembly 2, USB generic validation assembly 3, main equipment 9, from equipment 10, moderator 11 and code translator 12), aggressive mode if, serial device 13, driver 14 and monitor 15 are worked, if Passive Mode is worked when front assembly only has monitor 15.In this verification environment platform, all assemblies are all aggressive modes.
Activation sequence unit in each serial device of described AHB generic validation assembly 2 is by expanding layer by layer.Shown in Figure 2, it has expressed the expansion process of activation sequence unit in the serial device 13 of main equipment 9 assemblies of AHB generic validation assembly 2.
First, the default master sequence units that ahb bus checking IP provides is basic sequence units, has defined an ahb bus transfer sequence unit that can be random in this default master sequence units.This verification environment platform is on the basis of default master sequence, create user-defined basic sequence units, and user-defined basic sequence units is done to following expansion, add two tasks: write register [write_reg_single(addr, data), wherein, addr represents the register address writing, the data that data indicates to write] task (being called for short " writing task ") and read register [read_reg_single(addr, data), wherein, the register address that addr indicates to read, data represents the data of reading] task (being called for short " reading task "), by the direction of operating of these two task restriction ahb bus transfer sequence unit, address, type, data width and data value etc.Then, then taking user-defined basic sequence units as basis, expand more complicated activation sequence unit, increase a series of meaningful autotelic read-write operations, thereby realize certain scene.For example set up bag and process sequence units.Process in sequence units at the bag of setting up, called the interrupt latency statement of serial device, (register, read register address that read register address is `SETUP_1 are `SETUP_2 to multiple read register task ... read register address is the register of `SETUP_n etc.), thereby complete USB device controller module 4 and received that USB sets up after bag, a series of flow processing of doing.
In described USB generic validation assembly, the activation sequence unit extensions process of serial device, shown in Figure 3.Equally, from simple to complexity.The full detail that USB basis sequence units comprises USB issued transaction, as the rank of USB transmission, type, device address, equipment end period, data length and the data value etc. of issued transaction, these information can generate at random.User-defined basic sequence units has been expanded USB basis sequence units, on its basis, defined IN issued transaction task [addr(USB device address), the endpoint number of ep(USB devices communicating)], OUT issued transaction task (addr, ep), PING(output inquiry at a high speed) issued transaction task (addr, ep), address arranges issued transaction task (addr) and configuration issued transaction task [addr, the configuration information of config(USB equipment)] etc. is set.These task inside have retrained address, endpoint number, type and the data etc. of issued transaction closer, make the transmission of task have clear and definite object and concrete meaning.The address combination sequence that arranges shown in Fig. 3 has further expanded user-defined basic sequence, it has called address and issued transaction task (device address is 01) and IN issued transaction task has been set (device address is 01, equipment end period is 0), both combinations have jointly completed usb host and have sent foundation bag, device address is set, and obtains all processes that equipment is responded.
By embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these are also considered as protection scope of the present invention.
Claims (14)
1. a general-purpose serial bus USB device controller functions of modules verification method, it is characterized in that: based on verification methodology UVM, use system bus ahb bus checking intellecture property IP and general-purpose serial bus USB host verification intellecture property IP to build the reference model in verification environment platform, general-purpose serial bus USB device controller module is implemented to functional verification.
2. method according to claim 1, it is characterized in that: IP is as the main equipment reference model on the system bus AHB of general-purpose serial bus USB device controller module for described system bus ahb bus checking intellecture property, be used for the internal register of configure generic serial bus USB device controller module; Described general-purpose serial bus USB host verification intellecture property IP is as general-purpose serial bus USB main frame model, to general-purpose serial bus USB device controller module reset, bus enumeration and initiation transmission.
3. method according to claim 1 and 2, is characterized in that: described enforcement functional verification refers to, on the one hand, produces register read and write activation sequence unit by system bus ahb bus checking intellecture property IP; On the other hand, produce the activation sequence unit of the random general-purpose serial bus USB issued transaction level that can retrain by general-purpose serial bus USB host verification intellecture property IP, these two kinds of activation sequence unit reach synchronously by the flow process control of agreement in virtual sequence, jointly trigger verification environment working platform; Described verification environment platform automatization judgement response results, robotization statistical function coverage rate.
4. method according to claim 3, it is characterized in that: the described register read-write activation sequence unit that system bus AHB end produces is to expand on the basis of system bus ahb bus checking intellecture property IP basis sequence units, has expanded reading task and writing task; The serial device of system bus AHB end is also to expand on the basis of the former serial device of system bus ahb bus checking intellecture property IP, has added the virtual interrupt interface for flow process control; System bus AHB holds by interrupt latency and reading task or writing task, implements internal register configuration and the communication process control of general-purpose serial bus USB device controller module.
5. method according to claim 3, it is characterized in that: the activation sequence unit of the described general-purpose serial bus USB issued transaction level that general-purpose serial bus USB host side produces is to expand on the issued transaction level sequence units basis of general-purpose serial bus USB host verification intellecture property IP, on the basis of described issued transaction level sequence units, add multiple tasks, be used for sending input IN issued transaction task, output OUT issued transaction task, export inquiry PING issued transaction task and set up SETUP issued transaction task at a high speed.
6. method according to claim 5, is characterized in that: the activation sequence unit of general-purpose serial bus USB issued transaction level can generate at random, also can call individual task and realize; Usb bus enumeration process and data transmission realize by described task combination.
7. the verification environment platform that the arbitrary described method of claim 1-6 adopts, is characterized in that: adopt system verilog language, based on verification methodology, UVM completes; Comprise:
System bus AHB generic validation assembly, is system bus AHB end verification environment submodule, operates for completion system bus ahb bus;
General-purpose serial bus USB generic validation assembly, is general-purpose serial bus USB host side verification environment submodule, is used for simulating the work of general-purpose serial bus USB main frame;
Virtual sequence device, it is virtual generator, do not connect any driver in described system bus AHB generic validation assembly and general-purpose serial bus USB generic validation assembly, in the activation sequence unit of the upper strata of described system bus AHB generic validation assembly and general-purpose serial bus USB generic validation assembly control system bus AHB end and general-purpose serial bus USB host side generation order;
Scoring plug, is responsible for gathering the data of described system bus AHB generic validation assembly and the generation of general-purpose serial bus USB generic validation assembly, and automatically compares, to judge that whether transmission is correct;
General-purpose serial bus USB configuration file, is in charge of whole verification environment platform, the configuration information of synchro system bus AHB end and general-purpose serial bus USB host side.
8. verification environment platform according to claim 7, it is characterized in that: IP is by the associated inner register of system bus ahb bus configure generic serial bus USB device controller module for system bus ahb bus checking intellecture property, makes general-purpose serial bus USB device controller module connection universal serial bus USB main frame; General-purpose serial bus USB host verification intellecture property IP initiates reset signal after confirming that general-purpose serial bus USB connects; General-purpose serial bus USB device controller module is made reset answer, the reset operation of the line correlation register of going forward side by side; General-purpose serial bus USB host verification intellecture property IP resets and starts to carry out bus enumeration after flow process finishes confirmation both sides, treats the laggard row data communication of bus enumeration success; General-purpose serial bus USB device controller module is made and is replied and transmit the data in its internal register under the operation of system bus ahb bus checking intellecture property IP.
9. verification environment platform according to claim 7, is characterized in that: system bus AHB generic validation assembly comprises the each assembly in system bus ahb bus agreement, comprises main equipment, from equipment, and moderator, code translator; After these assemblies are communicated with, the running of common simulation system bus ahb bus system; Virtual sequence device, by main equipment assembly transmitter register read-write activation sequence unit, is realized the reception and registration of system bus AHB end register read-write activation sequence unit.
10. verification environment platform according to claim 7, is characterized in that: the work of described general-purpose serial bus USB generic validation assembly simulation general-purpose serial bus USB main frame, comprises initiation transmission, answering equipment, reset, hangs up and wake up.
11. verification environment platforms according to claim 7, is characterized in that: each described system bus AHB generic validation assembly and general-purpose serial bus USB generic validation assembly are encapsulated mouldings, configurable and reusable; Each described system bus AHB generic validation assembly and general-purpose serial bus USB generic validation component internal, comprise one or more proxy modules; Each proxy module is made up of serial device, driver and watch-dog;
Described serial device is an excitation generator, according to the demand of below driver, controls activation sequence unit and produces;
Described driver is the entity of an active, and abstract data sequence is changed into logical signal, is driven on system bus ahb bus interface;
Described watch-dog is a passive entity, is responsible for collecting interface signal and refinement event, to do coverage rate analysis, protocol testing and data comparison; Be responsible for supervisory system bus ahb bus or general-purpose serial bus USB Host behavior, if interface signal is not inconsistent with agreement, report an error.
12. verification environment platforms according to claim 11, is characterized in that: the verification environment platform that described verification environment platform is a layering: the activation sequence unit applying in top layer define system bus AHB end and general-purpose serial bus USB host side; This activation sequence unit exists with nested activation sequence unit form, describes the overall process of current test; Comprise that system bus AHB end initialization register sequence units, general-purpose serial bus USB main frame send reset signal sequence units, general-purpose serial bus USB main frame and address sequence unit, general-purpose serial bus USB main frame are set configuration sequence unit, system bus AHB end are set reply address and sequence units, system bus AHB end are set reply that configuration arranges sequence units, general-purpose serial bus USB main frame sends data sequence unit and system bus AHB end receiving data sequence unit; These activation sequence unit are distributed in the actual sequence device in system bus AHB generic validation assembly and general-purpose serial bus USB generic validation assembly by described virtual sequence device; On the one hand,, the sequence name that the serial device of the main equipment assembly in system bus AHB generic validation assembly obtains transmitting from described virtual sequence device, produce corresponding system bus AHB end register read-write activation sequence unit; The driver of main equipment assembly obtains these register read-write activation sequence unit and is driven on system bus ahb bus from its serial device, completes read-write operation; The signalizing activity of the monitor real-time monitoring system bus ahb bus of described main equipment assembly; On the other hand, the sequence name that the serial device in general-purpose serial bus USB generic validation assembly obtains transmitting from described virtual sequence device, produce the activation sequence unit of corresponding general-purpose serial bus USB issued transaction level; Driver in general-purpose serial bus USB generic validation assembly obtains the activation sequence unit of general-purpose serial bus USB issued transaction level from its serial device, and is transmitted to general-purpose serial bus USB host verification intellecture property IP; General-purpose serial bus USB host verification intellecture property IP resolves the activation sequence unit of this general-purpose serial bus USB issued transaction level, and changes into general-purpose serial bus USB interface signal, is driven in general-purpose serial bus USB bus; The watch-dog that general-purpose serial bus USB host verification intellecture property IP carries is responsible for detecting general-purpose serial bus USB bus activity and does protocol testing.
13. verification environment platforms according to claim 7, it is characterized in that: for the transmission of the output OUT direction of general-purpose serial bus USB host side, the data that system bus AHB holds the data received and general-purpose serial bus USB host side to send will be in collected scoring plug relatively; For the transmission of the input IN direction of general-purpose serial bus USB host side, the data and system bus AHB that general-purpose serial bus USB host side is received holds the data of sending will be in collected scoring plug relatively; Described data are by the port transmission of the transmitting stage model mechanism definition of verification methodology UVM.
14. verification environment platforms according to claim 7, is characterized in that: the initial configuration that described configuration information comprises general-purpose serial bus USB device controller inside modules register and the relevant configuration information of general-purpose serial bus USB main frame; Comprise maximum packet length, transport-type and transmission speed.
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| CN106294895A (en) * | 2015-05-19 | 2017-01-04 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module level function verification method and verification environment platform |
| CN106294895B (en) * | 2015-05-19 | 2019-11-12 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module grade function verification method and verification environment platform |
| CN105301480A (en) * | 2015-11-19 | 2016-02-03 | 四川和芯微电子股份有限公司 | Test method of SOC chip |
| CN106502900A (en) * | 2016-10-24 | 2017-03-15 | 上海华力微电子有限公司 | A kind of AHB core random verification methods based on systemverilog |
| CN106502900B (en) * | 2016-10-24 | 2019-06-28 | 上海华力微电子有限公司 | A kind of AHB core random verification method based on systemverilog |
| CN108388516B (en) * | 2018-03-14 | 2021-07-23 | 上海微小卫星工程中心 | Special verification test system capable of reconstructing FPGA software |
| CN108388516A (en) * | 2018-03-14 | 2018-08-10 | 上海微小卫星工程中心 | The special verifying test system and method for reconfigurable FPGA software |
| CN109254937A (en) * | 2018-07-19 | 2019-01-22 | 芯启源(上海)半导体科技有限公司 | Usb hub, USB device enumeration method for detecting abnormality and computer storage medium |
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| CN111008508A (en) * | 2019-12-26 | 2020-04-14 | 山东方寸微电子科技有限公司 | Interface type IP system application verification platform and verification method |
| CN111008508B (en) * | 2019-12-26 | 2023-05-02 | 山东方寸微电子科技有限公司 | Application verification platform and method for interface type IP system |
| CN111523284A (en) * | 2020-03-30 | 2020-08-11 | 眸芯科技（上海）有限公司 | Method and device for converting EDA (electronic design automation) simulation configuration of chip and application |
| CN111523284B (en) * | 2020-03-30 | 2023-05-26 | 眸芯科技（上海）有限公司 | Method, device and application for converting chip EDA simulation configuration |
| CN111914501A (en) * | 2020-05-07 | 2020-11-10 | 电子科技大学 | Implementation method of FeRAM interface verification platform based on UVM verification methodology |
| CN112527705A (en) * | 2020-11-05 | 2021-03-19 | 山东云海国创云计算装备产业创新中心有限公司 | PCIe DMA data path verification method, device and equipment |
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