CN101026781B - Quasi full-synchronous high-precision rapid frequency measuring device and method - Google Patents
Quasi full-synchronous high-precision rapid frequency measuring device and method Download PDFInfo
- Publication number
- CN101026781B CN101026781B CN2007100668569A CN200710066856A CN101026781B CN 101026781 B CN101026781 B CN 101026781B CN 2007100668569 A CN2007100668569 A CN 2007100668569A CN 200710066856 A CN200710066856 A CN 200710066856A CN 101026781 B CN101026781 B CN 101026781B
- Authority
- CN
- China
- Prior art keywords
- counter
- frequency
- rising edge
- actual gate
- standard time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The measuring device includes waveform shaping circuit, crystal oscillator, programmable device, CPU and display unit. The input end of the waveform shaping circuit is connected to the input end of the programmable device. Connecting the programmable device, the crystal oscillator provides clock source for the programmable device. The programmable device is connected to CPU. CPU is in use for calculating frequency value. The output end of CPU is connected to the input end of the display circuit. The display circuit displays calculated result. Measuring phase difference between signal to be measured and standard clock raises measuring accuracy. Advantages are: quick measuring frequency with high precision, simple structure of circuit hardware, using dedicated chip to measure frequency to reduce cost, and using FPGA to implement the device.
Description
Technical field
The present invention relates to a kind of communication technical field, especially relate to a kind of quasi full-synchronous high-precision rapid frequency device and method of measurement thereof.
Background technology
Existing conventional frequency mensuration has the M method, T method and M/T method.The M method be by measurement standard in gate time the umber of pulse of measured signal calculate the measured signal frequency, its precision depends on gate width and measured signal frequency.The T method is by the cycle of measuring measured signal and asks its inverse to try to achieve its frequency that its certainty of measurement depends on the cycle and the accuracy of timekeeping of measured signal.Therefore the certainty of measurement of T method and M method is lower.The M/T method is to adopt for low frequency signal to survey periodic method, adopts the frequency measurement method for high-frequency signal.When the measured signal frequency was higher, usually the selection standard frequency signal was as signal strobe, and with measured signal as filler pulse, the count value of establishing measured signal is N, standard-frequency signal is f
S, its cycle is T
S, then the frequency measurement of this method of testing is f
x=N/T
S, because measured signal counting exists ± 1 error, so the accuracy of measuring is Δ f
x=± 1/T
SWhen the measured signal frequency is low, select for use measured signal as signal strobe usually, and with standard-frequency signal as filler pulse, the count value of the accurate frequency signal of bidding is N, standard frequency is f
S, the cycle is T
S, then the frequency measurement of this method of testing is f
x=1/ (N*T
S), because standard-frequency signal counting exists ± 1 error, so the accuracy of measuring is Δ f=± f
x 2/ f
SThe major defect of M/T method is: because the existence of ± 1 error is difficult to take into account the measurement of low frequency and high frequency accuracy, so certainty of measurement is lower.
In addition, also have synchronous frequency measurement method of multicycle and full frequency measurement method synchronously, the core concept of multicycle synchronizing frequency method is synchronous by signal strobe and measured signal, and T is controlled to be the integral multiple in measured signal cycle with gate time.During measurement, begin to open actual gate when detecting when the measured signal rising edge of a pulse arrives, and begin standard time clock is counted; The actual gate of end is prolonged in the rising that detects measured signal after actual gate reaches certain width once more, and stopping criterion frequency counter counting.Its principle is as follows:
Suppose that the count value of measured signal in actual gate is N
x, the standard frequency count value is N
s(as Fig. 4), then tested frequency calculating formula is:
Because actual gate is the integral multiple in measured signal cycle, so N
xBe accurate.And to the standard-frequency meter numerical value of N
sThen there is Δ N
s(| Δ N
s|≤1) error, promptly have ± 1 error, its actual count value should be N
s± Δ N
sThen be by the actual value of measured frequency:
Then the relative error of multicycle synchronizing frequency method is:
Existing Chinese patent application number is 200510103485.8, the Chinese patent in open day on November 15th, 2005 discloses a kind of fast frequency measuring system and method, it improves multicycle synchronizing frequency method, reduced by measured frequency, improve the standard time clock frequency, improved the certainty of measurement of frequency.But this method has reduced the frequency of measured signal, has prolonged the time of frequency measurement, and it carries out high-frequency count to measuring whole process, has consumed more system resources.
Full frequency measurement ratio juris synchronously: the moment starting gate that arrives simultaneously when the rising edge of measured signal and standard clock signal; After gate reaches certain width, begin to detect both rising edges, detect after the rising edge closed shutter simultaneously.But hardware circuit is difficult to realize.
Currently used frequency measuring method exists precision low, has ± 1 counting error; Measuring speed is relatively slow, and circuit structure is complicated and be difficult to shortcoming such as realization.
Summary of the invention
Technical problem to be solved by this invention provides that a kind of measuring speed is fast, precision is high, circuit structure is simple, realizes quasi full-synchronous high-precision rapid frequency device and method of measurement thereof easily.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of quasi full-synchronous high-precision rapid frequency device, it comprises: waveform shaping circuit, crystal oscillator, programming device, CPU and display unit, described programming device comprises that standard is entirely with footwork core frequency senser and communication interface, described standard comprises frequency divider with footwork core frequency senser entirely, phase-locked loop, the core controller unit, first counter, second counter and the 3rd counter, the output output measured signal of described waveform shaping circuit is to described first counter and described core controller unit, described crystal oscillator provides the clock source, described crystal oscillator arrives described second counter and described core controller unit through described frequency divider outputting standard clock signal, described crystal oscillator arrives described the 3rd counter and described core controller unit through described phase-locked loop output phase clock signal, the output of described core controller unit respectively with described first counter, described second counter, the input of described the 3rd counter and described communication interface is connected, described first counter, the output of described second counter and described the 3rd counter is connected with the input of described communication interface, described communication interface is connected with described CPU, and described CPU is according to formula
Calculate the frequency values of measured signal, wherein N
1Be the pulse number of the phase clock between the 1st standard frequency rising edge in actual gate rising edge of a pulse and the actual gate pulse, N '
2Be the actual gate pulse trailing edge and the pulse number of the phase clock between the 1st standard time clock rising edge afterwards, N
2Be pulse number and the N ' of a standard time clock rising edge to the phase clock between the next standard time clock rising edge
2Difference, N
xFor opening first standard time clock rising edge behind the actual gate to the pulse number of closing the standard time clock between last standard time clock rising edge before the actual gate, N
sFor opening actual gate to the pulse number of closing the measured signal between the actual gate, actual gate is opened at actual gate rising edge of a pulse, at actual gate pulse trailing edge, actual closing gate, f
pBe the frequency of phase clock, f
sBe the frequency of standard time clock, the output of described CPU is connected with the input of described display unit, and the result that display unit will calculate shows.
A kind of quasi full-synchronous high-precision rapid frequency method is by waveform shaping circuit output measured signal f
xTo first counter, provide clock source f by crystal oscillator
c, f
cThrough frequency divider outputting standard clock signal fs to second counter, f
cThrough phase-locked loop output phase clock signal f
pTo the 3rd counter, may further comprise the steps:
Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;
Step 2 is as measured signal f
xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate
xNumber, the second rolling counters forward standard time clock fs number, the 3rd rolling counters forward phase clock f
pNumber;
Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N
1
Step 4 is as the count value N of second counter
s〉=N
S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate
x, N
s, simultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping
1-N '
2N
1Be the pulse number of the phase clock between the 1st standard frequency rising edge in actual gate rising edge of a pulse and the actual gate pulse, N '
2Be the actual gate pulse trailing edge and the pulse number of the phase clock between the 1st standard time clock rising edge afterwards; N
S0Be the minimum counted number of pulses of standard counter;
Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula
Calculate the measured signal frequency; N
2Be pulse number and the N ' of a standard time clock rising edge to the phase clock between the next standard time clock rising edge
2Difference, N
sFor opening first standard time clock rising edge behind the actual gate to the pulse number of closing the standard time clock between last standard time clock rising edge before the actual gate, N
xFor opening actual gate to the pulse number of closing the measured signal between the actual gate, f
pBe the frequency of phase clock, f
sFrequency for standard time clock;
Step 6 shows the frequency that finally calculates in display unit.
Compared with prior art, the invention has the advantages that frequency measurement speed is fast, the precision height; Simple in structure, solved the defective of hardware circuit complexity in the past, take less relatively resource; Use special-purpose frequency measurement chip, the lowering apparatus cost; Can adopt FPGA to realize, its processing speed is faster, adapts at a high speed, real-time Measurement and analysis occasion, is widely used, and has great realistic meaning.
Description of drawings
Fig. 1 is an installation drawing of the present invention;
Fig. 2 is a programming device cut-away view of the present invention;
Fig. 3 is the full frequency measurement method experimental waveform figure synchronously of standard of the present invention;
Fig. 4 is multicycle synchronous frequency measurement method experimental waveform figure.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
A kind of quasi full-synchronous high-precision rapid frequency device, it comprises: waveform shaping circuit 1, crystal oscillator 2, model is the programming device 3 of EP2C5T144C8, model is CPU4 and the display unit 5 of LPC2132, the output of waveform shaping circuit 1 is connected with programming device 3 inputs, crystal oscillator 2 is connected with programming device 3, crystal oscillator 2 provides the clock source for programming device 3, programming device 3 is connected with CPU4, CPU4 is used for the calculated rate value, the output of CPU4 is connected with the input of display unit 5, and the result that display unit 5 will calculate shows.Programming device 3 comprises that standard is entirely with footwork core frequency senser and communication interface 37, accurate full output with footwork core frequency senser is connected with the input of communication interface 37, communication interface 37 is connected with CPU4, the output of waveform shaping circuit 1 is connected with accurate full input with footwork core frequency senser, and crystal oscillator 2 is connected with footwork core frequency senser entirely with standard.Waveform shaping circuit, crystal oscillator and display unit adopt prior art.
Standard comprises frequency divider 31 with footwork core frequency senser entirely, phase-locked loop 32 (being called for short PLL), core controller unit 33, first counter 34, second counter 35, the 3rd counter 36, the output of frequency divider 31 is connected with the input of second counter 35 and the input of core controller unit 33 respectively, the output of phase-locked loop 32 is connected with the input of the 3rd counter 35 and the input of core controller unit 33 respectively, the output of core controller unit 33 respectively with first counter 34, second counter 35, the input of the 3rd counter 36 and communication interface 37 is connected, first counter 34, the output of second counter 35 and the 3rd counter 36 is connected with the input of communication interface 37.
A kind of quasi full-synchronous high-precision rapid frequency method is characterized in that, may further comprise the steps:
Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;
Step 2 is as measured signal f
xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate
xNumber, the second rolling counters forward standard time clock f
sNumber, the 3rd rolling counters forward phase clock f
pNumber;
Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N
1
Step 4 is as the count value N of second counter
s〉=N
S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate
x, N
s, simultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping
1-N '
2N
1Be the pulse number of the phase clock between the 1st standard frequency rising edge in gate rising edge and the gate, N '
2Be the actual gate trailing edge and the pulse number of the 1st standard time clock afterwards;
Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula
Calculate the measured signal frequency;
Step 6 shows the frequency that finally calculates in display unit.
Principle of the present invention is as follows: use phase detectors to calculate gate and standard frequency phase difference as Fig. 3.Adopt a phase counter to count the pulse number N of the phase clock between gate rising edge and interior the 1st the standard frequency rising edge of gate
1, the actual gate trailing edge and the pulse number N ' of the 1st standard time clock afterwards
2
If the frequency of phase clock is f
p, then the actual count error of standard time clock in signal strobe is:
Order:
Then have:
The actual frequency of measured signal is:
Its measured value is:
Relative error:
By formula (7) as can be seen, can be by reducing
Improve certainty of measurement.
At f
S=1MHz, f
p=200MHz, N
S0Under=1000 measuring conditions: accurate full maximum error of measuring with footwork is 1 * 10
-5And the measure error of multi-period synchronizing method is 1 * 10 under the same conditions
-3Therefore, the present invention can be widely used in the high-acruracy survey field of fields of measurement, particularly frequency.
Claims (2)
1. quasi full-synchronous high-precision rapid frequency device, it is characterized in that it comprises: waveform shaping circuit, crystal oscillator, programming device, CPU and display unit, described programming device comprises that standard is entirely with footwork core frequency senser and communication interface, described standard comprises frequency divider with footwork core frequency senser entirely, phase-locked loop, the core controller unit, first counter, second counter and the 3rd counter, the output output measured signal of described waveform shaping circuit is to described first counter and described core controller unit, described crystal oscillator provides the clock source, described crystal oscillator arrives described second counter and described core controller unit through described frequency divider outputting standard clock signal, described crystal oscillator arrives described the 3rd counter and described core controller unit through described phase-locked loop output phase clock signal, the output of described core controller unit respectively with described first counter, described second counter, the input of described the 3rd counter and described communication interface is connected, described first counter, the output of described second counter and described the 3rd counter is connected with the input of described communication interface, described communication interface is connected with described CPU, and described CPU is according to formula
Calculate the frequency values of measured signal, wherein N
1Be the pulse number of the phase clock between the 1st standard frequency rising edge in actual gate rising edge of a pulse and the actual gate pulse, N '
2Be the actual gate pulse trailing edge and the pulse number of the phase clock between the 1st standard time clock rising edge afterwards, N
2Be pulse number and the N ' of a standard time clock rising edge to the phase clock between the next standard time clock rising edge
2Difference, N
sFor opening first standard time clock rising edge behind the actual gate to the pulse number of closing the standard time clock between last standard time clock rising edge before the actual gate, N
xFor opening actual gate to the pulse number of closing the measured signal between the actual gate, actual gate is opened at actual gate rising edge of a pulse, at actual gate pulse trailing edge, actual closing gate, f
pBe the frequency of phase clock, f
sBe the frequency of standard time clock, the output of described CPU is connected with the input of described display unit, and the result that described display unit will calculate shows.
2. a quasi full-synchronous high-precision rapid frequency method is exported measured signal f by waveform shaping circuit
xTo first counter, provide clock source f by crystal oscillator
c, f
cThrough frequency divider outputting standard clock signal f
sTo second counter, f
cThrough phase-locked loop output phase clock signal f
pTo the 3rd counter, it is characterized in that, may further comprise the steps:
Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;
Step 2 is as measured signal f
xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate
xNumber, the second rolling counters forward standard time clock f
sNumber, the 3rd rolling counters forward phase clock f
pNumber;
Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N
1
Step 4 is as the count value N of second counter
s〉=N
S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate
x, N
s, simultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping
1-N '
2N
1Be the pulse number of the phase clock between the 1st standard frequency rising edge in actual gate rising edge of a pulse and the actual gate pulse, N '
2Be the actual gate trailing edge and the pulse number of the phase clock between the 1st standard time clock rising edge afterwards; N
S0Be the minimum counted number of pulses of standard counter;
Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula
Calculate the measured signal frequency; N
2Be pulse number and the N ' of a standard time clock rising edge to the phase clock between the next standard time clock rising edge
2Difference, N
sFor opening first standard time clock rising edge behind the actual gate to the pulse number of closing the standard time clock between last standard time clock rising edge before the actual gate, N
xFor opening actual gate to the pulse number of closing the measured signal between the actual gate, f
pBe the frequency of phase clock, f
sFrequency for standard time clock;
Step 6 shows the frequency that finally calculates in display unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100668569A CN101026781B (en) | 2007-01-23 | 2007-01-23 | Quasi full-synchronous high-precision rapid frequency measuring device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100668569A CN101026781B (en) | 2007-01-23 | 2007-01-23 | Quasi full-synchronous high-precision rapid frequency measuring device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101026781A CN101026781A (en) | 2007-08-29 |
| CN101026781B true CN101026781B (en) | 2010-12-08 |
Family
ID=38744606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100668569A Expired - Fee Related CN101026781B (en) | 2007-01-23 | 2007-01-23 | Quasi full-synchronous high-precision rapid frequency measuring device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101026781B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102749508A (en) * | 2011-04-20 | 2012-10-24 | 北京德威特继保自动化科技股份有限公司 | Frequency measurement device and method |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819231B (en) * | 2010-03-18 | 2014-08-06 | 天津农学院 | High-resolution frequency measurement method with continuous counting interval marking |
| CN102035455B (en) * | 2010-11-30 | 2012-11-21 | 中冶南方（武汉）自动化有限公司 | M/T speed measuring method for frequency converter |
| CN102109552B (en) * | 2010-12-14 | 2013-07-31 | 广东大普通信技术有限公司 | High-frequency and high-speed frequency testing system and method based on phase locking technique |
| CN102116797A (en) * | 2010-12-29 | 2011-07-06 | 天津七六四通信导航技术有限公司 | High accuracy numerical frequency measurement method based on FPGA |
| CN102495283B (en) * | 2011-12-09 | 2014-01-15 | 中国人民解放军第二炮兵计量站 | Self-adaptive equal-precision frequency measuring method |
| CN103235178A (en) * | 2013-04-26 | 2013-08-07 | 河南科技大学 | Double-button equal-precision frequency meter and calculating method thereof |
| CN104375004A (en) * | 2013-08-14 | 2015-02-25 | 苏州海博智能系统有限公司 | Method and system for measuring crystal oscillator frequency error |
| US9077328B1 (en) * | 2014-01-17 | 2015-07-07 | Broadcom Corporation | Method and apparatus for reference-less repeater with digital control |
| CN104215307B (en) * | 2014-10-14 | 2017-09-29 | 上海理工大学 | Double sprocket pulse interpolation counters and its implementation for flow standard device |
| CN105629062B (en) * | 2014-11-07 | 2019-05-03 | 北京北广科技股份有限公司 | A kind of frequency detecting method of variable frequency sine-wave |
| CN104483544B (en) * | 2014-12-01 | 2017-11-10 | 陕西海泰电子有限责任公司 | Single channel counter high accuracy frequency/period measuring method |
| CN104931779A (en) * | 2015-05-08 | 2015-09-23 | 中国电子科技集团公司第四十一研究所 | Single-channel realized continuous frequency measure method |
| CN105067054A (en) * | 2015-07-24 | 2015-11-18 | 浪潮集团有限公司 | Instantaneous flow rate detection method based on 8051 single-chip microcomputer |
| CN105486919B (en) * | 2015-12-22 | 2018-09-14 | 南京信息工程大学 | A kind of frequency measuring equipment based on FPGA |
| CN106918740B (en) * | 2015-12-28 | 2020-06-19 | 普源精电科技股份有限公司 | Equal-precision frequency measurement device and method |
| CN106597097A (en) * | 2016-12-28 | 2017-04-26 | 吉林大学 | High-precision frequency measurement method |
| CN107145419B (en) * | 2017-05-31 | 2020-05-08 | 河南思维轨道交通技术研究院有限公司 | Method for measuring frequency of external crystal oscillator of CPU |
| CN107782964B (en) * | 2017-09-29 | 2021-01-29 | 北京广利核系统工程有限公司 | Measuring system and measuring method capable of selectively outputting pulse signal frequency and counting |
| CN109358232A (en) * | 2018-10-25 | 2019-02-19 | 贵州大学 | A method of measurement HF current transformer frequency response |
| CN109283833A (en) * | 2018-10-26 | 2019-01-29 | 北京无线电测量研究所 | A kind of time statistical system and method |
| CN109856472B (en) * | 2018-12-13 | 2021-06-29 | 江汉大学 | Miniaturized fishpond fishing calibrating device based on multi-path detection signals |
| CN112698093A (en) * | 2020-12-17 | 2021-04-23 | 南京爱浦克施电气有限公司 | High-precision quick frequency measuring device |
| CN114924119B (en) * | 2022-07-21 | 2022-10-04 | 深圳市英特瑞半导体科技有限公司 | Clock chip and frequency measuring method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1389736A (en) * | 2001-06-04 | 2003-01-08 | 浙江大学 | AC signal measuring controller for power system |
| CN1862263A (en) * | 2005-09-19 | 2006-11-15 | 华为技术有限公司 | Fast frequency measuring system and method |
-
2007
- 2007-01-23 CN CN2007100668569A patent/CN101026781B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1389736A (en) * | 2001-06-04 | 2003-01-08 | 浙江大学 | AC signal measuring controller for power system |
| CN1862263A (en) * | 2005-09-19 | 2006-11-15 | 华为技术有限公司 | Fast frequency measuring system and method |
Non-Patent Citations (6)
| Title |
|---|
| CN 1389736 A,全文. |
| JP特開2000-88899A 2000.03.31 |
| JP特開2003-329740A 2003.11.19 |
| JP特開2003-337149A 2003.11.28 |
| 吴文全等.完全同步法实现对相位差的高精度测量.计量技术.2005,13-15. * |
| 谢登科等.基于数字移相的高精度脉宽测量系统及其FPGA实现.电子技术应用.2004,27-29. * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102749508A (en) * | 2011-04-20 | 2012-10-24 | 北京德威特继保自动化科技股份有限公司 | Frequency measurement device and method |
| CN102749508B (en) * | 2011-04-20 | 2015-08-12 | 北京德威特继保自动化科技股份有限公司 | Frequency measuring equipment and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101026781A (en) | 2007-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101026781B (en) | Quasi full-synchronous high-precision rapid frequency measuring device and method | |
| CN100501421C (en) | Fast frequency measuring system and method | |
| CN103248356B (en) | A kind of counter and implementation method based on adopting phase-locked loop pulse interpolation technology | |
| CN103487649B (en) | Method and device capable of measuring both frequency of continuous waves and frequency of pulse modulation carrier waves | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN100468060C (en) | Equal observations method and measuring device of rotary table rate | |
| CN102116797A (en) | High accuracy numerical frequency measurement method based on FPGA | |
| CN105549379A (en) | Synchronous measurement apparatus based on high precision time reference triggering and method thereof | |
| CN105486919A (en) | Frequency measurement device based on FPGA | |
| CN103941622A (en) | Method for adopting high-accuracy pulse per second frequency multiplication to produce sampling pulse based on FPGA | |
| CN106597097A (en) | High-precision frequency measurement method | |
| CN102565673A (en) | Highly-reliable pulse counting test system based on FPGA (Field Programmable Gate Array) | |
| CN204422648U (en) | A kind of modulation domain frequency counter | |
| CN106302014B (en) | The signal measurement method of wide-range high-precision | |
| CN107870262A (en) | A kind of high-precision optical pumped magnetometer meter frequency device and method based on GPS time services | |
| CN106645780A (en) | Rotating speed detection method and system base on DSP | |
| CN104635046A (en) | Modulation domain frequency counter and continuous frequency measurement method thereof | |
| CN207123716U (en) | A kind of pulse signal time difference measuring device | |
| CN203929885U (en) | Based on FPGA etc. precision frequency testing system | |
| CN103105534A (en) | Phase difference measurement circuit and measurement method based on field programmable gata array (FPGA) identical periodic signals | |
| CN105629062A (en) | Frequency detection method for variable frequency sine wave | |
| CN104215307B (en) | Double sprocket pulse interpolation counters and its implementation for flow standard device | |
| EP2495574A1 (en) | Method for determining the frequency of a pulse input signal | |
| CN204789754U (en) | When precision frequency measurement system | |
| CN203191708U (en) | Precise time-interval measuring instrument |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 Termination date: 20140123 |