CN101026781A - Quasi full-synchronous high-precision rapid frequency measuring device and method - Google Patents

Abstract

The measuring device includes waveform shaping circuit, crystal oscillator, programmable device, CPU and display unit. The input end of the waveform shaping circuit is connected to the input end of the programmable device. Connecting the programmable device, the crystal oscillator provides clock source for the programmable device. The programmable device is connected to CPU. CPU is in use for calculating frequency value. The output end of CPU is connected to the input end of the display circuit. The display circuit displays calculated result. Measuring phase difference between signal to be measured and standard clock raises measuring accuracy. Advantages are: quick measuring frequency with high precision, simple structure of circuit hardware, using dedicated chip to measure frequency to reduce cost, and using FPGA to implement the device.

Description

A kind of quasi full-synchronous high-precision rapid frequency device and method of measurement

Technical field

The present invention relates to a kind of communication technical field, especially relate to a kind of quasi full-synchronous high-precision rapid frequency device and method of measurement.

Background technology

Existing conventional frequency mensuration has the M method, T method and M/T method.The M method be by measurement standard in gate time the umber of pulse of measured signal calculate the measured signal frequency, its precision depends on gate width and measured signal frequency.The T method is by the cycle of measuring measured signal and asks its inverse to try to achieve its frequency that its certainty of measurement depends on the cycle and the accuracy of timekeeping of measured signal.Therefore the certainty of measurement of T method and M method is lower.The M/T method is to adopt for low frequency signal to survey periodic method, adopts the frequency measurement method for high-frequency signal.When the measured signal frequency was higher, usually the selection standard frequency signal was as signal strobe, and with measured signal as filler pulse, the count value of establishing measured signal is N, standard-frequency signal is fs, its cycle is Ts, then the frequency measurement of this method of testing is f _x=N/Ts is because measured signal counting exists ± 1 error, so the accuracy of measuring is Δ f _x=± 1/Ts.When the measured signal frequency is low, select for use measured signal as signal strobe usually, and with standard-frequency signal as filler pulse, the count value of the accurate frequency signal of bidding is N, standard frequency is fs, the cycle is Ts, then the frequency measurement of this method of testing is f _x=1/ (N*Ts) is because standard-frequency signal counting exists ± 1 error, so the accuracy of measuring is Δ f=± f _x ²/ fs.The major defect of M/T method is: because the existence of ± 1 error is difficult to take into account the measurement of low frequency and high frequency accuracy, so certainty of measurement is lower.

In addition, also have synchronous frequency measurement method of multicycle and full frequency measurement method synchronously, the core concept of multicycle synchronizing frequency method is synchronous by signal strobe and measured signal, and T is controlled to be the integral multiple in measured signal cycle with gate time.During measurement, begin to open actual gate when detecting when the measured signal rising edge of a pulse arrives, and begin standard time clock is counted; The actual gate of end is prolonged in the rising that detects measured signal after actual gate reaches certain width once more, and stopping criterion frequency counter counting.Its principle is as follows:

Suppose that the count value of measured signal in actual gate is N _x, the standard frequency count value is N _s(as Fig. 4), then tested frequency calculating formula is

$f_x=\frac{N_x}{N_s}{f}_s---\left(1\right)$

Because actual gate is the integral multiple in measured signal cycle, so N _xBe accurate.And to the standard-frequency meter numerical value of N _sThen there is Δ N _s(| Δ N _s|≤1) error, promptly have ± 1 error, its actual count value should be N _s± Δ N _s

Then be by the actual value of measured frequency:

$f_0=\frac{N_x}{N_s\±{\mathrm{\ΔN}}_s}{f}_s---\left(2\right)$

Then the relative error of multicycle synchronizing frequency method is:

$\mathrm{\σ}=\frac{\left|f_0\text{-}{f}_x\right|}{f_0}\×100\%=\frac{\left|{\mathrm{\ΔN}}_s\right|}{N_s}\≤\frac{1}{N_s}---\left(3\right)$

Existing Chinese patent application number is 200510103485.8, the Chinese patent in open day on November 15th, 2005 discloses a kind of fast frequency measuring system and method, it improves multicycle synchronizing frequency method, reduced by measured frequency, improve the standard time clock frequency, improved the certainty of measurement of frequency.But this method has reduced the frequency of measured signal, has prolonged the time of frequency measurement, and it carries out high-frequency count to measuring whole process, has consumed more system resources.

Full frequency measurement ratio juris synchronously: the moment starting gate that arrives simultaneously when the rising edge of measured signal and standard clock signal; After gate reaches certain width, begin to detect both rising edges, detect after the rising edge closed shutter simultaneously.But hardware circuit is difficult to realize.

Currently used frequency measuring method exists precision low, has ± 1 counting error; Measuring speed is relatively slow, and circuit structure is complicated and be difficult to shortcoming such as realization.

Summary of the invention

Technical problem to be solved by this invention provides that a kind of measuring speed is fast, precision is high, circuit structure is simple, realizes quasi full-synchronous high-precision rapid frequency device and method of measurement thereof easily.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of quasi full-synchronous high-precision rapid frequency device, it comprises: waveform shaping circuit, crystal oscillator, programming device, CPU and display unit, the input of described waveform shaping circuit is connected with described programming device input, described crystal oscillator is connected with described programming device, crystal oscillator provides the clock source for programming device, described programming device is connected with described CPU, CPU is used for the calculated rate value, the output of described CPU is connected with the input of described display circuit, and the result that display circuit will calculate shows.

The described standard that comprises able to programme is entirely with footwork core frequency senser and communication interface, described standard is connected with the input of described communication interface with the output of footwork core frequency senser entirely, described communication interface is connected with described CPU, the output of described waveform shaping circuit is connected with the input of footwork core frequency senser entirely with described standard, and described crystal oscillator is connected with footwork core frequency senser entirely with described standard.

Described standard comprises frequency divider with footwork core frequency senser entirely, phase-locked loop, the core controller unit, first counter, second counter, the 3rd counter, the output of described frequency divider is connected with the input of described second counter and the input of described core controller unit respectively, the output of described phase-locked loop is connected with the input of described the 3rd counter and the input of described core controller unit respectively, the output of described core controller unit respectively with described first counter, described second counter, the input of described the 3rd counter and described communication interface is connected, described first counter, the output of described second counter and described the 3rd counter is connected with the input of described communication interface.

A kind of quasi full-synchronous high-precision rapid frequency method may further comprise the steps:

Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;

Step 2 is as measured signal f _xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate _xNumber, the second rolling counters forward standard time clock fs number, the 3rd rolling counters forward phase clock f _pNumber;

Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N ₁

Step 4 is as the count value N of second counter _s〉=N _S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate _x, N _sSimultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping ₁-N ' ₂N ₁Be the pulse number of the phase clock between the 1st standard frequency rising edge in gate rising edge and the gate, N ' ₂Be the actual gate trailing edge and the pulse number of the 1st standard time clock afterwards; N _S0Be the minimum counted number of pulses of standard counter;

Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula $f_{x1}=\frac{N_x}{N_s+f_s(N_1+N_2)/f_p}{f}_s$ Calculate the measured signal frequency;

Step 6 shows the frequency that finally calculates in display module.

Compared with prior art, the invention has the advantages that frequency measurement speed is fast, the precision height; Simple in structure, solved the defective of hardware circuit complexity in the past, take less relatively resource; Use special-purpose frequency measurement chip, the lowering apparatus cost; Can adopt FPGA to realize, its processing speed is faster, adapts at a high speed, real-time Measurement and analysis occasion, is widely used, and has great realistic meaning.

Description of drawings

Fig. 1 is an installation drawing of the present invention;

Fig. 2 is a programming device cut-away view of the present invention;

Fig. 3 is the full frequency measurement method experimental waveform figure synchronously of standard of the present invention;

Fig. 4 is multicycle synchronous frequency measurement method experimental waveform figure.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

A kind of quasi full-synchronous high-precision rapid frequency device, it comprises: waveform shaping circuit 1, crystal oscillator 2, model is the programming device 3 of EP2C5T144C8, model is CPU4 and the display unit 5 of LPC2132, the input of waveform shaping circuit 1 is connected with programming device 3 inputs, crystal oscillator 2 is connected with programming device 3, crystal oscillator 2 provides the clock source for programming device 3, programming device 3 is connected with CPU4, CPU4 is used for the calculated rate value, the output of CPU4 is connected with the input of display circuit 5, and the result that display circuit 5 will calculate shows.Programming device 3 comprises that standard is entirely with footwork core frequency senser and communication interface 37, accurate full output with footwork core frequency senser is connected with the input of communication interface 37, communication interface 37 is connected with CPU4, the output of waveform shaping circuit 1 is connected with accurate full input with footwork core frequency senser, and crystal oscillator 2 is connected with footwork core frequency senser entirely with standard.Waveform shaping circuit, crystal oscillator and display circuit adopt prior art.

Standard comprises frequency divider 31 with footwork core frequency senser entirely, phase-locked loop 32 (being called for short PLL), core controller unit 33, first counter 34, second counter 35, the 3rd counter 36, the output of frequency divider 31 is connected with the input of second counter 35 and the input of core controller unit 33 respectively, the output of phase-locked loop 32 is connected with the input of the 3rd counter 35 and the input of core controller unit 33 respectively, the output of core controller unit 33 respectively with first counter 34, second counter 35, the input of the 3rd counter 36 and communication interface 37 is connected, first counter 34, the output of second counter 35 and the 3rd counter 36 is connected with the input of communication interface 37.

A kind of quasi full-synchronous high-precision rapid frequency method is characterized in that, may further comprise the steps:

Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;

Step 2 is as measured signal f _xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate _xNumber, the second rolling counters forward standard time clock f _SNumber, the 3rd rolling counters forward phase clock f _pNumber;

Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N ₁

Step 4 is as the count value N of second counter _s〉=N _S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate _x, N _sSimultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping ₁-N ₂N ₁Be the pulse number of the phase clock between the 1st standard frequency rising edge in gate rising edge and the gate, N ₂Be the actual gate trailing edge and the pulse number of the 1st standard time clock afterwards;

Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula $f_{x1}=\frac{N_x}{N_s+f_s(N_1+N_2)\text{/}{f}_p}{f}_s$ Calculate the measured signal frequency;

Step 6 shows the frequency that finally calculates in display module.

Principle of the present invention is as follows: use phase detectors to calculate gate and standard frequency phase difference as Fig. 3.Adopt a phase counter to count the pulse number N of the phase clock between gate rising edge and interior the 1st the standard frequency rising edge of gate ₁, the actual gate trailing edge and the pulse number N ' of the 1st standard time clock afterwards ₂

If the frequency of phase clock is f _p, then the actual count error of standard time clock in signal strobe is:

${\mathrm{\&Delta;N}}_s=\frac{f_s}{f_p}(N_1\&PlusMinus;1)+\frac{f_s}{f_p}({\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="A20071006685600101.png"\; state="\{\{state\}\}">N</figure-callout>}}_2\&PlusMinus;1)---\left(4\right)$

Order: $\mathrm{\&Delta;}{N}_s^{\&prime;}=\&PlusMinus;2\frac{f_s}{f_p}$

Then have:

${\mathrm{\&Delta;N}}_s=\frac{f_s}{f_p}(N_1+N_2)+\mathrm{\&Delta;}{N}_s^{\&prime;}$

The actual frequency of measured signal is:

$f_1=\frac{N_x}{N_s+f_s(N_1+N_2)/f_p+\mathrm{\&Delta;}{N}_s^{\&prime;}}{f}_s---\left(5\right)$

Its measured value is:

$f_2=\frac{N_x}{N_s+f_s(N_1+N_2)/f_p}{f}_s---\left(6\right)$

Relative error:

${\mathrm{\&sigma;}}^{\&prime;}=\frac{|f_1-{\mathrm{<figure-callout\; id="2"\; label="f"\; filenames="A20071006685600101.png"\; state="\{\{state\}\}">f</figure-callout>}}_2|}{f_1}\&times;100\%=\frac{\left|\mathrm{\&Delta;}{N}_s^{\&prime;}\right|}{N_s}\&le;2\frac{f_s}{f_p}\frac{1}{N_s}$

(7)

By formula (7) as can be seen, can be by reducing

Improve certainty of measurement.

At fs=1MHz, f _p=200MHz, N _S0Under=1000 measuring conditions: accurate full maximum error of measuring with footwork is 1 * 10 ^-5And the measure error of multi-period synchronizing method is 1 * 10 under the same conditions ^-3Therefore, the present invention can be widely used in the high-acruracy survey field of fields of measurement, particularly frequency.

Claims (4)

1. quasi full-synchronous high-precision rapid frequency device, it is characterized in that it comprises: waveform shaping circuit, crystal oscillator, programming device, CPU and display unit, the input of described waveform shaping circuit is connected with described programming device input, described crystal oscillator is connected with described programming device, crystal oscillator provides the clock source for programming device, described programming device is connected with described CPU, CPU is used for the calculated rate value, the output of described CPU is connected with the input of described display circuit, and the result that display circuit will calculate shows.

2. a kind of quasi full-synchronous high-precision rapid frequency device according to claim 1, it is characterized in that described programming device comprises that standard is entirely with footwork core frequency senser and communication interface, described standard is connected with the input of described communication interface with the output of footwork core frequency senser entirely, described communication interface is connected with described CPU, the output of described waveform shaping circuit is connected with the input of footwork core frequency senser entirely with described standard, and described crystal oscillator is connected with footwork core frequency senser entirely with described standard.

3. a kind of quasi full-synchronous high-precision rapid frequency device according to claim 1, it is characterized in that described standard comprises frequency divider with footwork core frequency senser entirely, phase-locked loop, the core controller unit, first counter, second counter, the 3rd counter, the output of described frequency divider is connected with the input of described second counter and the input of described core controller unit respectively, the output of described phase-locked loop is connected with the input of described the 3rd counter and the input of described core controller unit respectively, the output of described core controller unit respectively with described first counter, described second counter, the input of described the 3rd counter and described communication interface is connected, described first counter, the output of described second counter and described the 3rd counter is connected with the input of described communication interface.

4. a quasi full-synchronous high-precision rapid frequency method is characterized in that, may further comprise the steps:

Step 1 is respectively with first counter, second counter, the 3rd counter O reset, initialization programming device;

Step 2 is as measured signal f _xRising edge when arriving, open actual gate and, start first counter, second counter and the 3rd counter simultaneously, first rolling counters forward pulse f to be measured with reference to gate _xNumber, the second rolling counters forward standard time clock fs number, the 3rd rolling counters forward phase clock f _pNumber;

Step 3, when first rising edge that runs into standard time clock, the 3rd counter suspends plus coujnt, and keeps current count value N ₁

Step 4 is as the count value N of second counter _s≤ N _S0Afterwards, close, wait for the rising edge of measured signal, close actual gate and stop first counter, second counter, keep its count value N respectively with reference to gate _x, N _sSimultaneously the 3rd counter is done to subtract 1 and is counted on the basis of former count value, and till the rising edge of standard signal once more, its final count value is N when stopping ₁-N ₂'; N ₁Be the pulse number of the phase clock between the 1st standard frequency rising edge in gate rising edge and the gate, N ₂' be the actual gate trailing edge and the pulse number of the 1st standard time clock afterwards;

Step 5 is transferred to CPU with the count value of first counter, second counter, the 3rd counter by communication interface, and CPU is according to formula $f_{x1}=\frac{N_x}{N_s+f_s(N_1+N_2)/f_p}{f}_s$ Calculate the measured signal frequency;

Step 6 shows the frequency that finally calculates in display module.

Images