CN1159589C - AC signal measuring controller for power system - Google Patents
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- CN1159589C CN1159589C CNB01119393XA CN01119393A CN1159589C CN 1159589 C CN1159589 C CN 1159589C CN B01119393X A CNB01119393X A CN B01119393XA CN 01119393 A CN01119393 A CN 01119393A CN 1159589 C CN1159589 C CN 1159589C
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Abstract
The present invention relates to an AC signal measuring controller for power systems, which comprises a microprocessor system, an A/D converter and a self-adaptive equal-interval sampling pulse generator, wherein the self-adaptive equal-interval sampling pulse generator can automatically track and lock the fundamental frequency of measured signals no matter how the frequency of the measured signals changes, and can realize equal interval sampling. The controller of the present invention has the advantages of simple structure and low cost; besides, the real-time parameters of the power systems, particularly the measurement precision of phase angles, can be greatly improved with the application of the present invention.
Description
Technical field
The present invention relates to the AC signal measuring controller of electric system.
Background technology
The safe and reliable operation of electric system and quality of power supply standard, all require measuring and controlling accurately to measure the POWER SYSTEM STATE vector, comprise voltage, electric current phasor, the levels of precision of its measurement not only has influence on the precision of power calculation, electric energy metrical, and closely related with the accuracy and the reliability of system decision-making in real time.Owing to the development of digital processing technology, progressively replace the measure and control device of employing direct current transmitter based on the AC sampling measure and control device of digital processing algorithm.At present, the maximum digital processing algorithm of AC sampling application is exactly the discrete Fourier transform (DFT) algorithm.The discrete Fourier transform (DFT) algorithm can obtain the effective value and the phase angle of tested phasor simultaneously, and therefore, along with the development of synchronous measurement technique, its application is extensive day by day.
But whether the precision of discrete Fourier transform (DFT) algorithm reflects a complete cycle (referring to first-harmonic, down together) of measured signal based on the sampled data in its each data window, so is subjected to the influence of measured signal frequency (referring to fundamental frequency, down together) drift bigger.Usually sample frequency becomes certain multiple relation with the measured signal rated frequency, therefore, when measured signal frequency and its rated frequency generation skew, the error of calculation of discrete Fourier transform (DFT) algorithm is not allowed to ignore, and the control accuracy based on its result of calculation is had a strong impact on.Yet the randomness that power system load changes has determined that the frequency change of electric system is inevitable.
The key that improves the discrete Fourier transform (DFT) arithmetic accuracy is that sample frequency changes with the variation of frequency input signal, thereby each sampled data window of assurance discrete Fourier transform (DFT) algorithm can both reflect a complete cycle of measured signal.The AC signal measuring controller of electric system at present has A/D converter, microprocessor system, the control A/D converter is finished analog-to-digital sampling pulse and is generally produced by microprocessor, its sample frequency major part is changeless, also have by software according to the measured signal frequency change, revise sample frequency by the electric weight error that the discrete Fourier transform (DFT) algorithm is tried to achieve, this method not only implements the complexity height, and because the error of discrete Fourier transform (DFT) algorithm gained electric weight is to be similar to be directly proportional with frequency offset, thereby still there is round-off error.
Summary of the invention
In view of the foregoing, purpose of the present invention aims to provide a kind of cheap, simple in structure, can follow the tracks of and lock the fundamental frequency of measured signal effectively, realize the self-adaptation equal interval sampling, reliably control A/D converter and finish analog to digital conversion, the AC signal measuring controller of the electric system that measuring accuracy is high.
For achieving the above object, the measure that the present invention takes is that self-adaptation equal interval sampling pulse producer is set in measure and control device, 360 ° of electrical angles of each complete cycle are pressed sampling number M five equilibrium, then no matter how the frequency of measured signal changes, as long as every 360 °/M electrical angle once sampling, just can guarantee the complete cycle of sampled data reflection in the data window, and all sampled points are equally spaced, thereby realize that sample frequency can be from the self-adaptation equal interval sampling of motion tracking measured signal frequency change.Concrete technical solution has two:
Scheme one: the AC signal measuring controller of the electric system that invention provides, comprise microprocessor system, A/D converter is characterized in that also being provided with self-adaptation equal interval sampling pulse producer, and this sampling pulse generator comprises:
Signal superposition circuit is with the three-phase alternating current simulating signal V of input
a, V
b, V
cCarry out superposition;
Every straight bandpass filter, link to each other with the signal superposition circuit output terminal, be used for the flip-flop and the harmonic component of filtering superposition signal;
Shaping circuit will detect from the positive and negative zero crossing every the AC signal of straight bandpass filter, and carries out frequency multiplication and form square-wave pulse signal f
i
The phaselocking frequency multiplier that is made of phaselocked loop and 1/N frequency divider is with the f of input
iSquare-wave pulse signal N frequency multiplication, output double frequency pulse signal f
o
Counter A is to the pulse signal f of phaselocking frequency multiplier output
oCounting;
Monostable circuit, its input end links to each other with the output terminal of counter A, produces sampling pulse P1 and divides two tunnel outputs, the one road is used for counter A and resets, link to each other with the count resets end of counter A, another road is used to start A/D converter, links to each other with the startup controlling of sampling end of A/D converter.
Usually, monostable circuit adopts and can heavily trigger monostable circuit.
Scheme two: the electric power system alternating current signal measure and control device of invention can be realized the synchronous self-adapting equal interval sampling to the tested AC signal in strange land simultaneously, it comprises microprocessor system, A/D converter, it is characterized in that also being provided with self-adaptation equal interval sampling pulse producer, this sampling pulse generator comprises:
Signal superposition circuit is with the three-phase alternating current simulating signal V of input
a, V
b, V
cCarry out superposition;
Every straight bandpass filter, link to each other with the signal superposition circuit output terminal, be used for the flip-flop and the harmonic component of filtering superposition signal;
Shaping circuit will detect from the positive and negative zero crossing every the AC signal of straight bandpass filter, and carries out frequency multiplication and form square-wave pulse signal f
i
The phaselocking frequency multiplier that is made of phaselocked loop and 1/N frequency divider is with the f of input
iSquare-wave pulse signal N frequency multiplication, output double frequency pulse signal f
o
The first counter A is to the pulse signal f of phaselocking frequency multiplier output
oCounting;
Monostable circuit, its input end links to each other with the output terminal of the first counter A, produces sampling pulse P1 and imports second AND circuit;
Gps receiver provides 1PPS (pulse/sec) signal and nKHZ pulse signal (n is a positive integer) with clock synchronization;
The second counter B is to the nKHZ pulse count signal of gps receiver output;
Second monostable circuit, input 1PPS (pulse/sec) signal is exported whole second Synchronous Sampling Pulse P2;
Triple monostable circuit, its input end links to each other with the output terminal of the second counter B, output cycle data synchronous window sampling pulse P3;
Above-mentioned whole second Synchronous Sampling Pulse P2 and cycle data synchronous window sampling pulse P3 are sent to the middle fracture of microprocessor on the one hand respectively, import first AND circuit on the other hand; The output of first AND circuit divides two the tunnel, second AND circuit is imported on the one road, another road is used for the second counter B and resets, link to each other with the count resets end of the second counter B, the output of second AND circuit divides two the tunnel, and the one road is used for the first counter A and resets, link to each other with the count resets end of the first counter A, another road is used to start A/D converter, links to each other with the startup controlling of sampling end of A/D converter, and the communication port line of GPS links to each other with microprocessor.
Usually, monostable circuit, second monostable circuit and triple monostable circuit adopt and can heavily trigger monostable circuit.
Description of drawings
Below in conjunction with accompanying drawing the present invention is described in further detail.
Fig. 1 is the present invention program one a theory diagram;
Fig. 2 is the present invention program two a theory diagram;
Fig. 3 is a kind of practical circuit of self-adaptation equal interval sampling pulse producer;
Fig. 4 is the another kind of practical circuit of self-adaptation equal interval sampling pulse producer.
Embodiment
With reference to accompanying drawing 1, the electric power system alternating current signal measure and control device of invention comprises microprocessor system 1, A/D converter 2, self-adaptation equal interval sampling pulse producer 3, this sampling pulse generator comprises signal superposition circuit 4, the phaselocking frequency multiplier 9, the counter A that constitute every straight bandpass filter 5, shaping circuit 6, by phaselocked loop 7 and 1/N frequency divider 8 and can heavily trigger monostable circuit 10, the three-phase alternating current simulating signal v of input
a, v
b, v
c, form a composite analog signal v through signal superposition circuit 4
1(=k1v
a+ k2v
b-k3v
c), this signal is through after straight bandpass filter 5 filtering flip-flops and harmonic component, obtain the first-harmonic AC signal of a symmetry and be sent to shaping circuit 6, correctly detect from carrying out frequency multiplication by shaping circuit, form square-wave pulse signal f with enough steepness and width every the positive and negative zero crossing of the first-harmonic AC signal of straight bandpass filter and to it
iBe defeated by phaselocking frequency multiplier 9, phaselocking frequency multiplier is to input signal f
iCarry out the N frequency multiplication, output double frequency pulse signal f
o, that is: f
o=Nf
1Because phaselocking frequency multiplier can guarantee output signal f
oFrequency " is followed, is locked " at input signal f
iOn the frequency, and multiple linear relation with it, in other words, at one fixedly in the cycle, f
oPulse number is f always
iThe N of pulse number doubly and be maintained fixed constant, so each f
oA fixing electrical angle is all represented in the output pulse.Counter A one can preset number from involution (count value heavy duty) automatically counter, and it is according to the f of predefined count value to phaselocking frequency multiplier output
oPulse is counted, and exports a pulse when counting down to the preset count value, and this pulse is through can heavily triggering the sampling pulse p1 (negative pulse) that monostable circuit 10 generation steepness and width all meet the demands.The p1 pulse is used to start A/D converter on the one hand and begins analog to digital conversion, STRT links to each other with the A/D converter control end, be used for involution counter A on the other hand, make it restart counting, so go round and begin again, thereby form the self-adaptation equal interval sampling pulse sequence signal f that changes from the tested AC signal fundamental frequency of motion tracking
Samp
Obviously, because the signal of phaselocking frequency multiplier output " is followed, locked " tested interchange fundamental signal and concerns with its frequency multiplication that becomes to fix, therefore, need only enough big (each f of Clock Multiplier Factor N of phaselocking frequency multiplier
oThe electrical angle of pulse representative is enough little), according to the preset count value of sample frequency requirement adjustment counter A, then utilize f simultaneously
oAs the input count pulse of counter A, its counting precision just can be guaranteed.In other words, the sampling pulse sequence signal f of counter A output
SampCan in " follow, lock " tested AC signal fundamental frequency, guarantee its uniformly-spaced property, therefore utilize this signal controlling A/D converter to carry out analog to digital conversion, can guarantee the integrality of measured signal sampled data in each sampled data window and property uniformly-spaced, thereby realize frequency-tracking self-adaptation equal interval sampling measured signal.
Fig. 2 is another principle of compositionality block diagram of the present invention, the difference that constitutes with Fig. 1 is to have introduced global position system GPS, thereby can realize synchronous self-adapting equal interval sampling to the tested AC signal in strange land, it comprises microprocessor system 1, A/D converter 2, self-adaptation equal interval sampling pulse producer 3, wherein sampling pulse generator comprises signal superposition circuit 4, every straight bandpass filter 5, shaping circuit 6, phaselocking frequency multiplier 9, the first counter A that constitute by phaselocked loop 7 and 1/N frequency divider 8, can heavily trigger monostable circuit 10, gps receiver 11, the second counter B, second can heavily trigger monostable circuit 12, the 3rd can heavily trigger monostable circuit 13 and first AND circuit, 14, the second AND circuit 15.The three-phase alternating current simulating signal v of input
a, v
b, v
cThrough signal superposition circuit 4 superpositions, again through after straight bandpass filter 5 filtering flip-flops and harmonic component, being sent to shaping circuit 6, the square-wave pulse signal f of shaping circuit output
iBe defeated by phaselocking frequency multiplier 9, by the first counter A according to the f of predefined count value to phaselocking frequency multiplier output
oPulse is counted, the output of the first counter A is imported second AND circuit 15 through can heavily triggering monostable circuit 10 generation sampling pulse p1, and gps receiver 11 provides the full sized pules signal of two-way and clock synchronization: 1pps (pulse/sec) signal and 10kHz (or other nkHz) pulse signal.1pps (pulse/sec) signal forms width and steepness all satisfactory " whole second synchronously " sampling pulse p2 (negative pulse) through second after can heavily triggering monostable circuit 12; The 10kHz pulse signal is imported the 3rd and can heavily be triggered monostable circuit 13 through the second heavily loaded automatically counter B frequency division counter of count value, forms width and all satisfactory " the cycle data window is synchronous " the sampling pulse p3 of steepness (negative pulse).Whole second Synchronous Sampling Pulse P2 and cycle data window Synchronous Sampling Pulse P3 are sent to the middle fracture line INT1 and the INT2 of microprocessor on the one hand respectively, to ask its response to be interrupted and record " whole second synchronously " and " the cycle data window is synchronous " are sampled the zero hour respectively, start two sampling pulse signal sources of sampling as the control A/D converter on the other hand and import first AND circuit 14, the output of first AND circuit 14 divides two the tunnel, second AND circuit 15 is imported on the one road, another kind is used for the involution second counter B, the output of second AND circuit 15, be used for the involution first counter A on the one hand, be used to start A/D converter on the other hand, link to each other the communication port line TD of GPS with the control end STRT of A/D converter, RD end respectively with the R of microprocessor
xD, T
xThe D end links to each other, and transmits real-time clock information and gives microprocessor system.
During work, by the whole second synchronized sampling of whole second Synchronous Sampling Pulse p2 assurance the whole network; Cycle data window Synchronous Sampling Pulse p3 guarantees the cycle data window synchronized sampling of the whole network; Sampling pulse p1 guarantees the equal interval sampling in the cycle data window.These three sampling pulse signals all have only one at any one time and play a role, and its priority is: p2 is higher than p3 and is higher than p1.This function realizes with door 14 and 15 by two: realize output behind the logical with door 14 couples of p2, p3, be sent on the one hand with door 15 further with p1 mutually " with " with generation sampling pulse sequence f
Samp, be sent to the count resets end RST of the second counter B on the other hand, to realize heavy cartridges to its preset count value; Output f with door 15
SampIn fact be exactly the output behind p1, p2, the p3 logical, control on the one hand A/D converter and finish analog to digital conversion, be sent to the count resets end RST of the first counter A on the other hand, to realize heavy cartridges to its preset count value to measured signal.Obviously, be subjected to control, so its preset count value can be reloaded by any involution in p2, p3, the p1 pulse and begun counting with the output negative pulse of door 15 owing to produce the count resets end of the first counter A of p1; Similarly, be subjected to control, so its preset count value can be reloaded by any involution in p2, the p3 pulse and begun counting with the output negative pulse of door 14 owing to produce the count resets end of the second counter B of p3.Therefore, the present invention can produce not only be synchronized with the GPS standard time clock, simultaneously but also from motion tracking and be locked in frequency-tracking self-adaptation equal interval sampling pulse train f on the tested AC signal fundamental frequency
Samp
No matter the present invention adopts scheme 1 shown in Figure 1, or scheme 2 shown in Figure 2, the sampling pulse sequence f that utilizes self-adaptation equal interval sampling pulse producer to export
Samp, the control A/D converter is finished the frequency-tracking self-adaptation equal interval sampling to measured signal.A/D converter is whenever finished the one-off pattern number conversion, just produces " sampling a finishes " signal ENDS, and this signal is sent into a certain middle fracture line (being INTO among the figure) of microprocessor and caused respective interrupt, and sampled data is read in request; Microprocessor in time respond this interruption and read away that sampled data in the A/D converter is handled, deposit etc.The ENDS signal of A/D converter is involution automatically after the microprocessor reading of data, for sampling end interrupt microprocessor reading of data is next time got ready.So go round and begin again, realized the continuous frequency-tracking self-adaptation equal interval sampling of measured signal.
Fig. 3 is a kind of practical circuit about the self-adaptation equal interval sampling pulse producer in the present invention program two the electric power system alternating current signal measure and control device, signal superposition circuit is made of integrated operational amplifier chip U7 (available LM741) and resistance R 2, R5, R8, R9 and R10 in this example, finishes tested AC signal v
a, v
b, v
cThe signal superposition and export v
fTo carrying out every the direct sum bandpass filtering every straight bandpass filter.Constitute by R12, C1 and C2, R13 every straight bandpass filter.Wherein shaping circuit is made of zero-crossing comparator, high speed photo coupling, monostalbe trigger and OR circuit.Zero-crossing comparator is made of integrated operational amplifier chip U8 (available LM741) and zero potentiometer RV1, be responsible for to convert to every the symmetrical fundamental signal of straight bandpass filter output dutycycle and be 50% square-wave signal, high speed photo coupling chip U10 is the 6N137 of band application schmitt trigger function, its effect is that the square wave that U8 exports is carried out mould-number Signal Spacing and shaping, monostalbe trigger U11A and U11B are by a slice 54HC123 (or 74HC123) and auxiliary outer meeting resistance thereof, capacity cell R3, C7 and R4, C22 (determining the output pulse width of monostalbe trigger) forms, its effect is to extract the rising edge of the square-wave signal of opto-coupler chip U10 output (by U11A and R3, C7 finishes) and negative edge (by U11B and R4, C22 finishes) and form two positive pulses that width and steepness all meet the demands, these two pulses are just being represented the measured signal fundametal compoment respectively, negative two zero crossings, or door U9 synthesizes two positive pulse signals of U11A and U11B output, thereby obtains the square-wave pulse signal f that becomes frequency multiplication to concern with measured signal fundametal compoment frequency
i, and further be sent to phaselocking frequency multiplier and carry out the phase locking frequency multiplying processing.Phaselocking frequency multiplier is made of phaselocked loop and 1/N frequency divider, and wherein phaselocked loop is by integrated chip U13 (available HC4046) and by resistance R 6, R7, and the low-pass filter that capacitor C 24 constitutes and the resistance R 1 of definite phaselocked loop centre frequency, capacitor C 23 are formed; The 1/N frequency divider can preset several increasing/down counter U1, U2, U3 (available 54HC191 or 74HC191) and 1/2 monostalbe trigger chip U18A formations such as (available 1/2 54HC123 or 74HC123) by three 4, U1, U2, U3 are by the cascade of synchronous down counter mode, their CLK end is the count pulse input end, meets the phase locking frequency multiplying signal f of pin 4 outputs of phase-locked loop chip U13 after the parallel connection
oThe LD end is the count resets end, the negative pulse output terminal of back order steady state trigger chip U18A in parallel, the U/D end is for increasing/subtract the counting selecting side, all meet power supply VCC to select to subtract the counting working method, the counting Enable Pin CE ground connection of low level chip U1 is in the counting attitude to guarantee it always, and its carry output terminal RC links to each other with the CE end of U2, guarantees that U2 could count when U1 has carry; Similarly, the RC of U2 end links to each other with the CE end of U3, guarantees that U3 could count when U2 has carry; The signal that the RC end of high-order chip U3 is exported is the 1/N frequency divider to input signal f
oFractional-N frequency output, the negative pulse input end A that is sent to monostalbe trigger U18A makes pulsewidth and handles, thereby constitute 12 down counters, the effect of monostalbe trigger U18A is the pulse width of giving the count resets end of 1/N frequency counter for Control and Feedback, makes it neither wide and causes U1, U2, U3 " to leak meter " or " eating up " inputs to the count pulse f of its CLK end
o, again not can because of narrow cause can not reliable reset U1, U2, U3 makes their preset count values of reloading.The positive pulse output terminal of monostalbe trigger U18A is the pulse signal of pin one 3 outputs, feeds back to the pin 3 of phase-locked loop chip HC4046, and phaselocked loop is exactly to utilize this signal and another signal (f by the reflection measured signal fundamental frequency of pin one 4 inputs
i) carry out the phase bit comparison and realize phase-locked.This example can heavily trigger monostable circuit, and second can heavily trigger monostable circuit, and the 3rd can heavily trigger monostable circuit adopts 54HC123 respectively, and the first counter A and the second counter B constitute with 54HC191 respectively, fracture in P2, the P3 termination microprocessor among the figure, GPST
xD and GPSR
xD end respectively with the R of microprocessor
xD, T
xThe D end links to each other f
SampEnd links to each other with the control end of A/D converter.
Fig. 4 is the practical circuit about the present invention program one, the signal superposition circuit in this example, every straight bandpass filter, shaping circuit, phaselocking frequency multiplier, counter, can heavily to trigger monostable circuit identical with Fig. 3 example.
The present invention constitutes simply, cost is low, because the fundamental frequency of measured signal can be followed the tracks of and lock to the self-adaptation equal interval sampling pulse producer that is provided with, so can guarantee under signal fundamental frequency situation of change, to have high measuring accuracy, subordinate list 1 is that Sampling techniques of the present invention and routine sampling technology compare the Simulation results that measuring accuracy influences, the result can find out significantly from table, employing the technology of the present invention can improve the measuring accuracy to input exchange signal greatly, especially aspect phase angle measurement, when the measured signal frequency change is very fast, the result who adopts the routine sampling technology to be obtained has lost meaning, even and employing the present invention has still guaranteed higher sampling precision under the 5th the period frequency variation situation greatly of input model signal.
This shows, adopt measuring and controlling of the present invention, can improve the measuring accuracy of electric system real-time parameter (particularly phase angle) greatly, and introduce the whole network synchronous real-time measurement that gps receiver can also be realized electric system.
Claims (8)
1. the AC signal measuring controller of electric system comprises microprocessor system [1], and A/D converter [2] is characterized in that also being provided with self-adaptation equal interval sampling pulse producer [3], and this sampling pulse generator comprises:
Signal superposition circuit [4] is with the three-phase alternating current simulating signal [V of input
a, V
b, V
c] carry out superposition;
Every straight bandpass filter [5], link to each other with signal superposition circuit [4] output terminal, be used for the flip-flop and the harmonic component of filtering superposition signal;
Shaping circuit [6] will detect from the positive and negative zero crossing every the AC signal of straight bandpass filter [5], and carries out frequency multiplication and form square-wave pulse signal [f
i];
By the phaselocking frequency multiplier [9] of phaselocked loop [7] and 1/N frequency divider [8] formation, with the square wave arteries and veins [f of input
i] towards signal N frequency multiplication, output double frequency pulse signal [f
o];
Counter [A] is to the pulse signal [f of phaselocking frequency multiplier [9] output
o] counting;
Monostable circuit [10], its input end links to each other with the output terminal of counter [A], produce sampling pulse [P1] and divide two tunnel outputs, the one road is used for counter [A] and resets, link to each other with the count resets end of counter [A], another road is used to start A/D converter, links to each other with the startup controlling of sampling end of A/D converter [2].
2. by the AC signal measuring controller of the described electric system of claim 1, it is characterized in that said monostable circuit [10] is heavily to trigger monostable circuit.
3. press the AC signal measuring controller of the described electric system of claim 1, it is characterized in that said shaping circuit [6] is made of zero-crossing comparator, high speed photo coupling, monostalbe trigger and OR circuit, wherein zero-crossing comparator amplifies chip LM741 and zero potentiometer [RV1] formation by integrated computing, high speed photo coupling chip [U10] is the 6N137 of band application schmitt trigger function, and monostalbe trigger [U11A and U11B] is made up of a slice 54HC123 and corresponding Resistor-Capacitor Unit.
4. by the AC signal measuring controller of the described electric system of claim 1, it is characterized in that 1/N frequency divider [8] can preset several increasing/down counter 54HC191 by 34 and 1/2 monostalbe trigger chip 54HC123 constitutes.
5. the AC signal measuring controller of electric system comprises microprocessor system [1], and A/D converter [2] is characterized in that also being provided with self-adaptation equal interval sampling pulse producer [3], and this sampling pulse generator comprises:
Signal superposition circuit [4] is with the three-phase alternating current simulating signal [V of input
a, V
b, V
c] carry out superposition;
Every straight bandpass filter [5], link to each other with signal superposition circuit [4] output terminal, be used for the flip-flop and the harmonic component of filtering superposition signal;
Shaping circuit [6] will detect from the positive and negative zero crossing every the AC signal of straight bandpass filter [5], and carries out frequency multiplication and form square-wave pulse signal [f
i];
By the phaselocking frequency multiplier [9] of phaselocked loop [7] and 1/N frequency divider [8] formation, with the square wave arteries and veins [f of input
i] towards signal N frequency multiplication, output double frequency pulse signal [f
o];
First counter [A] is to the pulse signal [f of phaselocking frequency multiplier [9] output
o] counting;
Monostable circuit [10], its input end links to each other with the output terminal of first counter [A], produces sampling pulse [P1] input second AND circuit [15];
Gps receiver [11] provides 1PPS signal and nKHZ pulse signal with clock synchronization, and n is a positive integer;
Second counter [B] is to the nKHZ pulse count signal of gps receiver [11] output;
Second monostable circuit [12], input 1PPS signal is exported whole second Synchronous Sampling Pulse [P2];
Triple monostable circuit [13], its input end links to each other with the output terminal of second counter [B], output cycle data window Synchronous Sampling Pulse [P3];
Above-mentioned whole second Synchronous Sampling Pulse [P2] and cycle data window Synchronous Sampling Pulse [P3] one side are sent to the middle fracture of microprocessor [1] respectively, import first AND circuit [14] on the other hand; The output of first AND circuit [14] divides two the tunnel, second AND circuit [15] is imported on the one road, another road is used for second counter [B] and resets, link to each other with the count resets end of second counter [B], the output of second AND circuit [15] divides two the tunnel, and the one road is used for first counter [A] and resets, link to each other with the count resets end of first counter [A], another road is used to start A/D converter, links to each other with the startup controlling of sampling end of A/D converter [2], and the communication port line of GPS links to each other with microprocessor.
6. by the AC signal measuring controller of the described electric system of claim 5, it is characterized in that said monostable circuit [10], second monostable circuit [12] and triple monostable circuit [13] are heavily to trigger monostable circuit.
7. press the AC signal measuring controller of the described electric system of claim 5, it is characterized in that said shaping circuit [6] is made of zero-crossing comparator, high speed photo coupling, monostalbe trigger and OR circuit, wherein zero-crossing comparator amplifies chip LM741 and zero potentiometer [RV1] formation by integrated computing, high speed photo coupling chip [U10] is the 6N137 of band application schmitt trigger function, and monostalbe trigger [U11A and U11B] is made up of a slice 54HC123 and corresponding Resistor-Capacitor Unit.
8. by the AC signal measuring controller of the described electric system of claim 5, it is characterized in that 1/N frequency divider [8] can preset several increasing/down counter 54HC191 by 34 and 1/2 monostalbe trigger chip 54HC123 constitutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01119393XA CN1159589C (en) | 2001-06-04 | 2001-06-04 | AC signal measuring controller for power system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB01119393XA CN1159589C (en) | 2001-06-04 | 2001-06-04 | AC signal measuring controller for power system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1389736A CN1389736A (en) | 2003-01-08 |
| CN1159589C true CN1159589C (en) | 2004-07-28 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026781B (en) * | 2007-01-23 | 2010-12-08 | 宁波大学 | Quasi full-synchronous high-precision rapid frequency measuring device and method |
| DE102010041495A1 (en) * | 2010-09-28 | 2012-03-29 | Siemens Aktiengesellschaft | Protective switching device with digital data processing device |
| CN102590606A (en) * | 2012-02-28 | 2012-07-18 | 保定浪拜迪电气股份有限公司 | Uniformly-spaced sampling circuit and sampling method for different frequency signals |
| CN103178845A (en) * | 2013-03-04 | 2013-06-26 | 安徽省电力公司宣城供电公司 | Phase-locked loop and method for measuring voltage phase and frequency |
| CN104155596B (en) * | 2014-08-12 | 2017-01-18 | 北京航空航天大学 | Artificial circuit fault diagnosis system based on random forest |
| CN108303582A (en) * | 2018-03-12 | 2018-07-20 | 吉林特纳普节能技术有限公司 | A kind of ultra-low-power high-precision alternating voltage zero-crossing point detection circuit and method |
| CN109120267A (en) * | 2018-10-25 | 2019-01-01 | 南方电网科学研究院有限责任公司 | Power signal synchronous sampling system and method |
| CN109358228B (en) * | 2018-11-09 | 2020-12-15 | 哈工大（张家口）工业技术研究院 | Power grid voltage positive and negative sequence component real-time estimation method based on double enhanced phase-locked loops |
| CN110542792A (en) * | 2019-09-16 | 2019-12-06 | 南京海兴电网技术有限公司 | High-precision frequency measuring circuit |
| CN110579667A (en) * | 2019-10-22 | 2019-12-17 | 李玉玲 | Power system analysis method |
| CN113098447A (en) * | 2021-03-25 | 2021-07-09 | 厦门市必易微电子技术有限公司 | Duty ratio sampling circuit, duty ratio sampling method and LED drive circuit |
| CN115902681A (en) * | 2023-02-22 | 2023-04-04 | 江西省中碳数字能源技术有限公司 | Three-phase variable frequency power supply conversion efficiency test system |
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