CN104931779A - Single-channel realized continuous frequency measure method - Google Patents

Single-channel realized continuous frequency measure method Download PDF

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Publication number
CN104931779A
CN104931779A CN201510233650.5A CN201510233650A CN104931779A CN 104931779 A CN104931779 A CN 104931779A CN 201510233650 A CN201510233650 A CN 201510233650A CN 104931779 A CN104931779 A CN 104931779A
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data
tdc
time
frequency
gate
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刘永
王励
杨江涛
刘纪龙
贺增昊
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CETC 41 Institute
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CETC 41 Institute
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Abstract

The invention relates to the test technical field, and specifically relates to a single-channel realized continuous frequency measure method; the measure method can realize continuous frequency measurement, thus reducing almost half component application amount while having a same measure resolution; the method reduces PCB design complexity and instrument power consumption, so circuit debug and instrument aftersales fault maintenance are convenient, thus reducing production cost, and improving work performance.

Description

A kind of single channel realizes cline frequency measuring method
Technical field
The present invention relates to technical field of measurement and test, be specifically related to a kind of single channel and realize cline frequency measuring method.
Background technology
Frequency measurement is a fundamental measurement technology in electronic technology, is widely used in various fields such as communication, navigation, space science and measurement technologies.The high-acruracy survey of frequency impels the progress of science and technology, and the measuring accuracy of the progress of science and technology to frequency is had higher requirement.The raising of frequency measurement level has the facilitation of positive important to whole scientific technological advance.Cline frequency measuring technique can promote the resolution of frequency measurement further under the prerequisite that hardware device is certain, is measured at present, there is the shortcoming that circuit amount of redundancy is larger by two-way difference synchronous counting circuit realiration.
Fig. 1 is frequency and time interval measuring circuit theory diagram.As shown in the figure, this circuit can be divided into " passage conditioning and triggering ", " secondary synchronization " and " count and measure with short time interval " three main modular according to the front and back flow process measured.Whole measuring process is carried out under the unified coordination and control of FPGA.
Fig. 2 is the principle schematic that cline frequency is measured.As shown in the figure, cline frequency measuring process can be carried out substantially in three steps:
(1) select to fill gate by the signal strobe of FPGA or outside access as counting.For ensureing the Measurement Resolution of more than 12 bps, this original gate duration generally should be made to be greater than 1 second, selecting 1 second here for convenience of description;
(2) original gate is through " secondary synchronization " circuit each synchronous twice, and first time obtains " counting gate " for counting measured signal number, and second time obtains " filling gate " for counting filler pulse number;
(3) in " counting gate ", " filling gate " high level lasting time to measured signal and filler pulse counting, and measure short time interval △ t1, △ t2.
At the end of " second synchronization ", data send ARM platform to via FPGA.System software is according to formula:
T i = t N i = M i * T f + ( Δ t i - Δ t i + 1 ) N i - - - ( 1 )
f i = N i M i * T f + ( Δ t i - Δ t i + 1 ) - - - ( 2 )
Calculate continuous coverage cycle and frequency.Wherein T frepresent the cycle of filler pulse, N i, M irepresent the count value treating measured frequency and filler pulse when measuring for i-th time respectively, Δ t iand Δ t i+1it is the front and back short time interval measured for i-th time.
System software receives the data that FPGA sends, after each calculated rate value, judge whether measured signal frequency changes, if do not change, accumulation computing can be carried out to increase the resolution of frequency measurement to the data surveyed, otherwise abandon measurement data in the past, only show current frequency values, and perform continuous accumulation calculating process upper once continuation.For convenience of description, suppose to treat that measured frequency does not all change in the 1st time to i-th time continuous coverage process, then measured signal frequency can be accurate to after the accumulation of i time:
f = N 1 + N 2 + L + N i M 1 * T f + ( Δ t 1 - Δ t 2 ) + M 2 * T f + ( Δ t 2 - Δ t 3 ) + L + M i * T f + ( Δ t i - Δ t i + 1 ) - - - ( 3 )
Because measured signal frequency does not change, therefore formula (3) can abbreviation be:
f = N 1 + N 2 + L + N i ( M 1 + M 2 + L + M i ) * T f + ( Δ t 1 - Δ t i + 1 ) - - - ( 4 )
Wherein Δ t 1, Δ t 2, Δ t idraw Deng by the TDC_GPX chip measurement based on lag line principle, the temporal resolution adopting TDC chip to realize now can reach 100ps.For the gate of 1 second, the system quantizing error that single cline frequency is measured is:
± 1 count = ± t ss T = ± 100 ps 1 s = ± 10 - 10 - - - ( 5 )
Wherein t ssfor the time interval measurement resolution that TDC_GPX can realize.If systems axiol-ogy does not change to measured signal frequency, accumulate and can realize stochastic error reduction N for N time doubly.If N=10, then stochastic error is i.e. frequency measurement resolution is 11 bps, and in like manner, if N=100, system frequency Measurement Resolution can reach 12 bps.
Fig. 3 is the realizing circuit of cline frequency measure portion.As shown in the figure, the relevant synchronous and segment count circuit of this patent is only extracted for convenience of description herein.In figure, N6, N7 are the counters treating measured frequency, counting under " counting gate " controls.And N10, N11 are the counters of filler pulse, Selective filling pulsed frequency is 500MHz here, and counting process is carried out under " filling gate " controls.
Fig. 4 is the schematic diagram that two-way realizes continuous coverage.Wherein " counting gate " and " filling gate " are all that difference output is so that N6, N7 and N10, the N11 produced in two path control signal difference control chart 3 realizes counting.In figure, in each gate, dash area is the time period of counter real work.
The Gate of " counting gate " and " filling gate " and alternately control respective rolling counters forward, moment (time point of arrow signal downward in Fig. 4) FPGA terminated in " shade " region reads the count value N of counter and internal extended counter iwith M ito in Reg, postpone a period of time T d, to wait for that TDC_GPX completes short time interval Δ t iwith Δ t i+1measurement after send look-at-me INT to ARM platform, system software now read calculated rate need data N i, M i, Δ t iwith Δ t i+1(in figure upwards arrow signal time point).Then accept or reject currency according to frequency accumulation law mentioned above, hocket successively, thus realize continuous gapless frequency measurement.
" counting gate " and " filling gate " is all difference output, two-way respectively control counter modular circuit realizes continuous gapless frequency measurement, circuit structure is symmetrical, is namely actually and employs the almost identical circuit of two covers, is not continuous gapless frequency measurement truly.Further, use that device is more causes that cost is comparatively large, circuit working efficiency is lower.
Summary of the invention
For the defect that prior art exists, the object of the invention is to propose a kind of single channel and realize cline frequency measuring method, reduce synchronous counting and the level-conversion circuit thereof of half while realizing cline frequency measurement by self-control scheme, thus reach simplification circuit design, minimizing power supply power consumption, reduction FPGA wiring difficulty and PCB cost.
For reaching above-mentioned purpose, the invention provides a kind of single channel and realizing cline frequency measuring method, comprising:
According to described count synchronization gate, pad count gate, measured signal and the hyposynchronous relation of filler pulse two, FPGA is coordinated to control, at the end of described sync gate high level, store in the internal register of the first time count value Data_N1 of described measured signal and the first time count value Data_M1 of described filler pulse to described FPGA;
Measure plate after postponing a period of time and send look-at-me TNT to CPU, so that system software reads time-to-digit converter TDC1 and the TDC2 measured value of this measurement, and go out signal frequency value according to formulae discovery and show;
When low level starts, sync gate continues to control counting circuit synchronous counting; The second time count value Data_N2 of described measured signal and the second time count value Data_M2 of described filler pulse is stored at the end of low level; Look-at-me is sent after postponing a period of time; System software reads count value and TDC value;
Judge in the measuring process of twice, front and back, whether measured signal frequency changes; If there is change, then give up secondary data, and only previous measurement result is worked as in display; Otherwise perform accumulation computing, upgrade measurement result.
Wherein, described Data_N2 is the aggregate-value on Data_N1 basis.
Further, describedly signal frequency value is gone out according to formulae discovery, specifically according to following formulae discovery:
f 1 = Data _ N 1 Data _ M 1 × T f + ( TDC 1 - TDC 2 ) ; Wherein T frepresent the cycle of filler pulse.
Further, when measured signal frequency does not change in the measuring process of twice, front and back, perform described accumulative computing by following formula:
f = Data _ N 1 + Data _ N 2 ( Data _ M 1 + Data _ M 2 ) × T f + ( TDC 1 - TDC 3 ) ; Wherein T frepresent the cycle of filler pulse;
The present invention can reach following beneficial effect:
The measuring method proposed by the present invention is realized cline frequency and measures, and can reduce the components and parts use amount of nearly half under the prerequisite reaching same Measurement Resolution; The use of the method reduces complexity and the instrument power source power consumption of PCB design, can facilitate circuit debugging and instrument Breakdown Maintenance after sale, thus the target realizing reducing production cost, improve serviceability.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is frequency and time interval measuring circuit theory diagram;
Fig. 2 is the principle schematic that cline frequency is measured;
Fig. 3 is the realizing circuit of cline frequency measure portion;
Fig. 4 is the schematic diagram that two-way realizes continuous coverage;
Fig. 5 is the process flow diagram that single channel of the present invention realizes cline frequency measuring method;
Fig. 6 is the principle schematic that cline frequency of the present invention is measured;
Fig. 7 is the schematic flow sheet that data accumulation computing judges.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 5 is the process flow diagram that single channel of the present invention realizes cline frequency measuring method, as shown in the figure, comprising:
Step 501, according to described count synchronization gate, pad count gate, measured signal and the hyposynchronous relation of filler pulse two, FPGA is coordinated to control, at the end of described sync gate high level, store in the internal register of the first time count value Data_N1 of described measured signal and the first time count value Data_M1 of described filler pulse to described FPGA;
Step 502, measures plate and sends look-at-me TNT to CPU, so that system software reads time-to-digit converter TDC1 and the TDC2 measured value of this measurement, and go out signal frequency value according to formulae discovery and show after postponing a period of time;
Fig. 6 is the principle schematic that cline frequency of the present invention is measured, as shown in the figure, according to counting gate with fill gate and measured signal and the hyposynchronous relation of filler pulse two, FPGA is coordinated to control, store in data-measured signal count value Data_N1 and filler pulse count value Data_M1 to FPGA internal register at the end of sync gate high level, storage time point as in Fig. 5 ↓ place illustrate, measure plate after postponing a period of time and send look-at-me INT to CPU, so that system software reads TDC1 and the TDC2 measured value of this measurement, and go out signal frequency value according to formulae discovery and show:
f 1 = Data _ N 1 Data _ M 1 × T f + ( TDC 1 - TDC 2 ) ; Wherein T frepresent the cycle of filler pulse.
Step 503, when low level starts, sync gate continues to control counting circuit synchronous counting; The second time count value Data_N2 of described measured signal and the second time count value Data_M2 of described filler pulse is stored at the end of low level; Look-at-me INT is sent after postponing a period of time; System software reads count value and TDC value;
As shown in Figure 6, at the time point of ↑ signal, system software reads count value and TDC value.Wherein, Data_N2 is the accumulated value on Data_N1 basis, uses after needing system software process;
Step 504, judges in the measuring process of twice, front and back, whether measured signal frequency changes; If there is change, then give up secondary data, and only previous measurement result is worked as in display; Otherwise perform accumulation computing, upgrade measurement result.
Fig. 7 is the schematic flow sheet that data accumulation computing judges, as shown in the figure, after initialization is opened and measured, whether determination frequency changes, and concrete determination methods is, judges that whether TDC rreturn value is equal with last time, compares in conjunction with front and back twice frequency value.As changed, then giving up secondary data, being sent by software aobvious when previous measurement result; Otherwise carry out continuous coverage and add up computing:
f = Data _ N 1 + Data _ N 2 ( Data _ M 1 + Data _ M 2 ) × T f + ( TDC 1 - TDC 3 ) ; Wherein T frepresent the cycle of filler pulse.
Then this result is upgraded, and software send aobvious.
The present invention can reach following beneficial effect:
The measuring method proposed by the present invention is realized cline frequency and measures, and can reduce the components and parts use amount of nearly half under the prerequisite reaching same Measurement Resolution; The use of the method reduces complexity and the instrument power source power consumption of PCB design, can facilitate circuit debugging and instrument Breakdown Maintenance after sale, thus the target realizing reducing production cost, improve serviceability.
Those skilled in the art can also recognize the various illustrative components, blocks (illustrativelogical block) that the embodiment of the present invention is listed, unit, and step can pass through electronic hardware, computer software, or both combinations realize.For the replaceability (interchangeability) of clear displaying hardware and software, above-mentioned various illustrative components (illustrativecomponents), unit and step have universally described their function.Such function is the designing requirement realizing depending on specific application and whole system by hardware or software.Those skilled in the art for often kind of specifically application, can use the function described in the realization of various method, but this realization can should not be understood to the scope exceeding embodiment of the present invention protection.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. single channel realizes a cline frequency measuring method, it is characterized in that, comprising:
According to described count synchronization gate, pad count gate, measured signal and the hyposynchronous relation of filler pulse two, FPGA is coordinated to control, at the end of described sync gate high level, store in the internal register of the first time count value Data_N1 of described measured signal and the first time count value Data_M1 of described filler pulse to described FPGA;
Measure plate after postponing a period of time and send look-at-me TNT to CPU, so that system software reads time-to-digit converter TDC1 and the TDC2 measured value of this measurement, and go out signal frequency value according to formulae discovery and show;
When low level starts, sync gate continues to control counting circuit synchronous counting; The second time count value Data_N2 of described measured signal and the second time count value Data_M2 of described filler pulse is stored at the end of low level; Look-at-me is sent after postponing a period of time; System software reads count value and TDC value;
Judge in the measuring process of twice, front and back, whether measured signal frequency changes; If there is change, then give up secondary data, and only previous measurement result is worked as in display; Otherwise perform accumulation computing, upgrade measurement result.
2. method according to claim 1, is characterized in that, described Data_N2 is the aggregate-value on Data_N1 basis.
3. method according to claim 1, is characterized in that, describedly goes out signal frequency value according to formulae discovery, specifically according to following formulae discovery:
f 1 = Date _ N 1 Data _ M 1 × T f + ( TDC 1 - TDC 2 ) ; Wherein T frepresent the cycle of filler pulse.
4. method according to claim 1, is characterized in that, when measured signal frequency does not change in the measuring process of twice, front and back, performs described accumulative computing by following formula:
f = Data _ N 1 + Data _ N 2 ( Data _ M 1 + Data _ M 2 ) × T f + ( TDC 1 - TDC 3 ) ; Wherein T frepresent the cycle of filler pulse.
CN201510233650.5A 2015-05-08 2015-05-08 Single-channel realized continuous frequency measure method Pending CN104931779A (en)

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