CN206002858U - A kind of attribute High-precision time interval measurement device based on FPGA - Google Patents
A kind of attribute High-precision time interval measurement device based on FPGA Download PDFInfo
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Abstract
The utility model discloses a kind of attribute High-precision time interval measurement device based on FPGA, it is related to precise time-time-interval e measurement technology.This utility model is to realize attribute time interval measurement on fpga chip, i.e. on fpga chip, carry out the chronometer time measuring system that programming realization can measure two event time intervals initial, that stopping event occurs the moment by using Verilog HDL hardware description language, including PLL reference clock（100）, measured signal produce circuit（200）, Precision delay circuit（300）, enumerator group（400）, data storage（500）Data exports（600）.This utility model is that for other time interval measurement devices based on FPGA realization, this invention is significantly simpler to implement, takies resource less based on attribute time interval measurement.The field such as measurement of short time interval in seismic instrument can be applied.
Description
Technical field
This utility model is related to precise time-time-interval e measurement technology, more particularly, to a kind of attribute high accuracy based on FPGA
Time interval measurement device；Specifically, this utility model is to realize attribute time interval measurement on fpga chip, that is, exist
On fpga chip, carry out programming realization by using Verilog HDL hardware description language and can measure initial, stopping event generation
The chronometer time measurement apparatus at the two event time intervals in moment；The neck such as measurement of short time interval in seismic instrument can be applied
Domain.
Background technology
High-precision time-interval measurement technique plays very important effect in Observation Technology of Earthquakes, and its time interval is surveyed
The precision of amount directly affects the correctness of observed result, so high-precision time-interval measurement technique is always object of study.
Become the study hotspot of time interval measurement system realization in recent years based on FPGA.Using fpga chip, Ke Yi great
Big reduction designs risk and system cost, and high integration design can improve reliability and development efficiency, and easy realization is led to more
The measurement in road.
The existing time interval measurement method overwhelming majority is all based on longer delay chain and counts to realize, but
Be difficult to inside fpga chip to construct have outstanding postpone concordance and can provide high latency resolution long delay unit it is desirable to
It is extremely difficult that all delay cells in longer delay chain have the good concordance that postpones.
Based on the time interval measurement principle of attribute be using reference frequency signal as enumerator reference clock, to be measured
As the enable signal of rolling counters forward, the cycle that the count value of enumerator is multiplied by reference clock signal is time interval signal
The time value of time interval signal to be measured, the time interval resolution obtaining is relatively low, but this counting implementation method is relatively simple.
Close temporal system is realized based on FPGA, the advantages of its low cost, construction cycle are short, flexible design, compatibility are strong,
It is necessary for therefore realizing chronometer time measuring system in this model machine based on FPGA.
Utility model content
The purpose of this utility model is to realize the deficiency of time interval measurement for existing attribute, provides one kind to be based on
The attribute High-precision time interval measurement device of FPGA, to improve time interval measurement precision, to reduce measurement error.
The purpose of this utility model is realized in：
On fpga chip, it is capable of based on FPGA's come programming realization by Verilog HDL hardware description language
Attribute High-precision time interval measurement device.
Specifically, the system includes PLL reference clock, measured signal produces circuit, Precision delay circuit, enumerator
Group, the output of data storage data；
Its annexation is：
External input signal has Rst_n：Reset signal, Tr：Outside input clock source, Start：Commencing signal, Stop：Stop
Stop signal；
By outside input：Rst_n（Reset signal）、Tr（Outside input clock source）Input as PLL reference clock；
By outside input：Start（Commencing signal）、Stop（Stop signal）Produce the input of circuit as measured signal；
Output C0, C1, C2, C3 of PLL reference clock, will be connected to the defeated of the 1LCELL chain of Precision delay circuit respectively
Enter, the input of 2LCELL chain, the input of 3LCELL chain, the input of 4LCELL chain；
The output gate of measured signal generation circuit is signally attached to all rolling counters forward Enable Pins of enumerator group, point
Not Wei cnt01 enumerator ..., cnt12 enumerator, cnt13 enumerator ..., cnt24 enumerator, cnt25 count
Device ..., cnt36 enumerator, cnt37 enumerator ... the counting Enable Pin of cnt48 enumerator；
The output of the 1LCELL chain of Precision delay circuit（Totally 12）, the output of 2LCELL chain（Totally 12）,
The output of 3LCELL chain（Totally 12）, the output of 4LCELL chain（Totally 12）, respectively as the cnt01 counting of enumerator group
Device ..., cnt12 enumerator, cnt13 enumerator ..., cnt24 enumerator, cnt25 enumerator ..., cnt36 count
Device, cnt37 enumerator ... the input of the counting reference clock of cnt48 enumerator；
The output of enumerator group（Totally 48）It is connected to the input of data storage；
The output of data storage is connected to the input of data output.
This utility model has following advantages and good effect：
1. circuit of the present utility model is to be produced by fpga chip, is programmed real by Verilog HDL hardware description language
Existing；
2. this utility model institute is to have 11 LCELL devices to constitute using 4 delay chains, and delay chain is shorter, time delay
Relatively accurate, realize simple；
3. the reference clock signal that this utility model is used 48 with frequently, adjacent phase difference is equal is as 48 enumerators
Count reference clock signal, to time interval measurement to be measured, be effectively improved Measurement Resolution, and two neighboring using 4
Phase contrast be 90 ° of reference clock signal as reference clock signal, to correct the delay of LCELL chain, to greatly reduce measurement
Error.
4. a width of 10bit of rolling counters forward carry-out bit that this utility model uses, can be according to time interval measurement system
Use occasion different, change counter widths, increase its measurement range.
5. this utility model is based on attribute time interval measurement, the time interval realized based on FPGA compared to other
For measuring system, this invention is significantly simpler to implement, takies resource less.
The field such as measurement of short time interval in seismic instrument can be applied.
Brief description
Fig. 1 is the structure chart of this device；
Fig. 2 is the structure chart that measured signal produces circuit；
Fig. 3 is the structure chart of Precision delay circuit；
Fig. 4 is the structure chart of enumerator group；
Fig. 5 is commencing signal and the stop signal two event time interval sequential schematic diagram of the system；
Fig. 6 be the system Precision delay circuit in 4 LCELL chains postpone schematic diagrams；
Fig. 7 is 48 clock signal initial phase schematic diagrams of output of the Precision delay circuit of the system.
In figure：
100 PLL reference clocks；
200 measured signals produce circuit,
201—D1Trigger, 202 D2Trigger,
203 F not gates, 204 ＆ and door；
300 Precision delay circuits,
310 1LCELL chains,
311 LCELL01 devices, 312 LCELL02 devices ... ..., 321 LCELL11 devices,
330 2LCELL chains,
331 LCELL12 devices, 332 LCELL13 devices ... ..., 341 LCELL22 devices,
350 3LCELL chains,
351 LCELL23 devices, 352 LCELL24 devices ... ..., 361 LCELL33 devices,
370 4LCELL chains,
371 LCELL34 devices, 372 LCELL35 devices ... ..., 381 LCELL44 devices；
400 enumerator groups,
401 cnt01 enumerators ... ..., 412 cnt12 enumerators,
413 cnt13 enumerators ... ..., 424 cnt24 enumerators,
425 cnt25 enumerators ... ..., 436 cnt36 enumerators,
437 cnt37 enumerators ... ..., 448 cnt48 enumerators；
500 data storages；
600 data outputs.
Specific embodiment
Describe in detail with reference to the accompanying drawings and examples：
First, structure
1st, overall
As Fig. 1, this device includes PLL reference clock 100, measured signal produces circuit 200, Precision delay circuit 300, meter
Number device group 400, data storage 500 data output 600；
Its annexation is：
External input signal has Rst_n：Reset signal, Tr：Outside input clock source, Start：Commencing signal, Stop：Stop
Stop signal；
By outside input：Rst_n（Reset signal）、Tr（Outside input clock source）Defeated as PLL reference clock 100
Enter；
By outside input：Start（Commencing signal）、Stop（Stop signal）Produce the defeated of circuit 200 as measured signal
Enter；
Output C0, C1, C2, C3 of PLL reference clock 100, will be connected to the 1LCELL of Precision delay circuit 300 respectively
The input of chain 310, the input of 2LCELL chain 330, the input of 3LCELL chain 350, the input of 4LCELL chain 370；
All rolling counters forwards that the output gate of measured signal generation circuit 200 is signally attached to enumerator group 400 make
Can end, respectively cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator
424th, cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ... the meter of cnt48 enumerator 448
Number Enable Pin.
The output of the 1LCELL chain 310 of Precision delay circuit 300（Totally 12）, the output of 2LCELL chain 330（Totally 12
Individual）, the output of 3LCELL chain 350（Totally 12）, the output of 4LCELL chain 370（Totally 12）, respectively as enumerator group
400 cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424,
Cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ... the counting of cnt48 enumerator 448 ginseng
Examine clock input；
The output of enumerator group 400（Totally 48）It is connected to the input of data storage 500；
The output of data storage 500 is connected to the input of data output 600.
2nd, functional part
1）PLL reference clock 100
As Fig. 1, PLL reference clock 100 is to directly invoke to be configured building by the IP core of the PLL of altera corp
Hardware circuit.
By Tr：Outside input clock source（Cycle be 20ns, frequency be 50MHz）As input, by PLL reference clock
100 frequencys multiplication, phase shift technology generate with frequency, and two neighboring phase contrast is 90 ° C0, C1, C2 and C3（Cycle is as 5ns, frequently
Rate is 200MHz）.The clock signal feature of C0, C1, C2 and C3 of its output is signal stabilization.
2）Measured signal produces circuit 200
Measured signal produce circuit 200 be a kind of on fpga chip by writing Verilog HDL hardware description language
Come the hardware circuit to design；As Fig. 2, measured signal produces circuit 200 and includes D1Trigger 201, D2Trigger 202, F not gate 203
With ＆ and door 204；
Its annexation is：
Commencing signal Start is as D1The CLK input of trigger 201, stop signal Stop is as D2The CLK of trigger 202
Input, D1Trigger 201 and D2The D input of trigger 202 is set to logical one, by D1The output of trigger 201 is connected to ＆
Input with door 204, D2The output of trigger 202 is connected to F not gate 203 and inputs, and it is defeated with door 204 that F not gate 203 output is connected to ＆
Enter, ＆ is time interval signal gate to be measured with door 204 output.
Its working mechanism is：
As Fig. 2 and Fig. 5, use D1Trigger 201 and D2Trigger 202 is detecting commencing signal Start and stop signal Stop
Rising edge, output detection signal is once detected the rising edge of two signal, that is, exports 1, then by stop signal stop
After the rising edge detection output signal of signal is negated by F not gate 203, defeated with the rising edge detection of commencing signal Start signal
Go out signal by with door 204 with can get time interval signal gate signal.
3）Precision delay circuit 300
Precision delay circuit 300 is that one kind is called LCELL device blocks on fpga chip and write Verilog HDL hardware
Description language come the hardware circuit to design, such as Fig. 3, Precision delay circuit 300 is by 1LCELL chain 310,2LCELL chain
330th, 3LCELL chain 350 and 4LCELL chain 370 are constituted；
1LCELL chain 310 includes LCELL01 device 311, LCELL02 device 312 ... ..., LCELL11 device 321；
2LCELL chain 330 includes LCELL12 device 331, LCELL13 device 332 ... ..., LCELL22 device 341；
3LCELL chain 350 includes LCELL23 device 351, LCELL24 device 352 ... ..., LCELL33 device 361,
4LCELL chain 370 includes LCELL34 device 371, LCELL35 device 372 ... ..., LCELL44 device 381；
Its annexation：
As Fig. 3（a）Understand, 1LCELL chain 310, by LCELL01 device 311, LCELL02 device 312 ... ...,
LCELL11 device 321 is sequentially connected in series the 1LCELL chain 310 of formation；
As Fig. 3（b）Understand, 2LCELL chain 330, by LCELL12 device 331, LCELL13 device 332 ... ...,
LCELL22 device 341 is sequentially connected in series the 2LCELL chain 330 of formation；
As Fig. 3（c）Understand, 3LCELL chain 350, by LCELL23 device 351, LCELL24 device 352 ... ...,
LCELL33 device 361 is sequentially connected in series the 3LCELL chain 350 of formation；
As Fig. 3（d）Understand, 4LCELL chain 370, by LCELL34 device 371, LCELL35 device 372 ... ...,
LCELL44 device 381 is sequentially connected in series the 4LCELL chain 370 of formation；
Its working mechanism：
As Fig. 6,1LCELL chain 310 postpones schematic diagram and understands, PLL reference clock 100 is exported C0 as 1LCELL
The input of chain 310, the path delay time due to single LCELL device is about 105ps, then C0 is in LCELL01 device 311,
LCELL02 device 312 ... ..., LCELL11 device 321 transmits successively, then each LCELL device latencies 105ps, 1LCELL
Chain 310 is to be made up of the LCELL device of 11 path delay about 105ps, it can thus be appreciated that 1LCELL chain 310 total path prolongs
About 1250ps late；
In the same manner, as Fig. 6,2LCELL chain 330 postpones schematic diagram and understands, PLL reference clock 100 is exported C1 as the
The input of 2LCELL chain 330, the path delay time due to single LCELL device is about 105ps, then C1 is in LCELL12 device
Part 331, LCELL13 device 332 ... ..., transmit successively in LCELL22 device 341, then each LCELL device latencies 105ps,
2LCELL chain 330 is to be made up of the LCELL device of 11 path delay about 105ps, it can thus be appreciated that 2LCELL chain 330
Total path delay about 1250ps；
As Fig. 6,3LCELL chain 350 postpones schematic diagram and understands, PLL reference clock 100 is exported C2 as 3LCELL
The input of chain 350, the path delay time due to single LCELL device is about 105ps, then C2 is in LCELL23 device 351,
LCELL24 device 352 ... ..., LCELL33 device 361 transmits successively, then each LCELL device latencies 105ps, 3LCELL
Chain 350 is to be made up of the LCELL device of 11 path delay about 105ps, it can thus be appreciated that 3LCELL chain 350 total path prolongs
About 1250ps late；
As Fig. 6,4LCELL chain 370 postpones schematic diagram and understands, PLL reference clock 100 is exported C3 as 4LCELL
The input of chain 370, the path delay time due to single LCELL device is about 105ps, then C3 is in LCELL34 device 371,
LCELL35 device 372 ... ..., LCELL44 device 381 transmits successively, then each LCELL device latencies 105ps, 4LCELL
Chain 370 is to be made up of the LCELL device of 11 path delay about 105ps, it can thus be appreciated that 4LCELL chain 370 total path prolongs
About 1250ps late.
It follows that 4 frequencies that the input of 4 LCELL chains is PLL reference clock 100 are 200MHz, phase shift is respectively
For 0 °, 90 °, 180 °, 270 °（Time delay is respectively 0ps, 1250ps, 2500ps, 3750ps）, such as Fig. 7, by each LCELL chain
Postpone output just can by the reference clock of 200MHz be roughly divided into 48 delay phase places, will be inclined for the phase place of reference cycle signal
Shifting is uniformly distributed.
4）Enumerator group 400
Enumerator group 400 is the enumerator being designed by Verilog HDL hardware description language on fpga chip, such as
Fig. 4, enumerator group 400 include cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ...,
Cnt24 enumerator 424, cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 meter
Number device 448, totally 48 export the enumerator that width is 10bit（Can be adjusted according to time of measuring size, change enumerator width
Spend）.The frequency of C0, C1, C2 and C3 clock signal of the output of PLL reference clock 100 is 200MHz（Cycle is 5ns）,
So rolling counters forward maximum is 210It is known that the maximum measuring time of invention system is spaced apart 2 in theory10*5(ns).
Its working mechanism is：
As Fig. 4, measured signal is produced the cnt01 enumerator of the output gate of circuit 200 as enumerator group 400
401st ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424, cnt25 enumerator
425th ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., the counting of cnt48 enumerator 448 enable input, by essence
48 producing in close delay circuit 300 are the clock signal of 105ps respectively as enumerator group with frequency, adjacent two signal delays
400 cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424,
Cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., the counting of cnt48 enumerator 448 when
Clock signal, uses rising edging trigger, then 48 enumerators, in the case of gate time interval signal is effective, add up respectively
The number of input reference clock.
5）Data storage 500
Data storage 500 is the memorizer of the IP core realization of the DPRAM directly invoking ltera company.
Its annexation：
Cnt01 enumerator 401 in enumerator group 400 ..., cnt12 enumerator 412, cnt13 enumerator 413 ...,
Cnt24 enumerator 424, cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 meter
The input all as data storage 500 for the 48 count results outputs of number device 448.
Its working mechanism：
The count value of DPRAM each time interval of memory storage, have two sets of completely self-contained data wires, address wire and
Read-write control line, can be cascaded in model machine other subsystems and provide data access, directly invoke the speed of IP core guarantee
Degree and the optimum of power consumption.
6）Data output 600
Data output 600 is to be used improved serial communication protocol to design as the output module of module, by Verilog
HDL Programming with Pascal Language, realizes system and PC, carries out data transmission.
Its annexation：
The output of data storage 500 inputs as data storage 600.
Its working mechanism：
In Protocol Design, pc receiver module design in, receive bits per inch according to when, to bits per inch according in the most stable in
Between the stage carry out multiple repairing weld and ask probabilistic manner to determine this bit level, reach technical grade serial communication standard, improve data output
And the reliability of data that pc machine receives.
3rd, experimental result
This utility model is inputted using the outside input clock source of 50MHz as Tr, to system test process, fixes respectively
Time interval and multiple time interval measure, and its measurement result shows certainty of measurement up to 105ps, between maximum measuring time
It is divided into 5120ns, system run all right, explanation can apply in seismic instrument as chronometer time measuring system.
4th, apply
This utility model is mainly applied and is measured for the precise time-time-interval in seismic instrument, such as satellite laser ranging,
Three-dimensional laser scanner, absolute gravimeter, Hand-hold Distance Finder etc..
Claims (2)
1. a kind of attribute High-precision time interval measurement device based on FPGA it is characterised in that：
Produce circuit (200), Precision delay circuit (300), enumerator group including PLL reference clock (100), measured signal
(400), data storage (500) data output (600)；
Its annexation is：
External input signal has Rst_n：Reset signal, Tr：Outside input clock source, Start：Commencing signal, Stop：Stop letter
Number；
By outside input：Rst_n, Tr are as the input of PLL reference clock (100)；
By outside input：Start, Stop produce the input of circuit (200) as measured signal；
Output C0, C1, C2, C3 of PLL reference clock (100), will be connected to the 1LCELL of Precision delay circuit (300) respectively
The input of chain (310), the input of 2LCELL chain (330), the input of 3LCELL chain (350), 4LCELL chain (370) defeated
Enter；
All rolling counters forwards that the output gate of measured signal generation circuit (200) is signally attached to enumerator group (400) make
Can end, respectively cnt01 enumerator (401) ..., cnt12 enumerator (412), cnt13 enumerator (413) ..., cnt24
Enumerator (424), cnt25 enumerator (425) ..., cnt36 enumerator (436), cnt37 enumerator (437) ... cnt48
The counting Enable Pin of enumerator (448)；
The output of the 1LCELL chain (310) of Precision delay circuit (300) totally 12, the output totally 12 of 2LCELL chain (330)
Individual, 3LCELL chain (350) output totally 12, the output totally 12 of 4LCELL chain (370), respectively as enumerator group
(400) cnt01 enumerator (401) ..., cnt12 enumerator (412), cnt13 enumerator (413) ..., cnt24 counts
Device (424), cnt25 enumerator (425) ..., cnt36 enumerator (436), cnt37 enumerator (437) ... cnt48 count
The counting reference clock input of device (448)；
The output of enumerator group (400) is connected to the input of data storage (500)；
The output of data storage (500) is connected to the input of data output (600).
2. the attribute High-precision time interval measurement device based on FPGA as described in claim 1 it is characterised in that：
Described PLL reference clock (100) is to directly invoke to be configured building by the IP core of the PLL of altera corp
Hardware circuit；
By Tr：The outside input clock source cycle is 20ns, frequency be 50MHz as input, by PLL reference clock (100) times
Frequently, phase shift technology generates with frequency, and two neighboring phase contrast is 90 ° C0, C1, C2 and C3, and the cycle is 5ns, frequency is
200MHz；The clock signal feature of C0, C1, C2 and C3 of its output is signal stabilization.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106019924A (en) * | 2016-07-21 | 2016-10-12 | 中国地震局地震研究所 | FPGA-based counting type high-precision time interval measuring system |
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