CN106019924A - FPGA-based counting type high-precision time interval measuring system - Google Patents
FPGA-based counting type high-precision time interval measuring system Download PDFInfo
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/06—Apparatus for measuring unknown time intervals by electric means by measuring phase
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Abstract
The invention discloses a FPGA-based counting type high-precision time interval measuring system and relates to a precise time interval measuring technique. According to the invention, counting type time interval measurement is realized on a FPGA chip, namely, on the FPGA chip, Verilog HDL hardware description language is used for programming, so as to realize the precise time measuring system for measuring the time interval of a starting event and a stopping event. The system comprises a PLL reference clock (100), a to-be-measured signal generating circuit (200), a precise delay circuit (300), a counter set (400), a data storage (500) and a data output (600). The FPGA-based counting type high-precision time interval measuring system is based on counting type time interval measurement; compared with other FPGA-based time interval measuring systems, the system provided by the invention is more realized relatively simply and occupies less resource; the system is applied to the field, such as, measurement for short time interval in seismic apparatus.
Description
Technical field
The present invention relates to precise time-time-interval measurement technology, particularly relate to a kind of attribute split-second precision based on FPGA
Interval measurement system；Specifically, the present invention is to realize attribute time interval measurement on fpga chip, i.e. at fpga chip
On, by use Verilog HDL hardware description language come programming realization can measure initial, stop event generation time two
The chronometer time at event time interval measures system；The field such as measurement of short time interval in seismic instrument can be applied.
Background technology
High-precision time-interval measurement technique plays very important effect in Observation Technology of Earthquakes, and its time interval is surveyed
The precision of amount directly affects the correctness of observed result, so high-precision time-interval measurement technique is always object of study.
The study hotspot that time interval measurement system realizes is become in recent years based on FPGA.Use fpga chip, Ke Yi great
Big design risk and the system cost of reducing, high integration design can improve reliability and development efficiency, the most easily realize manifold
The measurement in road.
The existing time interval measurement method overwhelming majority is all based on what longer delay chain counting realized, but
It is difficult to inside fpga chip construct and there is outstanding delay concordance and the long delay unit of high latency resolution can be provided, it is desirable to
It is extremely difficult that all delay cells in longer delay chain have well delay concordance.
Time interval measurement principle based on attribute is as the reference clock of enumerator using reference frequency signal, to be measured
Time interval signal is as the enable signal of rolling counters forward, and the count value of enumerator is multiplied by the cycle of reference clock signal and is
The time value of time interval signal to be measured, the time interval resolution obtained is relatively low, but this counting implementation method is relatively simple.
Realizing close temporal system based on FPGA, its low cost, construction cycle be short, flexible design, the compatible advantage such as strong,
Therefore it is necessary for realize chronometer time in this model machine measuring system based on FPGA.
Summary of the invention
Present invention aims to existing attribute and realize the deficiency of time interval measurement, it is provided that be a kind of based on FPGA
Attribute high precision time interval measurement system, with improve time interval measurement precision, reduce measurement error.
The object of the present invention is achieved like this:
On fpga chip, carry out programming realization by Verilog HDL hardware description language and be capable of counting based on FPGA
Type high precision time interval measurement system.
Specifically, native system includes that PLL reference clock, measured signal produce circuit, Precision delay circuit, enumerator
The storage of group, data and data output；
Its annexation is:
External input signal has Rst_n: reset signal, Tr: outside input clock source, Start: commencing signal, Stop: stop letter
Number；
Outside is inputted: Rst_n(reset signal), the outside input clock source of Tr() as the input of PLL reference clock；
Using outside input: Start(commencing signal), Stop(stops signal) as measured signal generation circuit input；
Output C0, C1, C2, C3 of PLL reference clock, respectively by be connected to the 1LCELL chain of Precision delay circuit input,
The input of 2LCELL chain, the input of 3LCELL chain, the input of 4LCELL chain；
The output gate of measured signal generation circuit is signally attached to all rolling counters forward Enable Pins of enumerator group, is respectively
Cnt01 enumerator ..., cnt12 enumerator, cnt13 enumerator ..., cnt24 enumerator, cnt25 enumerator ...,
Cnt36 enumerator, the counting Enable Pin of cnt37 enumerator ... cnt48 enumerator；
The output (totally 12) of the 1LCELL chain of Precision delay circuit, the output (totally 12) of 2LCELL chain, 3LCELL
The output (totally 12) of chain, the output (totally 12) of 4LCELL chain, respectively as enumerator group cnt01 enumerator ...,
Cnt12 enumerator, cnt13 enumerator ..., cnt24 enumerator, cnt25 enumerator ..., cnt36 enumerator, cnt37 meter
The counting reference clock input of number device ... cnt48 enumerator；
The output (totally 48) of enumerator group is connected to the input of data storage；
The output of data storage is connected to the input of data output.
The present invention has following advantages and a good effect:
1. the circuit of the present invention is to be produced, by Verilog HDL hardware description language programming realization by fpga chip；
4 delay chains the most used herein are to have 11 LCELL devices to constitute, and delay chain is shorter, and time delay is relatively accurate, real
The simplest；
3. the reference clock signal that the present invention uses 48 with frequently, adjacent phase difference is equal is as the counting reference of 48 enumerators
Clock signal, to time interval measurement to be measured, is effectively improved Measurement Resolution, and 4 adjacent two phase contrasts of use is
The reference clock signal of 90 °, as reference clock signal, corrects the delay of LCELL chain, greatly reduces measurement error.
4. a width of 10bit of rolling counters forward carry-out bit that the present invention uses, can making according to time interval measurement system
Different by occasion, change counter widths, increase its measurement scope.
5. the present invention is based on attribute time interval measurement, the time interval measurement realized based on FPGA compared to other
For system, this invention is significantly simpler to implement, takies resource less.
The field such as measurement of short time interval in seismic instrument can be applied.
Accompanying drawing explanation
Fig. 1 is the structure chart of native system；
Fig. 2 is the structure chart that measured signal produces circuit；
Fig. 3 is the structure chart of Precision delay circuit；
Fig. 4 is the structure chart of enumerator group；
Fig. 5 is the commencing signal of native system and stops signal two event time interval sequential schematic diagram；
Fig. 6 be native system Precision delay circuit in 4 LCELL chains postpone schematic diagrams；
Fig. 7 is 48 clock signal initial phase schematic diagrams of output of the Precision delay circuit of native system.
In figure:
100 PLL reference clocks；
200 measured signals produce circuit,
201—D1Trigger, 202 D2Trigger,
203 F not gates, 204 & and door；
300 Precision delay circuits,
310 1LCELL chains,
311 LCELL01 devices, 312 LCELL02 devices ..., 321 LCELL11 devices,
330 2LCELL chains,
331 LCELL12 devices, 332 LCELL13 devices ..., 341 LCELL22 devices,
350 3LCELL chains,
351 LCELL23 devices, 352 LCELL24 devices ..., 361 LCELL33 devices,
370 4LCELL chains,
371 LCELL34 devices, 372 LCELL35 devices ..., 381 LCELL44 devices；
400 enumerator groups,
401 cnt01 enumerators ..., 412 cnt12 enumerators,
413 cnt13 enumerators ..., 424 cnt24 enumerators,
425 cnt25 enumerators ..., 436 cnt36 enumerators,
437 cnt37 enumerators ..., 448 cnt48 enumerators；
500 data storages；
600 data outputs.
Detailed description of the invention
Describe in detail with embodiment below in conjunction with the accompanying drawings:
One, structure
1, overall
Such as Fig. 1, native system includes that PLL reference clock 100, measured signal produce circuit 200, Precision delay circuit 300, enumerator
Group 400, data storage 500 and data output 600；
Its annexation is:
External input signal has Rst_n: reset signal, Tr: outside input clock source, Start: commencing signal, Stop: stop letter
Number；
Outside is inputted: Rst_n(reset signal), the outside input clock source of Tr() as the input of PLL reference clock 100；
Using outside input: Start(commencing signal), Stop(stops signal) as measured signal generation circuit 200 input；
Output C0, C1, C2, C3 of PLL reference clock 100, will be connected to the 1LCELL chain of Precision delay circuit 300 respectively
The input of 310, the input of 2LCELL chain 330, the input of 3LCELL chain 350, the input of 4LCELL chain 370；
The output gate of measured signal generation circuit 200 is signally attached to all rolling counters forward Enable Pins of enumerator group 400,
Be respectively cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424,
Cnt25 enumerator 425 ..., cnt36 enumerator 436, the counting of cnt37 enumerator 437 ... cnt48 enumerator 448 make
Can end.
The output (totally 12) of the 1LCELL chain 310 of Precision delay circuit 300, the output (totally 12 of 2LCELL chain 330
Individual), the output (totally 12) of 3LCELL chain 350, the output (totally 12) of 4LCELL chain 370, respectively as enumerator group
The cnt01 enumerator 401 ... of 400, cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424,
Cnt25 enumerator 425 ..., cnt36 enumerator 436, the counting ginseng of cnt37 enumerator 437 ... cnt48 enumerator 448
Examine clock input；
The output (totally 48) of enumerator group 400 is connected to the input of data storage 500；
The output of data storage 500 is connected to the input of data output 600.
2, functional part
1) PLL reference clock 100
As Fig. 1, PLL reference clock 100 be directly invoke by the IP core of the PLL of altera corp be configured building hard
Part circuit.
Using Tr: outside input clock source (cycle be 20ns, frequency be 50MHz) is as inputting, by PLL reference clock
100 frequencys multiplication, phase shift technology generate with frequency, and C0, C1, C2 and C3(cycle that adjacent two phase contrasts are 90 ° is as 5ns, frequently
Rate is 200MHz).The clock signal feature of C0, C1, C2 and C3 of its output is signal stabilization.
2) measured signal produces circuit 200
It is a kind of to set by writing Verilog HDL hardware description language on fpga chip that measured signal produces circuit 200
The hardware circuit of meter；Such as Fig. 2, measured signal produces circuit 200 and includes D1Trigger 201, D2Trigger 202, F not gate 203 and &
With door 204；
Its annexation is:
Commencing signal Start is as D1The CLK input of trigger 201, stops signal Stop as D2The CLK of trigger 202 is defeated
Enter, D1Trigger 201 and D2The D input of trigger 202 is set to logical one, by D1The output of trigger 201 be connected to & with
Door 204 input, D2The output of trigger 202 is connected to F not gate 203 and inputs, and it is defeated with door 204 that F not gate 203 output is connected to &
Entering, & is time interval signal gate to be measured with door 204 output.
Its working mechanism is:
Such as Fig. 2 and Fig. 5, use D1Trigger 201 and D2Trigger 202 detects commencing signal Start and stops signal Stop's
Rising edge, once detects the rising edge of two signal by output detections signal, i.e. exports 1, then will stop signal stop letter
Number rising edge detection output signal negated by F not gate 203 after, detect output with the rising edge of commencing signal Start signal
Signal by with door 204 phase with i.e. can get time interval signal gate signal.
3) Precision delay circuit 300
Precision delay circuit 300 is that one is called LCELL device blocks on fpga chip and writes Verilog HDL hardware description
The hardware circuit that language designs, such as Fig. 3, Precision delay circuit 300 be by 1LCELL chain 310,2LCELL chain 330,
3LCELL chain 350 and 4LCELL chain 370 are constituted；
1LCELL chain 310 includes LCELL01 device 311, LCELL02 device 312 ..., LCELL11 device 321；
2LCELL chain 330 includes LCELL12 device 331, LCELL13 device 332 ..., LCELL22 device 341；
3LCELL chain 350 includes LCELL23 device 351, LCELL24 device 352 ..., LCELL33 device 361,
4LCELL chain 370 includes LCELL34 device 371, LCELL35 device 372 ..., LCELL44 device 381；
Its annexation:
As Fig. 3 (a) understands, 1LCELL chain 310, by LCELL01 device 311, LCELL02 device 312 ..., LCELL11 device
Part 321 is sequentially connected in series the 1LCELL chain 310 of formation；
As Fig. 3 (b) understands, 2LCELL chain 330, by LCELL12 device 331, LCELL13 device 332 ..., LCELL22 device
Part 341 is sequentially connected in series the 2LCELL chain 330 of formation；
As Fig. 3 (c) understands, 3LCELL chain 350, by LCELL23 device 351, LCELL24 device 352 ..., LCELL33 device
Part 361 is sequentially connected in series the 3LCELL chain 350 of formation；
As Fig. 3 (d) understands, 4LCELL chain 370, by LCELL34 device 371, LCELL35 device 372 ..., LCELL44 device
Part 381 is sequentially connected in series the 4LCELL chain 370 of formation；
Its working mechanism:
Such as Fig. 6,1LCELL chain 310 postpones schematic diagram and understands, PLL reference clock 100 is exported C0 as 1LCELL chain 310
Input, owing to the path delay time of single LCELL device is about 105ps, then C0 is at LCELL01 device 311,
LCELL02 device 312 ..., LCELL11 device 321 transmits successively, the most each LCELL device latencies 105ps, 1LCELL
Chain 310 is to be made up of the LCELL device of about 105ps in 11 path delays, it can thus be appreciated that 1LCELL chain 310 total path prolongs
About 1250ps late；
In like manner, such as Fig. 6,2LCELL chain 330 postpones schematic diagram and understands, and PLL reference clock 100 exports C1 as 2LCELL
The input of chain 330, owing to the path delay time of single LCELL device is about 105ps, then C1 is at LCELL12 device 331,
LCELL13 device 332 ..., LCELL22 device 341 transmits successively, the most each LCELL device latencies 105ps, the
2LCELL chain 330 is to be made up of, it can thus be appreciated that 2LCELL chain 330 is total the LCELL device of about 105ps in 11 path delays
Path delay about 1250ps；
Such as Fig. 6,3LCELL chain 350 postpones schematic diagram and understands, PLL reference clock 100 is exported C2 as 3LCELL chain 350
Input, owing to the path delay time of single LCELL device is about 105ps, then C2 is at LCELL23 device 351,
LCELL24 device 352 ..., LCELL33 device 361 transmits successively, the most each LCELL device latencies 105ps, 3LCELL
Chain 350 is to be made up of the LCELL device of about 105ps in 11 path delays, it can thus be appreciated that 3LCELL chain 350 total path prolongs
About 1250ps late；
Such as Fig. 6,4LCELL chain 370 postpones schematic diagram and understands, PLL reference clock 100 is exported C3 as 4LCELL chain 370
Input, owing to the path delay time of single LCELL device is about 105ps, then C3 is at LCELL34 device 371,
LCELL35 device 372 ..., LCELL44 device 381 transmits successively, the most each LCELL device latencies 105ps, 4LCELL
Chain 370 is to be made up of the LCELL device of about 105ps in 11 path delays, it can thus be appreciated that 4LCELL chain 370 total path prolongs
About 1250ps late.
It follows that 4 frequencies that input is PLL reference clock 100 of 4 LCELL chains are 200MHz, phase shift is respectively
Be 0 °, 90 °, 180 °, 270 ° (time delay is respectively 0ps, 1250ps, 2500ps, 3750ps), such as Fig. 7, by each LCELL chain
Postpone output just the reference clock of 200MHz can be roughly divided into 48 postpone phase places, by inclined for the phase place of reference cycle signal
Shifting is uniformly distributed.
4) enumerator group 400
Enumerator group 400 is the enumerator designed by Verilog HDL hardware description language on fpga chip, such as Fig. 4,
Enumerator group 400 includes cnt01 enumerator 401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24
Enumerator 424, cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 enumerator
448, the enumerator that totally 48 output width are 10bit (can adjust according to measuring time size, change counter widths i.e.
Can).The frequency of C0, C1, C2 and C3 clock signal of the output of PLL reference clock 100 is to be 5ns in the 200MHz(cycle), so
Rolling counters forward maximum is 210, it is known that the maximum measuring time of invention system is spaced apart 2 in theory10*5(ns)。
Its working mechanism is:
Such as Fig. 4, measured signal is produced the output gate cnt01 enumerator as enumerator group 400 of circuit 200
401 ..., cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424, cnt25 enumerator
425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 enumerator 448 counting enable input, by essence
48 produced in close delay circuit 300 are that the clock signal of 105ps is respectively as enumerator group with frequency, adjacent two signal delays
The cnt01 enumerator 401 ... of 400, cnt12 enumerator 412, cnt13 enumerator 413 ..., cnt24 enumerator 424,
Cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 enumerator 448 counting time
Clock signal, uses rising edging trigger, then 48 enumerators are in the case of gate time interval signal is effective, add up respectively
The number of input reference clock.
5) data storage 500
Data storage 500 is the memorizer of the IP core realization of the DPRAM directly invoking ltera company.
Its annexation:
Cnt01 enumerator 401 ... in enumerator group 400, cnt12 enumerator 412, cnt13 enumerator 413 ...,
Cnt24 enumerator 424, cnt25 enumerator 425 ..., cnt36 enumerator 436, cnt37 enumerator 437 ..., cnt48 meter
48 count results outputs of number device 448 are all as the input of data storage 500.
Its working mechanism:
DPRAM memorizer stores the count value of each time interval, has the two completely self-contained data wires of set, address wire and read-write
Control line, can be cascaded in model machine other subsystem and provide data access, directly invoke IP core ensure speed and
The optimum of power consumption.
6) data output 600
Data output 600 is to use the serial communication protocol improved to design, by Verilog HDL as the output module of module
Programming with Pascal Language, it is achieved system and PC, carries out data transmission.
Its annexation:
The output of data storage 500 is as data storage 600 input.
Its working mechanism:
In Protocol Design, in pc receiver module designs, receive bits per inch according to time, to bits per inch according in the most stable scala media
Duan Jinhang multiple repairing weld asks probabilistic manner to determine this bit level, reaches technical grade serial communication standard, improves data output and pc
The reliability of the data that machine receives.
Three, experimental result
The present invention inputs using the outside input clock source of 50MHz as Tr, to system test process, difference Fixed Time Interval
Measuring with multiple time interval, its measurement result shows that certainty of measurement is spaced apart up to 105ps, maximum measuring time
5120ns, system run all right, explanation can be measured system as chronometer time and be applied in seismic instrument.
Four, application
The present invention mainly applies the precise time-time-interval in seismic instrument to measure, such as satellite laser ranging, three-dimensional laser
Scanner, absolute gravimeter, Hand-hold Distance Finder etc..
Claims (7)
1. an attribute high precision time interval measurement system based on FPGA, it is characterised in that:
Circuit (200), Precision delay circuit (300), enumerator group is produced including PLL reference clock (100), measured signal
(400), data storage (500) and data output (600)；
Its annexation is:
External input signal has Rst_n: reset signal, Tr: outside input clock source, Start: commencing signal, Stop: stop letter
Number；
Outside is inputted: Rst_n, Tr are as the input of PLL reference clock (100)；
Outside is inputted: Start, Stop produce the input of circuit (200) as measured signal；
Output C0, C1, C2, C3 of PLL reference clock (100), will be connected to the 1LCELL of Precision delay circuit (300) respectively
The input of chain (310), the input of 2LCELL chain (330), the input of 3LCELL chain (350), 4LCELL chain (370) defeated
Enter；
The output gate of measured signal generation circuit (200) is signally attached to all rolling counters forwards of enumerator group (400) to be made
Energy end, respectively cnt01 enumerator (401) ..., cnt12 enumerator (412), cnt13 enumerator (413) ..., cnt24
Enumerator (424), cnt25 enumerator (425) ..., cnt36 enumerator (436), cnt37 enumerator (437) ... cnt48
The counting Enable Pin of enumerator (448)；
The output (totally 12) of the 1LCELL chain (310) of Precision delay circuit (300), the output of 2LCELL chain (330) (are total to
12), the output (totally 12) of 3LCELL chain (350), the output (totally 12) of 4LCELL chain (370), respectively as meter
Number device groups (400) cnt01 enumerator (401) ..., cnt12 enumerator (412), cnt13 enumerator (413) ...,
Cnt24 enumerator (424), cnt25 enumerator (425) ..., cnt36 enumerator (436), cnt37 enumerator (437) ...
The counting reference clock input of cnt48 enumerator (448)；
The output of enumerator group (400) is connected to the input of data storage (500)；
The output of data storage (500) is connected to the input of data output (600).
2. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described PLL reference clock (100) is to directly invoke to be configured building by the IP core of the PLL of altera corp
Hardware circuit；
Using Tr: outside input clock source (cycle be 20ns, frequency be 50MHz) is as inputting, by PLL reference clock (100)
Frequency multiplication, phase shift technology generate with frequency, and C0, C1, C2 and C3(cycle that adjacent two phase contrasts are 90 ° is as 5ns, frequency
It is 200MHz)；The clock signal feature of C0, C1, C2 and C3 of its output is signal stabilization.
3. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described measured signal produce circuit (200) be a kind of on fpga chip by writing Verilog HDL hardware description
The hardware circuit that language designs, including D1Trigger (201), D2Trigger (202), F not gate (203) and & and door (204).
4. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described Precision delay circuit (300), is to call LCELL device blocks on fpga chip and to write Verilog HDL hard
Part describes the hardware circuit that language designs, and is by 1LCELL chain (310), 2LCELL chain (330), 3LCELL chain
(350) constitute with 4LCELL chain (370)；Wherein 1LCELL chain (310) includes LCELL01 device (311), LCELL02
Device (312) ..., LCELL11 device (321)；2LCELL chain (330) includes LCELL12 device (331), LCELL13 device
Part (332) ..., LCELL22 device (341)；3LCELL chain (350) includes LCELL23 device (351), LCELL24 device
(352) ..., LCELL33 device (361), 4LCELL chain (370) includes LCELL34 device (371), LCELL35 device
(372) ..., LCELL44 device (381).
5. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described enumerator group (400) is the counting designed by Verilog HDL hardware description language on fpga chip
Device, including cnt01 enumerator (401) ..., cnt12 enumerator (412), cnt13 enumerator (413) ..., cnt24 meter
Number device (424), cnt25 enumerator (425) ..., cnt36 enumerator (436), cnt37 enumerator (437) ..., cnt48
Enumerator (448), totally 48 output width are the enumerator of 10bit；C0, C1, C2 of the output of PLL reference clock (100)
It is 200MHz with the frequency of C3 clock signal.
6. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described data storage (500) are the memorizeies of the IP core realization of the DPRAM directly invoking ltera company.
7. the attribute high precision time interval measurement system based on FPGA as described in claim 1, it is characterised in that:
Described data output (600) are to use the serial communication protocol improved to design as the output module of module, pass through
Verilog HDL Programming with Pascal Language, it is achieved system carries out data transmission with PC.
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| CN109407500A (en) * | 2018-11-22 | 2019-03-01 | 深圳天眼激光科技有限公司 | Time interval measuring method based on FPGA |
| CN112327694A (en) * | 2020-11-04 | 2021-02-05 | 中北大学 | High-precision three-level time delay system and method based on FPGA |
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| CN206002858U (en) * | 2016-07-21 | 2017-03-08 | 中国地震局地震研究所 | A kind of attribute High-precision time interval measurement device based on FPGA |
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| CN109407500A (en) * | 2018-11-22 | 2019-03-01 | 深圳天眼激光科技有限公司 | Time interval measuring method based on FPGA |
| CN109407500B (en) * | 2018-11-22 | 2021-03-23 | 深圳天眼激光科技有限公司 | Time interval measuring method based on FPGA |
| CN112327694A (en) * | 2020-11-04 | 2021-02-05 | 中北大学 | High-precision three-level time delay system and method based on FPGA |
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