CN103345144A - Time measurement method and device - Google Patents
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- CN103345144A CN103345144A CN2013102558959A CN201310255895A CN103345144A CN 103345144 A CN103345144 A CN 103345144A CN 2013102558959 A CN2013102558959 A CN 2013102558959A CN 201310255895 A CN201310255895 A CN 201310255895A CN 103345144 A CN103345144 A CN 103345144A
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Abstract
The invention discloses a time measurement method and device which are applied to an FPGA. An input clock is converted to N sub clocks, and the period of each sub clock is M, wherein the quotient obtained by dividing M with N is the smallest counting unit for time measurement; the phase difference between every two adjacent sub clocks is adjusted to be L, wherein L is the quotient obtained by dividing 360 degrees with N; when timing is started, the number of the smallest counting units which the sub clocks pass through is recorded; when occurrence of a preset event is detected the total number of the smallest counting units which the sub clocks pass through is recorded to calculate the occur moment of the preset event, and the smallest time unit of the occur moment is the smallest counting unit. Therefore, through the method that the input clock of an FPGA chip is adjusted to form a plurality of sub clocks with the same period and the phase difference between every two adjacent sub clocks is correspondingly adjusted, the smallest counting unit of the FPGA can be increased, and the technical effect that the time measurement precision of a PET system is improved is achieved.
Description
Technical field
The present invention relates to computer realm, particularly relate to a kind of Method Of Time Measurement and device.
Background technology
PET (Positron Emission Tomograph, positron emission computerized tomography device) is at the decay process positron annihilation radiation that produces and the computerized tomograph that meets the detection principle formation according to the radioactive nuclide in the injection body.The PET video picture is a kind of " isotopic tagging image technology ".The PET imaging at first need be injected the synthetic biological spike medicine of radioactive nuclide that can discharge positron in the patient body, the position of the annihilation reaction by the detection of radioactive nucleic is further analyzed then.
The concrete process of burying in oblivion is such, and biological spike medicine is the nucleic of rich proton normally, and they can produce positron in decay process.The positron that radioactive nuclide in the injection body is launched meeting negatron in human body in human body is combined annihilation radiation is taken place, and it is identical to produce two energy during positron-electron annihilation, and the γ photon that direction is opposite is measured with two detectors staggered relatively.Because the path difference of two photons in human body, also there is certain difference the time that arrives two detectors, if in the official hour window, detector system detects two photons that are mutually 180 degree, and then this event is referred to as coincident event.By coincident event is handled and calculated, finally form needed PET image.
In novel TOF (Time of Flight, flight time) PET, the photon of two annihilation radiations arrives real time of detector can measured and record, utilizes two photons to arrive mistiming of detectors, can determine the position of annihilation radiation in theory.The emphasis of TOF technology is exactly to demarcate the time that photon arrives detector accurately, the precision of demarcating is more high, final determine to bury in oblivion the position more accurate, yet the time measurement precision of TOF PET of the prior art is not high, the result who has caused determining burying in oblivion the position is very inaccurate.This shows how improving the time measurement accuracy that produces for this event of photon arrival detector is the problem that needs solve.
Summary of the invention
In order to solve the not high technical matters of Measuring Time precision among the above-mentioned PET, the invention provides a kind of Method Of Time Measurement and device.
The embodiment of the invention discloses following technical scheme:
A kind of Method Of Time Measurement is applied in the on-site programmable gate array FPGA, and the input clock of FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is divided by the merchant of the N least count unit for time measurement; Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N; When picking up counting, comprising:
Record period of the day from 11 p.m. to 1 a.m clock is through the number of least count unit;
When detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
Preferably, also comprise reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
Preferably, described input clock with FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is specially for the least count unit of time measurement divided by the merchant of N:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, described number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, and wherein L is that 360 ° of merchants divided by N are specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, the cycle of described reference clock is 250ns.
A kind of time measurement device is applied in the on-site programmable gate array FPGA, and the input clock of FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is divided by the merchant of the N least count unit for time measurement; Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N; When picking up counting, comprising:
Counting unit is used for record period of the day from 11 p.m. to 1 a.m clock through the number of least count unit;
Determine to take place unit constantly, be used for when detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
Preferably, also comprise reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
Preferably, the described unit that arranges is specially:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, the described unit that arranges is specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, the cycle of described reference clock is 250ns.
By technique scheme as can be seen, by the input clock in the fpga chip being adjusted to the period of the day from 11 p.m. to 1 a.m clock of a plurality of same period, and phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock of corresponding adjustment, thereby can improve the least count unit of FPGA, and then reach the technique effect that improves PET systematic survey time precision, improved the signal to noise ratio (S/N ratio) of PET system thus greatly.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the method flow diagram of a kind of Method Of Time Measurement of the present invention;
Fig. 2 is the system construction drawing that the present invention is based on the time measurement system of fpga chip;
Fig. 3 is the structure drawing of device of a kind of time measurement device of the present invention.
Embodiment
The embodiment of the invention provides a kind of Method Of Time Measurement and device.At first, by the input clock in the fpga chip being adjusted to the period of the day from 11 p.m. to 1 a.m clock of a plurality of same period, and phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock of corresponding adjustment, thereby can improve the least count unit of FPGA, and then reach the technique effect that improves PET systematic survey time precision, improved the signal to noise ratio (S/N ratio) of PET system thus greatly.
Secondly, add reference clock after, each predetermined period passes through several zero clearings of least count unit with the period of the day from 11 p.m. to 1 a.m clock of record, improves the counting yield of system greatly, has further strengthened user experience.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the embodiment of the invention is described in detail.
Embodiment one
See also Fig. 1, it is the method flow diagram of a kind of Method Of Time Measurement of the present invention, is applied among the FPGA (Field-ProgrammableGateArray, field programmable gate array), and this method comprises the stage of setting:
The input clock of FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is the least count unit of time measurement divided by the merchant of N;
Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N;
Preferably, described input clock with FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is specially for the least count unit of time measurement divided by the merchant of N:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, described number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, and wherein L is that 360 ° of merchants divided by N are specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
This step mainly is to preset step, realize by the internal logic of FPGA, at first the Clock Managing Unit by FPGA is configured the input clock of FPGA, in general the input clock of FPGA is the clock of frequency 100mhz, by being divided into the period of the day from 11 p.m. to 1 a.m clock of a plurality of higher same frequencys after the Clock Managing Unit configuration, the number of period of the day from 11 p.m. to 1 a.m clock and frequency in the operating range of FPGA, be adjustable in theory, the foundation of adjusting mainly is the least count unit, that is to say it is the minimum time unit of timing, this is also representing the very important mark post of the degree of accuracy of time calibrating measurement.Set the number and corresponding clock period of period of the day from 11 p.m. to 1 a.m clock in least count unit as required after, enter step S101 and carry out concrete counting flow process.
Certainly, based on the phase differential of 18 ° on period of the day from 11 p.m. to 1 a.m clock that 20 cycles preferably are set is 2.5ns and adjacent period of the day from 11 p.m. to 1 a.m clock in this optimum embodiment can be described in detail with concrete application scenarios at last at embodiment one.Need to prove that simultaneously the concrete numerical value in the number of antithetical phrase clock of the present invention and cycle does not limit, and can arrange according to the actual requirements.
When picking up counting:
S101: record period of the day from 11 p.m. to 1 a.m clock is through the number of least count unit;
When system starts, start working according to the multichannel period of the day from 11 p.m. to 1 a.m clock of FPGA internal logic setting, each period of the day from 11 p.m. to 1 a.m clock of real time record the number of least count unit of process.
Preferably, also comprise reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
Preferably, the cycle of described reference clock is 250ns.
Here need to prove, if continue each period of the day from 11 p.m. to 1 a.m clock of meter record in the course of work through the number of least count unit, working pressure to record cell can be very big, also can produce bigger calculating pressure to the calculating of follow-up summation, so preferably introduced the major clock of reference clock as system here, whenever reference clock (can be one-period or pre-set a plurality of cycles through predetermined period here, the present invention does not limit this), just the record that will pass through the storage unit of least count unit number for each period of the day from 11 p.m. to 1 a.m clock that preservation is recorded empties, start from scratch then and continue counting, like this can effectively improve operation efficiency, under the situation that guarantees the time calibrating precision, further improve user experience.In actual operation, the cycle is that the reference clock of 250ns is comparatively preferred reference clock, and certainly, the present invention did not limit the concrete cycle of reference clock.
S102: when detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
Scheduled event described here refers to that mainly the photon that produces when positron is buried in oblivion arrives detector or is detected the event that device detects, certainly, also can be other events, such as be the event that any needs are determined concrete triggered time, the time of reaching etc., the present invention does not specifically limit scheduled event.
When event takes place, each period of the day from 11 p.m. to 1 a.m clock of system log (SYSLOG) process the least count unit number and add up, thereby the time the when event of determining takes place.
To come by concrete application scenarios technical scheme of the present invention is described below, before introducing concrete system architecture, the background of this application scenarios is once described earlier, technical scheme of the present invention is mainly used on the PET instrument, wherein possible application scenarios is exactly the time that the photon that produces when measuring positron annihilation is run into detector, be exactly that the negatron of positron in human body that inject the active nucleus of human body is combined annihilation radiation is taken place specifically, produced the opposite γ photon of two energy identical (511keV) direction after burying in oblivion, poor by time and the computing time of detecting these two photons arrival detectors, can whether satisfy the schedule time according to the described mistiming and judge whether to be a coincident event, parameters such as number according to coincident event are further operated, as seen, the precision of systematic survey time is more high, and the judged result that causes thus also can be more accurate.
In this application scenarios, according to the feature of putting down in writing among the step S100 is set, with the input clock of the cycle 100MHZ of the FPGA period of the day from 11 p.m. to 1 a.m clock that to be arranged to 20 cycles be 400MHZ, and the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 °, after arranging like this, 20 road high frequency clocks all are operated in 400M, and its cycle is 2.5ns.As previously mentioned, 18 ° of phase phasic differences between per two pll, each cycle is 360 °, so 20 high frequency clocks can cover whole cycles, namely Zui Xiao time counting unit can reach 2.5ns/20=125ps, our the highest temporal resolution that can realize that Here it is.Concrete system architecture sees also Fig. 2, it is the system construction drawing that the present invention is based on the time measurement system of fpga chip, comprise input clock unit 21, period of the day from 11 p.m. to 1 a.m clock unit 22, counting unit 23, latch units 24 and sum unit 25, as can be seen, by the period of the day from 11 p.m. to 1 a.m clock 22 that the input clock of the cycle 100MHZ of input clock unit 21 input is arranged to 20 cycles is 400MHZ, all be connected to separately behind each period of the day from 11 p.m. to 1 a.m clock counting unit be used for record period of the day from 11 p.m. to 1 a.m clock the number of least count unit of process, the output terminal of each counting unit 23 all is connected to a latch units 24 separately, counting unit 23 with the period of the day from 11 p.m. to 1 a.m clock that records the number of least count unit of process send in the latch units 24, photon that scheduled event produces during positron annihilation in other words when taking place and run into detector in latch units 24, to lock and send to sum unit 25 from the numerical value that technical unit 23 receives, the data input pin of sum unit 25 links to each other with the data output end of all latch units 24, be used for when photon that scheduled event produces during positron annihilation in other words taking place run into detector, the numerical value that each latch units that receives is sent carries out read group total, thereby the time that the event of determining takes place is to the time calibrating precision of 125ps.
Simultaneously, preferably also comprise zero clearing unit 26, the output terminal of described zero clearing unit 26 links to each other with individual count unit 23 and latch units 24 respectively, the input end of described zero clearing unit 26 links to each other with reference clock, in this application scene, the cycle of reference clock is 4MHZ, whenever reference clock during through a clock period, trigger zero clearing unit 26 and send clear command to individual count unit 23 and latch units 24, with numerical value zero clearing in individual count unit 23 and the latch units 24, making counting unit 23 start from scratch counts again, improved the operation efficiency of sum unit 25 thus, need to prove that simultaneously can be set at a plurality of cycles of every process to trigger the zero clearing unit, the present invention does not limit this yet.
After the photon that produces when accurately measuring a positron annihilation is run into the time of detector, can be by definite time of running into detector with another this time corresponding photon of the event criteria of coincident event, the event criteria of coincident event described here comprises three kinds of different classifications, first kind is the true coincidence event, two photon sources that namely detect are in same annihilation event, and all less than with medium any interaction taking place, they contain accurate localization information to these two photons before arriving detector.Second kind is the scattering coincident event, two photon sources that namely detect are in same annihilation event, but in arriving preceding two photons of detector, have at least the scattering of a process to retrodeviate from original direction, so the locating information that this coincident event contains is inaccurate.The third is coincident event at random, and two photons that detect are not from same annihilation event.
Event criteria by above-mentioned coincident event and same Method Of Time Measurement are determined with after another this time corresponding photon is run into the corresponding time of detector, obtain the mistiming of twice time, if the mistiming (when in general being decided to be 8～12ns), then can determine to have taken place one time coincident event less than the schedule time.
By present embodiment as can be seen, by the input clock in the fpga chip being adjusted to the period of the day from 11 p.m. to 1 a.m clock of a plurality of same period, and phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock of corresponding adjustment, thereby can improve the least count unit of FPGA, and then reach the technique effect that improves PET systematic survey time precision, improved the signal to noise ratio (S/N ratio) of PET system thus greatly, secondly, after adding reference clock, each predetermined period passes through the period of the day from 11 p.m. to 1 a.m clock of record several zero clearings of least count unit, improve the counting yield of system greatly, further strengthened user experience.
Embodiment two
Corresponding with above-mentioned a kind of Method Of Time Measurement, the embodiment of the invention also provides a kind of time measurement device.See also Fig. 3, it is the structure drawing of device of a kind of time measurement device of the present invention, and this device comprises and unit 300, counting unit 301 is set and determines to take place unit 302 constantly.
Unit 300 is set, is used for the input clock of FPGA is converted to N sub-clock, the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is the least count unit of time measurement divided by the merchant of N; Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N;
Preferably, the described unit that arranges is specially:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Preferably, the described unit that arranges is specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
Counting unit 301 is used for record period of the day from 11 p.m. to 1 a.m clock through the number of least count unit;
Determine to take place unit 302 constantly, be used for when detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
Preferably, also comprise reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
Preferably, the cycle of described reference clock is 250ns.
As can be seen from the above-described embodiment, by the input clock in the fpga chip being adjusted to the period of the day from 11 p.m. to 1 a.m clock of a plurality of same period, and phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock of corresponding adjustment, thereby can improve the least count unit of FPGA, and then reach the technique effect that improves PET systematic survey time precision, improved the signal to noise ratio (S/N ratio) of PET system thus greatly.
Need to prove, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random AccessMemory, RAM) etc.
More than a kind of Method Of Time Measurement provided by the present invention and device are described in detail, used specific embodiment herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a Method Of Time Measurement is applied to it is characterized in that in the on-site programmable gate array FPGA, and the input clock of FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is divided by the merchant of the N least count unit for time measurement; Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N; When picking up counting, comprising:
Record period of the day from 11 p.m. to 1 a.m clock is through the number of least count unit;
When detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
2. method according to claim 1 is characterized in that, also comprises reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
3. method according to claim 1 is characterized in that, described input clock with FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is specially for the least count unit of time measurement divided by the merchant of N:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
4. according to claim 1 or 3 described methods, it is characterized in that described number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L is that 360 ° of merchants divided by N are specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
5. method according to claim 2 is characterized in that, the cycle of described reference clock is 250ns.
6. a time measurement device is applied to it is characterized in that in the on-site programmable gate array FPGA, and the input clock of FPGA is converted to N sub-clock, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is M, and wherein, M is divided by the merchant of the N least count unit for time measurement; Number N according to period of the day from 11 p.m. to 1 a.m clock is adjusted into L with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein L be 360 ° divided by the merchant of N; When picking up counting, comprising:
Counting unit is used for record period of the day from 11 p.m. to 1 a.m clock through the number of least count unit;
Determine to take place unit constantly, be used for when detecting the scheduled event generation, total number of each period of the day from 11 p.m. to 1 a.m clock process least count unit that records when taking place according to scheduled event calculates the generation moment of scheduled event, and the described minimum time unit that the moment takes place is described least count unit.
7. device according to claim 6 is characterized in that, also comprises reference clock:
Described reference clock is every through predetermined period, counts again after the number zero clearing with described record period of the day from 11 p.m. to 1 a.m clock process least count unit.
8. device according to claim 6 is characterized in that, the described unit that arranges is specially:
The input clock of FPGA is converted to 20 sub-clocks, and the cycle of each period of the day from 11 p.m. to 1 a.m clock is 2.5ns, and wherein, the cycle 2.5ns of each period of the day from 11 p.m. to 1 a.m clock is the least count unit 125ps of time measurement divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
9. according to claim 6 or 8 described devices, it is characterized in that the described unit that arranges is specially:
Number 20 according to period of the day from 11 p.m. to 1 a.m clock is adjusted into 18 ° with the phase differential between the adjacent period of the day from 11 p.m. to 1 a.m clock, wherein 18 ° be 360 ° divided by the merchant of the number 20 of period of the day from 11 p.m. to 1 a.m clock.
10. device according to claim 7 is characterized in that, the cycle of described reference clock is 250ns.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103676621A (en) * | 2013-12-18 | 2014-03-26 | 哈尔滨工程大学 | Method and device for measuring electric signal transmission time in phase-type wire |
| CN106019924A (en) * | 2016-07-21 | 2016-10-12 | 中国地震局地震研究所 | FPGA-based counting type high-precision time interval measuring system |
| US9866220B2 (en) | 2015-12-08 | 2018-01-09 | Shenyang Neusoft Medical Systems Co., Ltd. | Timing device |
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