CN103135650A - Current/frequency conversion circuit linearity and symmetry digital compensation method - Google Patents

Current/frequency conversion circuit linearity and symmetry digital compensation method Download PDF

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CN103135650A
CN103135650A CN2013100206137A CN201310020613A CN103135650A CN 103135650 A CN103135650 A CN 103135650A CN 2013100206137 A CN2013100206137 A CN 2013100206137A CN 201310020613 A CN201310020613 A CN 201310020613A CN 103135650 A CN103135650 A CN 103135650A
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symmetry
coefficient
conversion circuit
compensation
linearity
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CN103135650B (en
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黄丽娟
邵志浩
万志江
吕江涛
李星善
陆俊清
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General Designing Institute of Hubei Space Technology Academy
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General Designing Institute of Hubei Space Technology Academy
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Abstract

The invention discloses a current/frequency conversion circuit linearity and symmetry digital compensation method. The current/frequency conversion circuit linearity and symmetry digital compensation method comprises the steps of measuring and recording D trigger output pulse number and subdivided pulse number when different current values are input into a current/frequency conversion circuit; confirming conversion circuit linearity compensation factors and performing compensation to a conversion circuit output in digital mode; measuring and obtaining symmetrical coefficient and zero coefficient of the current/frequency conversion circuit; and confirming symmetrical compensation coefficient of the conversion circuit and performing real-time compensation to the conversion circuit output in digital mode. By means of the current/frequency conversion circuit linearity and symmetry digital compensation method, the problems including complicated operation, effective accuracy, high demands on debugging persons and unsatisfied batch production demand in the current production debugging process is effectively solved.

Description

Electric current/frequency-conversion circuit linearity and symmetry of the figure compensation method
Technical field
The present invention relates to the field of measuring technique of current mode device, refer to particularly a kind of electric current/frequency-conversion circuit linearity and symmetry of the figure compensation method.
Background technology
Electric current/frequency-conversion circuit is adopted in measurement to the current mode device usually, and its output pulse frequency is directly proportional to the input current size.Affected by translation circuit components and parts actual parameter, there is error in on-off circuit single charge/discharge electricity amount, causes translation circuit to exist non-linear, and because positive and negative passage independence and have asymmetry, therefore, be necessary the non-linear and symmetry of electric current/frequency-conversion circuit is compensated.
At present in production run, by changing the switch triode base stage saturation current adjustment translation circuit linearity in electric current/frequency-conversion circuit, adjust the translation circuit symmetry by changing the positive and negative constant flow source electric current, the precision resistance resistance that is used for debugging needs through rough estimation and repetition test adjustment, operating process is complicated, precision is limited, and the commissioning staff is had relatively high expectations, and can't adapt to the batch production demand.
Summary of the invention
The object of the invention is to overcome the limitation of existing electric current/frequency-conversion circuit linearity, symmetry adjustment method, a kind of simple and effective electric current/frequency-conversion circuit linearity and symmetry of the figure compensation method is provided.
For achieving the above object, the designed electric current of the present invention/frequency-conversion circuit linearity and symmetry of the figure compensation method comprises the following steps:
(1) by constant current source to the different current value of electric current/frequency-conversion circuit input, measure and the record coversion circuit in sub-divided pulse number when the corresponding pulses number, sub-divided pulse number of d type flip flop output and zero current;
During (2) according to umber of pulse, sub-divided pulse number and zero current, the sub-divided pulse number, determine the linearity compensation coefficient, and the linearity compensation coefficient formula is as follows:
k p = I 2 ( n 1 - m 1 ) - I 1 ( n 2 - m 2 ) I 1 ( m 2 - n 0 ) - I 2 ( m 1 - n 0 )
Wherein, I iBe input current value, m iBe the umber of pulse of d type flip flop output, n iBe sub-divided pulse number, n 0Sub-divided pulse number during for zero current, i=0,1,2, k pBe the linearity compensation coefficient;
(3) according to the linearity compensation coefficient, the sub-divided pulse number that translation circuit is exported carries out linearity real-Time Compensation;
(4) to through the electric current after linearity real-Time Compensation/frequency-conversion circuit input n to different current value+I ' i ,-I ' i, measure and record corresponding pulses number and the segmentation afterpulse number of d type flip flop output, described+I ' i ,-I ' i is the identical reversal of size, determines symmetry coefficient and the zero-bit coefficient of electric current/frequency-conversion circuit according to this corresponding pulses number;
(5) according to symmetry coefficient and zero-bit coefficient, determine the symmetry penalty coefficient, symmetry penalty coefficient formula is as follows:
k s = ( 1 - k 0 ) ( 1 + k 0 + k 2 ) ( 1 + k 0 ) ( 1 - k 0 - k 2 )
Wherein, k 2Be symmetry coefficient, k 0The zero-bit coefficient, k sBe the symmetry penalty coefficient;
(6) according to the symmetry penalty coefficient, the sub-divided pulse number that translation circuit is exported carries out the symmetry real-Time Compensation.
In the step of technique scheme (3), it is as follows that linearity compensation coefficient and linearity compensation afterpulse are counted the formula of relation:
n p＝n i-m i+m i×k p
Wherein, n pBe linearity compensation afterpulse number.
In the step of technique scheme (4), the symmetry coefficient of determining electric current/frequency-conversion circuit according to corresponding pulses number and the sub-divided pulse number of d type flip flop output and the process of zero-bit coefficient are, first determine constant multiplier and zero-bit coefficient according to the corresponding pulses number, according to constant multiplier and zero-bit parameter identification symmetry coefficient, each formula is as follows again:
k 1 = Σ i = 1 n ( N + i + N - i ) 2 × n × T - - - ( a )
k 0 = N 0 T - - - ( b )
k 2 = Σ i = 1 n ( N + i - N - i ) 2 × n × T × k 1 - k 0 - - - ( c )
Determine reaching of electric current/frequency-conversion circuit;
Wherein, N + i, N -i, N 0Be respectively input+I ' i,-I ' iWhen reaching zero current, the sub-divided pulse number of translation circuit output, T is the count cycle, k 1Be constant multiplier, k 0Be zero-bit coefficient, k 2Be the symmetry coefficient.
In the step of technique scheme (6), it is as follows that symmetry penalty coefficient and symmetry compensation afterpulse is counted the formula of relation:
n s＝n p×k s
Wherein, n sFor repaying umber of pulse after the symmetry benefit.
In technique scheme, described current value I i,+I ' iWith-I ' iSpan be to choose according to the range of electric current/frequency-conversion circuit.
Beneficial effect of the present invention:
(1) electric current of the present invention/frequency-conversion circuit linearity and symmetry of the figure compensation method, on the basis that does not increase any cost, can realize electric current/frequency-conversion circuit linearity, symmetric digital compensation, compare with present hardware debug compensation, simple to operate, compensation precision is high, has improved debugging efficiency;
(2) electric current of the present invention/frequency-conversion circuit linearity and symmetry of the figure compensation method can utilize the FPGA(field programmable gate array when concrete the application), realize pulse data collection and compensation calculating;
(3) electric current of the present invention/frequency-conversion circuit linearity and symmetry of the figure compensation method, real-time is high, satisfies the occasion that dynamic is had relatively high expectations fully.
By electric current provided by the invention/frequency-conversion circuit linearity and symmetry of the figure compensation method, effectively solved complicated operation in present production debug process, precision effectively, the commissioning staff is had relatively high expectations, can't satisfy the problem of batch production demand.
Description of drawings
Fig. 1 is electric current in prior art/frequency-conversion circuit block diagram.
Fig. 2 is the process flow diagram of electric current of the present invention/frequency-conversion circuit linearity and symmetry of the figure compensation method.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Electric current/frequency-conversion circuit d type flip flop incoming frequency is 80kHz, is output as pulse signal, and high level is effective.Under larger electric current input condition, there is adhesion phenomenon in d type flip flop output pulse, therefore d type flip flop need to be exported pulse and input clock and carry out the logical and operation, and the pulse after logical and is sub-divided pulse and counts n i
By constant current source, electric current/frequency-conversion circuit is inputted different current value I i(for example 30s) d type flip flop output umber of pulse m in the certain intervals time is measured and recorded to (choosing of current value needs or inhomogeneous choose even according to electric current/frequency-conversion circuit range, comprises zero current) i, sub-divided pulse counts n i(the sub-divided pulse number be d type flip flop output pulse with the d type flip flop input clock carry out with operate after umber of pulse) and during zero current sub-divided pulse count n 0
The linearity compensation coefficient k pWith umber of pulse m i, sub-divided pulse counts n iWhen reaching zero current, sub-divided pulse is counted n 0The expression formula of relation is as follows:
k p = I 2 ( n 1 - m 1 ) - I 1 ( n 2 - m 2 ) I 1 ( m 2 - n 0 ) - I 2 ( m 1 - n 0 )
Wherein, I iBe input current value, m iBe d type flip flop output umber of pulse, n iBe sub-divided pulse number, n 0Sub-divided pulse number during for zero current, i=0,1,2, k pBe the linearity compensation coefficient.
Through type (1) calculates the linearity compensation coefficient k p, write corresponding hardware description language code and realize linearity real-Time Compensation in FPGA.In FPGA, to setting (for example 10ms, can be set as the unit interval) d type flip flop umber of pulse m in interval time iAnd sub-divided pulse is counted n iCount, the linearity compensation afterpulse is counted n pExpression formula is as follows:
n p＝n i-m i+m i×k p
Linearity compensation after-current/frequency-conversion circuit is inputted n to different current value+I ' i,-I ' i, wherein+I ' i,-I ' iBe the identical reversal of size, measure and record umber of pulse and the sub-divided pulse number of d type flip flop output, determine symmetry coefficient and the zero-bit coefficient of electric current/frequency-conversion circuit.
Constant multiplier k 1, the symmetry coefficient k 2And zero-bit coefficient k 0Expression formula as follows:
k 1 = Σ i = 1 n ( N + i + N - i ) 2 × n × T - - - ( a )
k 0 = N 0 T - - - ( b )
k 2 = Σ i = 1 n ( N + i - N - i ) 2 × n × T × k 1 - k 0 - - - ( c )
Wherein, N + i, N -i, N 0Be input+I ' i,-I ' iWhen reaching zero current, the sub-divided pulse number of translation circuit output, T is the count cycle, n is the right quantity of reversal of getting.
Symmetry penalty coefficient k sWith the symmetry coefficient k 2, the zero-bit coefficient k 0The expression formula of relation is as follows:
k s = ( 1 - k 0 ) ( 1 + k 0 + k 2 ) ( 1 + k 0 ) ( 1 - k 0 - k 2 )
Calculate symmetry penalty coefficient k s, realize the symmetry real-Time Compensation to translation circuit output umber of pulse in FPGA, symmetry compensation afterpulse is counted n sExpression formula is as follows:
n s＝n p×k s
In actual use procedure, the linearity compensation coefficient k that will obtain by above-mentioned measuring and calculation p, symmetry penalty coefficient k sWrite FPGA, the umber of pulse of electric current/frequency-conversion circuit output and sub-divided pulse number carry out the real-time linearity, symmetry compensation by FPGA, with the umber of pulse n after compensation sSend to the related application circuit.

Claims (5)

1. electric current/frequency-conversion circuit linearity and symmetry of the figure compensation method is characterized in that: comprise the following steps:
(1) by constant current source to the different current value of electric current/frequency-conversion circuit input, measure and the record coversion circuit in sub-divided pulse number when the corresponding umber of pulse, sub-divided pulse number of d type flip flop output and zero current;
During (2) according to umber of pulse, sub-divided pulse number and zero current, the sub-divided pulse number, determine the linearity compensation coefficient, and the linearity compensation coefficient formula is as follows:
k p = I 2 ( n 1 - m 1 ) - I 1 ( n 2 - m 2 ) I 1 ( m 2 - n 0 ) - I 2 ( m 1 - n 0 )
Wherein, I iBe input current value, m iBe the umber of pulse of d type flip flop output, n iBe sub-divided pulse number, n 0Sub-divided pulse number during for zero current, i=0,1,2, k pBe the linearity compensation coefficient;
(3) according to the linearity compensation coefficient, the sub-divided pulse number that translation circuit is exported carries out linearity real-Time Compensation;
(4) to through the electric current after linearity real-Time Compensation/frequency-conversion circuit input n to different current value+I ' i ,-I ' i, measure and record corresponding pulses number and the sub-divided pulse number of d type flip flop output, described+I ' i ,-I ' i is the identical reversal of size, determines symmetry coefficient and the zero-bit coefficient of electric current/frequency-conversion circuit according to this corresponding pulses number and sub-divided pulse number;
(5) according to symmetry coefficient and zero-bit coefficient, determine the symmetry penalty coefficient, symmetry penalty coefficient formula is as follows:
k s = ( 1 - k 0 ) ( 1 + k 0 + k 2 ) ( 1 + k 0 ) ( 1 - k 0 - k 2 )
Wherein, k 2Be symmetry coefficient, k 0The zero-bit coefficient, k sBe the symmetry penalty coefficient;
(6) according to the symmetry penalty coefficient, the sub-divided pulse number that translation circuit is exported carries out the symmetry real-Time Compensation.
2. electric current according to claim 1/frequency-conversion circuit linearity and symmetry of the figure compensation method is characterized in that: in described step (3), it is as follows that linearity compensation coefficient and linearity compensation afterpulse are counted the formula of relation:
n p＝n i-m i+m i×k p
Wherein, n pBe linearity compensation afterpulse number.
3. electric current according to claim 1/frequency-conversion circuit linearity and symmetry of the figure compensation method, it is characterized in that: in described step (4), the symmetry coefficient of determining electric current/frequency-conversion circuit according to corresponding pulses number and the sub-divided pulse number of d type flip flop output and the process of zero-bit coefficient are, first determine constant multiplier and zero-bit coefficient according to the corresponding pulses number, according to constant multiplier and zero-bit parameter identification symmetry coefficient, each formula is as follows again:
k 1 = Σ i = 1 n ( N + i + N - i ) 2 × n × T - - - ( a )
k 0 = N 0 T - - - ( b )
k 2 = Σ i = 1 n ( N + i - N - i ) 2 × n × T × k 1 - k 0 - - - ( c )
Determine reaching of electric current/frequency-conversion circuit;
Wherein, N + i, N -i, N 0Be respectively input+I ' i,-I ' iWhen reaching zero current, the sub-divided pulse number of translation circuit output, T is the count cycle, n is the right quantity of reversal of getting, k 1Be constant multiplier, k 0Be zero-bit coefficient, k 2Be the symmetry coefficient.
4. electric current according to claim 1/frequency-conversion circuit linearity and symmetry of the figure compensation method is characterized in that: in described step (6), it is as follows that symmetry penalty coefficient and symmetry compensation afterpulse is counted the formula of relation:
n s＝n p×k s
Wherein, n sBe symmetry compensation afterpulse number.
5. according to claim 1～4 described electric current of any one/frequency-conversion circuit linearity and symmetry of the figure compensation methodes, is characterized in that: described current value I i,+I ' iWith-I ' iSpan be to choose according to the range of electric current/frequency-conversion circuit.
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Cited By (6)

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Publication number Priority date Publication date Assignee Title
CN108206688A (en) * 2016-12-16 2018-06-26 航天科工惯性技术有限公司 A kind of automatic shunt I/F conversion circuits exit shunting circuit and method
CN111174810A (en) * 2019-12-31 2020-05-19 中国船舶重工集团公司第七一七研究所 High-precision IF conversion module applied to inertial navigation system
CN111638744A (en) * 2020-04-30 2020-09-08 北京航天时代光电科技有限公司 Current frequency conversion circuit
CN112525189A (en) * 2020-12-22 2021-03-19 重庆华渝电气集团有限公司 Electric zero compensation structure and method of micro current frequency conversion circuit
CN113848453A (en) * 2021-09-09 2021-12-28 湖南航天机电设备与特种材料研究所 I/F circuit linearity calibration method and system
CN113984047A (en) * 2021-10-29 2022-01-28 西安微电子技术研究所 I/F conversion circuit scale factor positive and negative symmetry adjusting method

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108206688A (en) * 2016-12-16 2018-06-26 航天科工惯性技术有限公司 A kind of automatic shunt I/F conversion circuits exit shunting circuit and method
CN108206688B (en) * 2016-12-16 2021-04-27 航天科工惯性技术有限公司 Exit shunt control circuit and method of automatic shunt I/F conversion circuit
CN111174810A (en) * 2019-12-31 2020-05-19 中国船舶重工集团公司第七一七研究所 High-precision IF conversion module applied to inertial navigation system
CN111638744A (en) * 2020-04-30 2020-09-08 北京航天时代光电科技有限公司 Current frequency conversion circuit
CN111638744B (en) * 2020-04-30 2022-05-24 北京航天时代光电科技有限公司 Current frequency conversion circuit
CN112525189A (en) * 2020-12-22 2021-03-19 重庆华渝电气集团有限公司 Electric zero compensation structure and method of micro current frequency conversion circuit
CN112525189B (en) * 2020-12-22 2024-03-12 重庆华渝电气集团有限公司 Electrical zero compensation structure and method of miniature current frequency conversion circuit
CN113848453A (en) * 2021-09-09 2021-12-28 湖南航天机电设备与特种材料研究所 I/F circuit linearity calibration method and system
CN113848453B (en) * 2021-09-09 2023-05-12 湖南航天机电设备与特种材料研究所 I/F circuit linearity calibration method and system
CN113984047A (en) * 2021-10-29 2022-01-28 西安微电子技术研究所 I/F conversion circuit scale factor positive and negative symmetry adjusting method
CN113984047B (en) * 2021-10-29 2023-05-30 西安微电子技术研究所 Method for adjusting positive and negative symmetry of scale factors of I/F conversion circuit

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