CN108206688A - A kind of automatic shunt I/F conversion circuits exit shunting circuit and method - Google Patents
A kind of automatic shunt I/F conversion circuits exit shunting circuit and method Download PDFInfo
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- CN108206688A CN108206688A CN201611170809.4A CN201611170809A CN108206688A CN 108206688 A CN108206688 A CN 108206688A CN 201611170809 A CN201611170809 A CN 201611170809A CN 108206688 A CN108206688 A CN 108206688A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- G—PHYSICS
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
A kind of automatic shunt I/F conversion circuits of present invention offer exit shunting circuit and method, it is realized using FPGA or CPLD, composition includes Clock Managing Unit, direct transition status synchronization d type flip flop, shunts transition status low frequency synchronisation d type flip flop, shunting transition status high-frequency synchronous d type flip flop, count input logic and door, count clearing logic sum gate, synchronous addition counter, exit flow-dividing control logical unit, exiting flow-dividing control latch and unlocking unit and exit flow-dividing control synchronism output d type flip flop.The present invention monitors the size of input current by the timing of input current integration segment, by changing flow-dividing control logical unit, you can split point is exited in change, exits split point setting flexibly, the hysteresis with entering split point can be adjusted arbitrarily as needed；Without increasing peripheral analog circuit, be conducive to the miniaturization of automatic shunt current/frequency conversion circuit, make its application range wider.
Description
Technical field
Shunting circuit and method are exited the present invention relates to a kind of automatic shunt I/F conversion circuits.
Background technology
Current/frequency conversion circuit is mainly used for inertial navigation field, also referred to as I/F conversion circuits, major function be by
Current signal is converted into frequency pulse signal current/frequency conversion circuit proportional therewith and belongs to A/D conversion arts.
There are three types of current/frequency conversion circuits：The first is that input current is directly converted；Second is to input
Electric current is converted after carrying out shunting processing；The third is that input current is directly converted when input current is smaller, works as input
It is converted after carrying out shunting processing to input current when electric current is larger.The third mode is melting for first way and the second way
Close, when the switching between two states be independently accomplished without will extraneous control when, referred to as automatic shunt I/F conversion circuits.
Automatic shunt I/F conversion circuits are related to the switching between two kinds of working conditions：Direct transition status is switched to shunting
Transition status (entering shunting), shunting transition status are switched to direct transition status (exiting shunting), patent CN201854263U
Disclose such conversion circuit.Such circuit exists simultaneously some defects, when SHUNT state is transformed into direct transition status,
Exiting shunting, control is more complicated, to solve the monitoring of input current size, into split point and exit hysteresis between split point
It sets, exit the problems such as SHUNT state is latched with unlock, be such as controlled as described above using analog circuit realization, need to additionally increase conditioning electricity
Road, comparison circuit etc., hardware increase is more, by limitations such as product layout areas, realizes difficult.
Invention content
Shunting circuit and method are exited the object of the present invention is to provide a kind of automatic shunt I/F conversion circuits.It adopts
It is realized with FPGA or CPLD, total digitalization is realized, reduces peripheral circuit, is conducive to product miniaturization.
Technical scheme is as follows：
A kind of automatic shunt I/F conversion circuits exit shunting circuit, are realized using FPGA or CPLD total digitalizations,
It, which is formed, includes Clock Managing Unit, direct transition status synchronization d type flip flop, shunting transition status low frequency synchronisation d type flip flop, divides
Stream transition status high-frequency synchronous d type flip flop counts input logic and door, counts clearing logic sum gate, synchronous addition counter, moves back
Go out flow-dividing control logical unit, exit flow-dividing control latch and unlocking unit and exit flow-dividing control synchronism output D and touch
Send out device；
The shunting transition status low frequency synchronisation d type flip flop and shunting transition status high-frequency synchronous d type flip flop output level
Signal to counting input logic and door, the level signal of the shunting transition status low frequency synchronisation d type flip flop output through NOT gate extremely
It counts and resets logic sum gate；The direct transition status synchronize d type flip flop outputs level signals to count reset logic sum gate with
And exit flow-dividing control latch and unlocking unit；The counting input logic resets logic sum gate with door and counting and outputs signal to
Synchronous addition counter makes synchronous addition counter count or reset；The synchronous addition counter is exported to exiting flow-dividing control
Logical unit, it is described exit flow-dividing control logical unit outputs level signals to exit flow-dividing control latch and unlock
Unit, it is described to exit that flow-dividing control latches and unlocking unit outputs level signals are to exiting flow-dividing control synchronism output d type flip flop,
It is described exit flow-dividing control synchronism output d type flip flop output exit shunt control signal and to count reset logic sum gate.
Wherein, the Clock Managing Unit synchronizes d type flip flop, shunting transition status low frequency synchronisation D for direct transition status
Trigger, shunting transition status high-frequency synchronous d type flip flop count input logic and door, exit flow-dividing control latch and unlock single
Member, exit flow-dividing control synchronism output d type flip flop provide work clock, it is described shunting transition status high-frequency synchronous d type flip flop and
The synchronised clock for counting input logic and door is quadruple groundwork clock, described to exit flow-dividing control latch and unlocking unit
Synchronised clock be octonary groundwork clock.
The input for exiting shunting circuit includes clock, SHUNT state comparison signal, direct transition status and compares
Signal, final output is exits shunt control signal.
The input SHUNT state comparison signal, direct transition status comparison signal are that I/F conversion circuit integrating circuit are defeated
Go out the signal relatively obtained with the threshold level of setting, wherein, when SHUNT state comparison signal is always high level, represent I/F
Conversion circuit is operated in direct conversion work state；When SHUNT state comparison signal becomes low level from high level, represent that I/F turns
Shunting conversion work state will be entered by changing circuit.
It is complete by following steps the present invention also provides the control method that a kind of automatic shunt I/F conversion circuits exit shunting
Into：
S1, SHUNT state comparison signal become low level from high level, represent that I/F conversion circuits will enter shunting conversion work
Make state, the shunting transition status low frequency synchronisation d type flip flop and high-frequency synchronous d type flip flop carry out SHUNT state comparison signal
It is synchronous, and the shunting transition status low frequency synchronisation d type flip flop resets logic sum gate through NOT gate by counting, by synchronous addition meter
Number device is reset；
S2, judge that the output for shunting transition status low frequency synchronisation d type flip flop is high level or low level, if output is
Low level then continues to work under SHUNT state, and passes through counting and reset logic sum gate, and synchronous addition counter is clear
Zero, if output is high level, for count start signal, the output for shunting transition status high-frequency synchronous d type flip flop at this time is also
High level carries out S3；
The output of S3, shunting the transition status low frequency synchronisation d type flip flop and high-frequency synchronous d type flip flop are high level,
It starts counting up synchronous addition counter by counting input logic and door；
S4, judge that the output for shunting transition status high-frequency synchronous d type flip flop is high level or low level, if output is
High level, then synchronous addition counter continue to count, if output for low level, for count stop signal, into S5；
The output of S5, the synchronous addition counter represent I/F conversion circuit input current sizes, with exiting shunting control
The threshold value of logical unit setting processed is compared, if the threshold value of the output of synchronous addition counter not up to setting,
Then continue to repeat S2, if the output of synchronous addition counter reaches the threshold value of setting, carry out S6；
The output of S6, the synchronous addition counter reach the threshold value for exiting the setting of flow-dividing control logical unit
When, the output for exiting flow-dividing control logical unit becomes high level, and shunting instruction is exited at this point, representing to send out, described to move back
Go out flow-dividing control latch and shunting instruction is exited in unlocking unit latch；
S7, it is described exit flow-dividing control latch and unlocking unit output through exiting flow-dividing control synchronism output d type flip flop
It after synchronizing, sends out and exits shunt control signal, and pass through counting and reset logic sum gate, by synchronous addition counter O reset, at this time
The output that the direct transition status synchronizes d type flip flop is low level；
S8, when the output that the direct transition status synchronizes d type flip flop becomes high level, represent that I/F is converted and exit
Shunting, and pass through counting and reset logic sum gate, by synchronous addition counter O reset, at this point, representing that I/F conversion circuits are in direct
Transition status；
S9, unlock exit shunting instruction.
Beneficial effects of the present invention：The present invention exits flow-dividing control using full digital starting, can be real with CPLD or FPGA
It is existing, the size of input current is monitored by the timing of input current integration segment, by changing flow-dividing control logical unit, you can
Split point is exited in change, exits split point setting flexibly, the hysteresis with entering split point can be adjusted arbitrarily as needed；It need not
Increase peripheral analog circuit, be conducive to the miniaturization of automatic shunt I/F conversion circuits, make its application range wider.
Description of the drawings
Fig. 1 exits a kind of embodiment of shunting circuit for a kind of automatic shunt I/F conversion circuits provided by the present invention
Structure diagram；
Fig. 2 is a kind of a kind of structural representation of embodiment for exiting flow-dividing control latch and unlocking unit provided by the invention
Figure；
Fig. 3 exits a kind of embodiment of flow-dividing control method for a kind of automatic shunt I/F conversion circuits provided by the present invention
Flow chart.
Specific embodiment
Illustrate the embodiment of the present invention with reference to the accompanying drawings.It is retouched in the attached drawing of the present invention or a kind of embodiment
The elements and features stated can be combined with elements and features illustrated in one or more other drawings or embodiments.
It should be noted that it in order to understand purpose, is omitted known to unrelated to the invention, those of ordinary skill in the art in attached drawing and explanation
Component and processing expression and description.
Embodiment 1
With reference to figure 1-2, the present embodiment provides a kind of shunting circuits that exits of automatic shunt I/F conversion circuits, use
FPGA or CPLD total digitalizations realize that composition includes：
Clock Managing Unit 1, direct transition status synchronize d type flip flop 2, shunting transition status low frequency synchronisation d type flip flop 3,
It shunts the synchronous d type flip flop 4 of transition status high level frequency, counting input logic and door 5, counting and resets logic sum gate 6, synchronous addition
Counter 7 exits flow-dividing control logical unit 8, exits that flow-dividing control latches and unlocking unit 9, to exit flow-dividing control same
Step output d type flip flop 10 and NOT gate 11.
Further, the input for exiting shunting circuit includes clock, directly SHUNT state comparison signal, conversion
Epidemic situation comparison signal, output is exits shunt control signal.
The input SHUNT state comparison signal, direct transition status comparison signal are that I/F conversion circuit integrating circuit are defeated
Go out the signal relatively obtained with high and low two threshold levels of setting.When the output voltage of integrating circuit is less than the low door set
It rations the power supply usually, SHUNT state comparison signal, direct transition status comparison signal are high level；When the output voltage of integrating circuit
Low-threshold-level higher than setting, less than setting high threshold level when, SHUNT state comparison signal is high level, directly conversion
Epidemic situation comparison signal is low level；When the output voltage of integrating circuit is higher than the high threshold level set, stream mode compares letter
Number, direct transition status comparison signal be low level.When SHUNT state comparison signal is always high level, I/F conversions are represented
Circuit is operated in direct conversion work state；When SHUNT state comparison signal becomes low level from high level, I/F conversion electricity is represented
Road will enter shunting conversion work state.
The Clock Managing Unit 1 synchronizes d type flip flop 2, the D triggerings of shunting transition status low frequency synchronisation for direct transition status
Device 3, shunting transition status high-frequency synchronous d type flip flop 4 count input logic and door 5, exit flow-dividing control latch and unlocking unit
9th, it exits flow-dividing control synchronism output d type flip flop 10 and work clock is provided.
The shunting transition status low frequency synchronisation d type flip flop 3 synchronizes SHUNT state comparison signal, and synchronised clock is
Groundwork clock, 3 outputs level signals of shunting transition status low frequency synchronisation d type flip flop to count input logic and door 5 and
Logic sum gate 6 is reset through the output of NOT gate 11 to counting；
And the shunting transition status high-frequency synchronous d type flip flop 4 synchronizes SHUNT state comparison signal, it is synchronous
Clock is quadruple groundwork clock, and 4 outputs level signals of shunting transition status high-frequency synchronous d type flip flop are patrolled to input is counted
It collects and door 5；
The input for counting input logic and door 5 further includes quadruple groundwork clock.
Specifically,
The output of the shunting transition status low frequency synchronisation d type flip flop 3 is count start signal, if shunting transition status is low
The output of the synchronous d type flip flop 3 of frequency becomes low, and corresponding counting end cycle resets logic sum gate 6 through NOT gate 11 by counting
Synchronous addition counter 7 is reset, is now in shunting working condition；If shunt the defeated of transition status low frequency synchronisation d type flip flop 3
Go out to become high level, then it represents that counting starts, and the end of corresponding feedback current integration segment shunts transition status high-frequency synchronous at this time
The output of d type flip flop 4 is necessarily high level, that is, shunts transition status low frequency synchronisation d type flip flop 3 and high-frequency synchronous d type flip flop 4 will
Synchronous addition counter 7 can be started counting up by counting input logic and door 5；
Further, the output of shunting transition status high-frequency synchronous d type flip flop 4 is count stop signal, becomes low electricity
It usually represents to count to stop, the end of corresponding input current integration segment, quadruple groundwork clock is counts main signal, herein
It is to make timing more accurate using relative high frequency clock；
Further, input logic and 5 outputs level signals of door to synchronous addition counter 7 are counted, synchronous addition counts
The counting effective time of device 7 is input current integration segment, and the time of integration is inversely proportional with input current size, synchronous addition counter
The number more multilist of 7 meters shows that the time is longer, and input current is smaller, and the output of synchronous addition counter 7 represents the input of I/F conversion circuits
Size of current exports to flow-dividing control logical unit 8 is exited, exits flow-dividing control logical unit 8 and set one
A threshold value, the threshold value correspond to some input current value (exiting split point) of I/F conversion circuits, when synchronous addition counts
When the output of device 7 reaches the threshold value for exiting the setting of flow-dividing control logical unit 8, flow-dividing control logical unit is exited
8 output becomes high level, exits shunting instruction at this point, representing to send out, the wherein output of synchronous addition counter 7 is binary system
Number is parallel, and the threshold value is binary number threshold value.
It is described exit 8 outputs level signals of flow-dividing control logical unit to exit flow-dividing control latch and unlocking unit
9, exit that flow-dividing control latches and unlocking unit 9 is exported to exiting flow-dividing control synchronism output d type flip flop 10；Exit flow-dividing control
The output of synchronism output d type flip flop 10 exits shunt control signal and resets logic sum gate 6 to counting.
Specifically,
It is described exit flow-dividing control latch and unlocking unit 9 composition include latch or door 91, unlock and door 92, synchronous D
Trigger 93, NOT gate 94.Exit 8 outputs level signals of flow-dividing control logical unit extremely latch or door 91, latch or door 91
Outputs level signals synchronize d type flip flop 93 to unlock and door 92, unlock and 92 outputs level signals of door to synchronous d type flip flop 93
Output latch to exit flow-dividing control and the output of unlocking unit 9, synchronous 93 outputs level signals of d type flip flop are to latching or door
91, direct transition status synchronizes the outputs level signals of d type flip flop 2 through NOT gate 94 to unlock and door 92.
It is described exit flow-dividing control latch and unlocking unit 9 latch exit shunting instruction, exit flow-dividing control latch and solution
The output of lock unit 9 sends out after exiting flow-dividing control synchronism output d type flip flop 10 and synchronizing and exits shunt control signal, and lead to
It crosses counting and resets logic sum gate 6, synchronous addition counter 7 is reset.
The direct transition status synchronizes d type flip flop 2 and direct transition status comparison signal is synchronized, and synchronised clock is
Groundwork clock, and directly transition status synchronizes 2 outputs level signals of d type flip flop to counting clearing logic sum gate 6 and moves back
Go out flow-dividing control latch and unlocking unit 9；
Specifically,
It exits after shunt control signal sends out, when the output that direct transition status synchronizes d type flip flop 2 becomes high level, table
Show that I/F is converted and exit shunting, and pass through counting and reset logic sum gate 6, synchronous addition counter 7 is reset, at this point, representing
In direct transition status, synchronous addition counter 7 does not work for I/F conversions, and exits flow-dividing control at this time and latch and unlock
Unlock is exited shunting instruction by unit 9.
What outputs level signals described above referred specifically to output is high level or low level.
Embodiment 2
Referring to figs. 2 and 3, the present embodiment provides the control method that a kind of automatic shunt I/F conversion circuits exit shunting, packets
It includes：
S1, SHUNT state comparison signal become low level from high level, represent that I/F conversion circuits will enter shunting conversion work
Make state, shunting transition status low frequency synchronisation d type flip flop 3 and high-frequency synchronous d type flip flop 4 carry out SHUNT state comparison signal same
Step, and shunt transition status low frequency synchronisation d type flip flop 3 and logic sum gate 6 is reset by counting through NOT gate 11, synchronous addition is counted
Device 7 is reset；
Wherein, the input SHUNT state comparison signal, direct transition status comparison signal are I/F conversion circuits integration electricity
Road exports the signal relatively obtained with high and low two threshold levels of setting.When the output voltage of integrating circuit is less than setting
During low-threshold-level, SHUNT state comparison signal, direct transition status comparison signal are high level；When the output of integrating circuit
When low-threshold-level of the voltage higher than setting, the high threshold level less than setting, SHUNT state comparison signal is high level, directly
Transition status comparison signal is low level；When the output voltage of integrating circuit is higher than the high threshold level set, stream mode ratio
It is low level compared with signal, direct transition status comparison signal.When SHUNT state comparison signal is always high level, I/F is represented
Conversion circuit is operated in direct conversion work state；When SHUNT state comparison signal becomes low level from high level, represent that I/F turns
Shunting conversion work state will be entered by changing circuit.
S2, judge that the output for shunting transition status low frequency synchronisation d type flip flop 3 is high level or low level, if output is low,
Then continue to work under SHUNT state, and pass through counting and reset logic sum gate 6, synchronous addition counter 7 is reset, if defeated
Go out for high level, be then count start signal, the output of high-frequency synchronous d type flip flop 4 at this time is also high level, carries out S3；
The output of S3, shunting transition status low frequency synchronisation d type flip flop 3 and high-frequency synchronous d type flip flop 4 are high level,
Synchronous addition counter is started counting up by counting input logic and door 5；
S4, judge that the output for shunting transition status high-frequency synchronous d type flip flop 4 is high level or low level, if output is height
Level, then synchronous addition counter 7 continue to count, if output to be low, for count stop signal, into S5；
The output of S5, synchronous addition counter 7 represent I/F conversion circuit input current sizes, with exiting flow-dividing control
The threshold value that logical unit 8 is set is compared, if the threshold value of the output of synchronous addition counter 7 not up to setting,
Then continue to repeat S2, if the output of synchronous addition counter 7 reaches the threshold value of setting, carry out S6；
When the output of S6, synchronous addition counter 7 reach the threshold value for exiting the setting of flow-dividing control logical unit 8,
The output for exiting flow-dividing control logical unit 8 becomes high level, and shunting instruction is exited at this point, representing to send out；Exit shunting
Control is latched and shunting instruction is exited in the latch of unlocking unit 9；
S7, flow-dividing control latch and the output of unlocking unit 9 are exited through exiting flow-dividing control synchronism output d type flip flop 10 together
It after step, sends out and exits shunt control signal, and pass through counting and reset logic sum gate 6, synchronous addition counter 7 is reset, at this time
The output that direct transition status synchronizes d type flip flop 2 is low level；
S8, when the output that direct transition status synchronizes d type flip flop 2 becomes high level, represent that I/F is converted and exit point
Stream, and pass through to count and reset logic sum gate 6, synchronous addition counter 7 is reset, at this point, representing I/F conversions in directly conversion
State；
S9, unlock exit shunting instruction.
It is described exit flow-dividing control latch and unlocking unit 9 composition include latch or door 91, unlock and door 92, synchronous D
Trigger 93, NOT gate 94.Exit 8 outputs level signals of flow-dividing control logical unit extremely latch or door 91, latch or door 91
Outputs level signals synchronize d type flip flop 93 to unlock and door 92, unlock and 92 outputs level signals of door to synchronous d type flip flop 93
Output latch to exit flow-dividing control and the output of unlocking unit 9, synchronous 93 outputs level signals of d type flip flop are to latching or door
91, direct transition status synchronizes the outputs level signals of d type flip flop 2 through NOT gate 94 to unlock and door 92.
The detailed process of the step S7-S9 is：Exit flow-dividing control logical unit 8 send out exit shunting instruction after
(becoming high level), latches or the output of door 91 becomes high level, at this point, the output that directly transition status synchronizes d type flip flop 2 is
Low level, the output of NOT gate 94 is high level, and unlock and the output of door 92 are high level, in synchronised clock along after arriving, synchronous D
The output of trigger 93 becomes high level, and the output of synchronous d type flip flop 93 protects latch or the output of door 91 to latch or door 91
High level is held, shunting signal latch is exited in realization.The output that direct transition status synchronizes d type flip flop 2 becomes high level, represents I/
F conversions have been completed to exit shunting, and the output unlocked with door 92 is set to low level at this time, so as to synchronize d type flip flop 93
Zero setting is exported, realizes unlock.
According to above-described embodiment, flow-dividing control is exited using digital circuit automatic shunt I/F conversion circuits, is exited
Split point can be adjusted as desired by the threshold value for exiting the setting of flow-dividing control logical unit, not need to outer boxing
Intend circuit, can be realized using CPLD or FPGA, the component part of CPLD or FPGA inherently I/F conversion circuits, this method
Be conducive to the miniaturization of product.
Although the present invention and its advantage is described in detail it should be appreciated that without departing from by appended claim
Various changes, replacement and transformation can be carried out in the case of the spirit and scope of the present invention limited.Moreover, the model of the application
Enclose the specific embodiment for being not limited only to the described process of specification, equipment, means, method and steps.In the art is common
Technical staff performs and corresponding reality described herein from the disclosure it will be readily understood that can be used according to the present invention
Apply the essentially identical function of example or obtain process essentially identical with it result, existing and that future is to be developed, equipment,
Means, method or step.Therefore, appended claim purport includes such process, equipment, hand in the range of them
Section, method or step.
Claims (9)
1. a kind of automatic shunt I/F conversion circuits exit shunting circuit, it is characterised in that：Including Clock Managing Unit,
Direct transition status synchronizes d type flip flop, shunting transition status low frequency synchronisation d type flip flop, the D triggerings of shunting transition status high-frequency synchronous
Device, count input logic and door, count clearing logic sum gate, synchronous addition counter, exit flow-dividing control logical unit,
It exits flow-dividing control latch and unlocking unit and exits flow-dividing control synchronism output d type flip flop；
The shunting transition status low frequency synchronisation d type flip flop and shunting transition status high-frequency synchronous d type flip flop outputs level signals
To input logic and door is counted, the level signal of the shunting transition status low frequency synchronisation d type flip flop output is through NOT gate to counting
Reset logic sum gate；The direct transition status synchronizes d type flip flop outputs level signals to counting and resets logic sum gate and move back
Go out flow-dividing control latch and unlocking unit；The counting input logic outputs signal to synchronous with door and counting clearing logic sum gate
Up counter makes synchronous addition counter count or reset；The synchronous addition counter is exported to exiting flow-dividing control logic
Arithmetic element, it is described to exit flow-dividing control logical unit outputs level signals flow-dividing control latches and unlock is single to exiting
Member, it is described to exit that flow-dividing control latches and unlocking unit outputs level signals are to exiting flow-dividing control synchronism output d type flip flop, institute
State exit flow-dividing control synchronism output d type flip flop output exit shunt control signal and to count reset logic sum gate.
2. a kind of automatic shunt I/F conversion circuits according to claim 1 exit shunting circuit, feature exists
In：The Clock Managing Unit synchronizes d type flip flop, shunting transition status low frequency synchronisation d type flip flop, shunting for direct transition status
Transition status high-frequency synchronous d type flip flop, counting input logic and door exit flow-dividing control latch and unlocking unit, exit shunting
Synchronism output d type flip flop is controlled to provide work clock, the shunting transition status high-frequency synchronous d type flip flop and counting input logic
It is quadruple groundwork clock with the synchronised clock of door, it is described to exit that flow-dividing control latches and the synchronised clock of unlocking unit is
Octonary groundwork clock.
3. a kind of automatic shunt I/F conversion circuits according to claim 1 or 2 exit shunting circuit, feature
It is：The output of the shunting transition status low frequency synchronisation d type flip flop represents count start signal, if shunting transition status low frequency
The output of synchronous d type flip flop becomes high level, then it represents that counting starts；The shunting transition status high-frequency synchronous d type flip flop
Output represents count stop signal, becomes low level and represents to count stopping.
4. shunting circuit is exited according to a kind of automatic shunt I/F conversion circuits of claim 1-3 any one of them,
It is characterized in that：It is described to exit that flow-dividing control latches and the composition of unlocking unit includes latching or door, unlock and door, synchronous D triggerings
Device and NOT gate；It is described to exit flow-dividing control logical unit outputs level signals extremely latch or door, latch or door output level
For signal to unlocking with door, unlock and door outputs level signals to synchronous d type flip flop, the output for synchronizing d type flip flop is to exit shunting
Control is latched and the output of unlocking unit, and to latch or door, direct transition status synchronizes synchronous d type flip flop also outputs level signals
D type flip flop outputs level signals are through NOT gate to unlock and door.
5. shunting circuit is exited according to a kind of automatic shunt I/F conversion circuits of claim 1-4 any one of them,
It is characterized in that：The input for exiting shunting circuit includes clock, SHUNT state comparison signal, direct transition status and compares
Signal, final output is exits shunt control signal.
6. shunting circuit is exited according to a kind of automatic shunt I/F conversion circuits of claim 1-5 any one of them,
It is characterized in that：The shunting circuit that exits is realized using FPGA or CPLD total digitalizations.
7. a kind of automatic shunt I/F conversion circuits exit the control method of shunting, which is characterized in that include the following steps：
S1, SHUNT state comparison signal become low level from high level, represent that I/F conversion circuits will enter shunting conversion work shape
State, the shunting transition status low frequency synchronisation d type flip flop and high-frequency synchronous d type flip flop carry out SHUNT state comparison signal same
Step, and the shunting transition status low frequency synchronisation d type flip flop resets logic sum gate through NOT gate by counting, and synchronous addition is counted
Device is reset；
S2, judge that the output for shunting transition status low frequency synchronisation d type flip flop is high level or low level, if output is low electricity
It is flat, then continue to work under SHUNT state, and pass through counting and reset logic sum gate, by synchronous addition counter O reset, if
It exports as high level, is then count start signal, the output for shunting transition status high-frequency synchronous d type flip flop at this time is also high electricity
It is flat, carry out S3；
The output of S3, shunting the transition status low frequency synchronisation d type flip flop and high-frequency synchronous d type flip flop are high level, are led to
Crossing counting input logic and door starts counting up synchronous addition counter；
S4, judge that the output for shunting transition status high-frequency synchronous d type flip flop is high level or low level, if output is high electricity
Flat, then synchronous addition counter continues to count, if output is low level, for count stop signal, into S5；
The output of S5, the synchronous addition counter represent I/F conversion circuit input current sizes, are patrolled with exiting flow-dividing control
The threshold value for collecting arithmetic element setting is compared, if the threshold value of the output of synchronous addition counter not up to setting, after
It is continuous to repeat S2, if the output of synchronous addition counter reaches the threshold value of setting, carry out S6；
When the output of S6, the synchronous addition counter reach the threshold value for exiting the setting of flow-dividing control logical unit, move back
The output for going out flow-dividing control logical unit becomes high level, and shunting instruction is exited at this point, representing to send out, described to exit shunting
Control is latched and shunting instruction is exited in unlocking unit latch；
S7, it is described exit flow-dividing control latch and unlocking unit output through exit flow-dividing control synchronism output d type flip flop synchronize
Afterwards, it sends out and exits shunt control signal, and pass through counting and reset logic sum gate, it is described at this time by synchronous addition counter O reset
The output that direct transition status synchronizes d type flip flop is low level；
S8, when the output that the direct transition status synchronizes d type flip flop becomes high level, represent that I/F is converted and exit shunting,
And pass through counting and reset logic sum gate, by synchronous addition counter O reset, at this point, representing I/F conversions in direct transition status；
S9, unlock exit shunting instruction.
8. according to the method described in claim 6, it is characterized in that：The composition for exiting flow-dividing control latch and unlocking unit
Including latch or door, unlock and door, synchronous d type flip flop and NOT gate；It is described to exit flow-dividing control logical unit output level
Signal latches to latch or door or door outputs level signals to unlock is triggered with door, unlock and door outputs level signals to synchronous D
Device, the output of synchronous d type flip flop is exits flow-dividing control latch and the output of unlocking unit, synchronous d type flip flop also output level
For signal to latch or door, direct transition status synchronizes d type flip flop outputs level signals through NOT gate to unlock and door.
9. according to the method described in claim 7, it is characterized in that：It is described exit flow-dividing control logical unit and send out exit
It after shunting instruction, latches or the output of door becomes high level, at this point, the output that directly transition status synchronizes d type flip flop is low electricity
Flat, the output of NOT gate is high level, and unlock and the output of door are high level, in synchronised clock along after arriving, synchronous d type flip flop
Output becomes high level, and the output of synchronous d type flip flop makes latch or the output of door keep high level, realization is moved back to latch or door
Go out shunting signal latch；The output that direct transition status synchronizes d type flip flop becomes high level, represents that I/F conversion circuits are complete
Into shunting is exited, the output unlocked with door is set to low level at this time, so as to which the output zero setting of d type flip flop will be synchronized, realizes solution
Lock.
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| CN105659812B (en) * | 2006-12-29 | 2009-07-01 | 北京航天时代光电科技有限公司 | Marine integral fiber-optic gyroscope strapdown vertical reference system |
| JP2010217941A (en) * | 2009-03-13 | 2010-09-30 | Rohm Co Ltd | Data processor |
| CN201854263U (en) * | 2010-09-29 | 2011-06-01 | 航天科工惯性技术有限公司 | High-accuracy current frequency conversion circuit based on double-integrator |
| CN102539831A (en) * | 2012-02-17 | 2012-07-04 | 北京航天自动控制研究所 | Signal conversion device for accelerometer in strapdown inertial navigation system |
| CN103135650A (en) * | 2013-01-21 | 2013-06-05 | 湖北航天技术研究院总体设计所 | Current/frequency conversion circuit linearity and symmetry digital compensation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105659812B (en) * | 2006-12-29 | 2009-07-01 | 北京航天时代光电科技有限公司 | Marine integral fiber-optic gyroscope strapdown vertical reference system |
| JP2010217941A (en) * | 2009-03-13 | 2010-09-30 | Rohm Co Ltd | Data processor |
| CN201854263U (en) * | 2010-09-29 | 2011-06-01 | 航天科工惯性技术有限公司 | High-accuracy current frequency conversion circuit based on double-integrator |
| CN102539831A (en) * | 2012-02-17 | 2012-07-04 | 北京航天自动控制研究所 | Signal conversion device for accelerometer in strapdown inertial navigation system |
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